forked from Apple-2-HW/GR8RAM
f471e04244
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502. |
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|---|---|---|
| .. | ||
| db | ||
| incremental_db | ||
| output_files | ||
| GR8RAM.qpf | ||
| GR8RAM.qsf | ||
| GR8RAM.qws | ||
| GR8RAM.v | ||