forked from Apple-2-HW/GR8RAM
f471e04244
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
220 lines
7.3 KiB
Verilog
Executable File
220 lines
7.3 KiB
Verilog
Executable File
module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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A, RA, nWE, D, RD,
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nDEVSEL, nIOSEL, nIOSTRB, nINH,
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nRAS, nCAS0, nCAS1, nRCS, nROE, nRWE);
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/* Clock, Reset, Mode */
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input C7M, C7M_2, Q3, PHI0in, PHI1in; // Clock inputs
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input nRES, nMode; // Reset, mode
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/* PHI1 Delay */
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wire [8:0] PHI1b;
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wire PHI1;
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LCELL PHI1b0_MC (.in(PHI1in), .out(PHI1b[0]));
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LCELL PHI1b1_MC (.in(PHI1b[0]), .out(PHI1b[1]));
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LCELL PHI1b2_MC (.in(PHI1b[1]), .out(PHI1b[2]));
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LCELL PHI1b3_MC (.in(PHI1b[2]), .out(PHI1b[3]));
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LCELL PHI1b4_MC (.in(PHI1b[3]), .out(PHI1b[4]));
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LCELL PHI1b5_MC (.in(PHI1b[4]), .out(PHI1b[5]));
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LCELL PHI1b6_MC (.in(PHI1b[5]), .out(PHI1b[6]));
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LCELL PHI1b7_MC (.in(PHI1b[6]), .out(PHI1b[7]));
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LCELL PHI1b8_MC (.in(PHI1b[7]), .out(PHI1b[8]));
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LCELL PHI1b9_MC (.in(PHI1b[8] & PHI1in), .out(PHI1));
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/* Address Bus, etc. */
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input nDEVSEL, nIOSEL, nIOSTRB; // Card select signals
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input [15:0] A; // 6502 address bus
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input nWE; // 6502 R/W
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output [10:0] RA; // DRAM/ROM address
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assign RA[10:8] = ASel ? Addr[21:19] : Addr[10:8];
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assign RA[7:0] = (~nIOSTRB & FullIOEN) ? Bank+1 :
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(~nIOSTRB & ~FullIOEN) ? {7'b0000001, Bank[0]} :
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(~ASel & nIOSEL & nIOSTRB) ? Addr[18:11] :
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(ASel & nIOSEL & nIOSTRB) ? Addr[7:0] : 8'h00;
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/* Select Signals */
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wire BankSELA = A[3:0]==4'hF;
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wire SetSELA = A[3:0]==4'hE;
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wire RAMSELA = A[3:0]==4'h3;
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wire AddrHSELA = A[3:0]==4'h2;
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wire AddrMSELA = A[3:0]==4'h1;
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wire AddrLSELA = A[3:0]==4'h0;
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LCELL BankWR_MC (.in(BankSELA & ~nWE & ~nDEVSEL & REGEN), .out(BankWR)); wire BankWR;
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wire SetWR = SetSELA & ~nWE & ~nDEVSEL & REGEN;
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LCELL RAMSEL_MC (.in(RAMSELA & ~nDEVSEL & REGEN), .out(RAMSEL)); wire RAMSEL;
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LCELL AddrHWR_MC (.in(AddrHSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrHWR)); wire AddrHWR;
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LCELL AddrMWR_MC (.in(AddrMSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrMWR)); wire AddrMWR;
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LCELL AddrLWR_MC (.in(AddrLSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrLWR)); wire AddrLWR;
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/* Data Bus Routing */
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// DRAM/ROM data bus
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wire RDOE = CSDBEN & ~nWE;
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inout [7:0] RD = RDOE ? D[7:0] : 8'bZ;
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// Apple II data bus
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wire DOE = CSDBEN & nWE &
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((~nDEVSEL & REGEN) | ~nIOSEL | (~nIOSTRB & IOROMEN));
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wire [7:0] Dout = (nDEVSEL | RAMSELA) ? RD[7:0] :
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AddrHSELA ? {Addr[23:16]} :
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AddrMSELA ? Addr[15:8] :
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AddrLSELA ? Addr[7:0] : 8'h00;
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inout [7:0] D = DOE ? Dout : 8'bZ;
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/* Inhibit output */
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wire AROMSEL;
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LCELL AROMSEL_MC (.in(/*(A[15:12]==4'hD | A[15:12]==4'hE | A[15:12]==4'hF) & nWE & ~MODE*/0), .out(AROMSEL));
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output nINH = AROMSEL ? 1'b0 : 1'bZ;
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/* DRAM and ROM Control Signals */
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output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSDBEN); // ROM chip select
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output nROE = ~nWE; // need this for flash ROM
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output nRWE = nWE | (nDEVSEL & nIOSEL & nIOSTRB); // for ROM & DRAM
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output nRAS = ~(RASr | RASf);
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output nCAS0 = ~(CAS0f | (CASr & RAMSEL & ~Addr[22])); // DRAM CAS bank 0
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output nCAS1 = ~(CAS1f | (CASr & RAMSEL & Addr[22])); // DRAM CAS bank 1
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/* 6502-accessible Registers */
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reg [7:0] Bank = 0; // Bank register for ROM access
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reg [23:0] Addr = 0; // RAM address register
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/* Increment Control */
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reg IncAddrL = 0, IncAddrM = 0, IncAddrH = 0;
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/* CAS rising/falling edge components */
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reg CASr = 0, CAS0f = 0, CAS1f = 0;
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reg RASr = 0, RASf = 0;
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/* State Counters */
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reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
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reg PHI0seen = 0; // Have we seen PHI0 since reset?
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reg [2:0] S = 0; // State counter
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reg [3:0] Ref = 0; // Refresh skip counter
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/* Misc. */
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reg REGEN = 0; // Register enable
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reg IOROMEN = 0; // IOSTRB ROM enable
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reg CSDBEN = 0; // ROM CS, data bus driver gating
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reg ASel = 0; // DRAM address multiplexer select
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reg FullIOEN = 0;
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// Apple II Bus Compatibiltiy Rules:
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// Synchronize to PHI0 or PHI1. (PHI1 here)
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// PHI1's edge may be -20ns,+10ns relative to C7M.
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// Delay the rising edge of PHI1 to get enough hold time:
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// PHI1modified = PHI1 & PHI1delayed;
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// Only sample /DEVSEL, /IOSEL at these times:
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// 2nd and 3rd rising edge of C7M in PHI0 (S4, S5)
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// all 3 falling edges of C7M in PHI0 (S4, S5, S6)
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// Can sample /IOSTRB at same times as /IOSEL, plus:
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// 1st rising edge of C7M in PHI0 (S3)
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always @(posedge C7M, negedge nRES) begin
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if (~nRES) begin // Reset
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PHI1reg <= 0;
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PHI0seen <= 0;
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S <= 0;
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Ref <= 0;
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REGEN <= 0;
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IOROMEN <= 0;
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CSDBEN <= 0;
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end else begin
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// Synchronize state counter to S1 when just entering PHI1
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PHI1reg <= PHI1; // Save old PHI1
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if (~PHI1) PHI0seen <= 1; // PHI0seen set in PHI0
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S <= (PHI1 & ~PHI1reg & PHI0seen) ? 4'h1 :
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S==0 ? 3'h0 :
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S==7 ? 3'h7 : S+1;
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// Refresh counter allows DRAM refresh once every 13 cycles
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if (S==3) Ref <= (Ref[3:2]==2'b11) ? 4'h0 : Ref+1;
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// Disable IOSTRB ROM when accessing 0xCFFF.
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if (S==3 & ~nIOSTRB & A[10:0]==11'h7FF) IOROMEN <= 1'b0;
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// Registers enabled at end of S4 by any IOSEL access (Cn00-CnFF).
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if (S==4 & ~nIOSEL) REGEN <= 1;
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// Enable IOSTRB ROM when accessing CnXX in IOSEL ROM.
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if (S==4 & ~nIOSEL) IOROMEN <= 1'b1;
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// Only drive Apple II data bus after state 4 to avoid bus fight.
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// Thus we wait 1.5 7M cycles (210 ns) into PHI0 before driving.
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// Same for driving the ROM/SRAM data bus (RD).
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// Similarly, only select the ROM chip starting at the end of S4.
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// This provides address setup time for write operations and
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// minimizes power consumption.
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CSDBEN <= S==4 | S==5 | S==6 | S==7;
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end
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end
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always @(negedge C7M, negedge nRES) begin
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if (~nRES) begin
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Addr <= 0;
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Bank <= 0;
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FullIOEN <= 0;
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IncAddrL <= 0;
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IncAddrM <= 0;
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IncAddrH <= 0;
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end else begin
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// Increment address register
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if (S==1 & IncAddrL) begin
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Addr[7:0] <= Addr[7:0]+1;
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IncAddrL <= 0;
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IncAddrM <= Addr[7:0] == 8'hFF;
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end
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if (S==2 & IncAddrM) begin
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Addr[15:8] <= Addr[15:8]+1;
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IncAddrM <= 0;
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IncAddrH <= Addr[15:8] == 8'hFF;
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end
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if (S==3 & IncAddrH) begin
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IncAddrH <= 0;
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Addr[23:16] <= Addr[23:16]+1;
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end
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// Set register in middle of S6 if accessed.
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if (S==6) begin
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if (BankWR) Bank[7:0] <= D[7:0]; // Bank
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if (SetWR) FullIOEN <= D[7:0] == 8'hE5;
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IncAddrL <= RAMSEL;
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IncAddrM <= AddrLWR & Addr[7] & ~D[7];
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IncAddrH <= AddrMWR & Addr[15] & ~D[7];
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if (AddrHWR) Addr[23:16] <= D[7:0]; // Addr hi
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if (AddrMWR) Addr[15:8] <= D[7:0]; // Addr mid
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if (AddrLWR) Addr[7:0] <= D[7:0]; // Addr lo
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end
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end
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end
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/* DRAM RAS/CAS */
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always @(posedge C7M, negedge nRES) begin
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if (~nRES) begin
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RASr <= 1'b0; ASel <= 1'b0; CASr <= 1'b0;
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end else begin
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RASr <= (S==1 & Ref==0) | // Refresh
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(S==4 & RAMSEL & nWE) | // Read: Early RAS
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(S==5 & RAMSEL & ~nWE); // Write: Late RAS
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// Multiplex DRAM address in at end of S4 through S6.
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ASel = (RAMSEL & nWE & S==4) | // Read: mux address early
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(RAMSEL & ~nWE & S==5); // Write: mux address late
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// Read: long, early CAS, gated later by RAMSEL
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CASr <= (RAMSEL & ~nWE & (S==5 | S==6 | S==7));
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end
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end
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always @(negedge C7M, negedge nRES) begin
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if (~nRES) begin RASf <= 1'b0; CAS0f <= 1'b0; CAS1f <= 1'b0;
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end else begin
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RASf <= (S==4 & RAMSEL & nWE) | // Read: Early RAS
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(S==5 & RAMSEL & ~nWE); // Write: Late RAS
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CAS0f <= (S==1 & Ref==0) | // Refresh
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(S==6 & RAMSEL & ~Addr[22] & ~nWE); // Write: Late CAS
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CAS1f <= (S==1 & Ref==0) | // Refresh
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(S==6 & RAMSEL & Addr[22] & ~nWE); // Write: Late CAS
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end
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end
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endmodule
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