GR8RAM/cpld/output_files/GR8RAM.sta.summary
Zane Kaminski f471e04244 New PLD revision
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 15:07:38 -04:00

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TimeQuest Timing Analyzer Summary
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Type : Setup 'C7M'
Slack : -47.500
TNS : -2169.500
Type : Hold 'C7M'
Slack : 5.000
TNS : 0.000
Type : Minimum Pulse Width 'C7M'
Slack : -4.500
TNS : -486.000
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