471 lines
12 KiB
Plaintext
471 lines
12 KiB
Plaintext
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[[Info]]
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_PARENT: none
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_FAMILY: xo2c00
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_FILE_FORMAT: 1.00
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_DATA_VALUES: 1.00
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_STATUS: Advanced
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[[Project]]
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DesignName: top
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Family: MachXO2
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Device: LCMXO2-640HC
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Package: TQFP100
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Operating: Commercial
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Version: 8.0
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Performance: -4
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PartName: LCMXO2-640HC-4TG100C
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[[Settings]]
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EstimationMode: Medium
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ProcessType: Typical
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SoftwareMode: Calculation
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TempAmbX: Ambient Temperature
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SectionY: Total Power
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SectionX: Vcc
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SectionLowerLimit: 0.0000
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SectionUpperLimit: 0.0000
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SectionResolution: 0.0000
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TempAmbY: Ambient Temperature
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TempAmbLowerLimit: -30.0000
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TempAmbUpperLimit: 115.0000
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TempAmbResolution: 29.0000
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FreqY: Total Power
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FreqX: No Clocks Found!
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FreqLowerLimit: 10.0000
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FreqUpperLimit: 100.0000
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FreqAmbResolution: 20.0000
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PowerMode: Normal
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DisableBandgap: false
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DisablePor: false
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DisableDll: false
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DisableOsc: false
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DisablePLL0: false
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DisablePLL1: false
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DisableInRd0: false
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DisableInRd1: false
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DisableInRd2: false
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DisableInRd3: false
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DisableInRd4: false
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DisableInRd5: false
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DisableInRd6: false
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DisableInRd7: false
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EnablePg0: false
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EnablePg1: false
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EnablePg2: false
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EnablePg3: false
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EnablePg4: false
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EnablePg5: false
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EnablePg6: false
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EnablePg7: false
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DisableLVDS: false
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DisableLVDS1: false
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DisableLVDS2: false
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DisableLVDS3: false
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DisableLVDS4: false
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DisableLVDS5: false
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DisableLVDS6: false
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DisableLVDS7: false
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[[Thermal]]
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Airflow: 200 LFM
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AmbientTemperature: 25
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CustomThetaSA: -1
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JunctionTemperature: 25.19
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MaxSafeAmbient: 84.67
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ThetaBA: 10.0
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ThetaCS: 0
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ThetaEffective: 16.65
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ThetaJA: 20.59
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ThetaJB: 12.88
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ThetaJC: 0
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ThetaSA: -1
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UserThetaBA: No
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UserThetaCS: No
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UserThetaEffective: No
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UserThetaJA: No
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UserThetaJB: No
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UserThetaJC: No
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UserThetaSA: No
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thetaBoard: Medium Board
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thetaHeatSink: No Heat Sink
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thetaOption: ThermalModels
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[[VDPM]]
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Supply = Voltage, DPM
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Vcc = 3.300, 1.00
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Vccio 3.3 = 3.300, 1.00
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Vccio 2.5 = 2.500, 1.00
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Vccio 1.8 = 1.800, 1.00
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Vccio 1.5 = 1.500, 1.00
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Vccio 1.2 = 1.200, 1.00
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[[Logic]]
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Clk = F, AF, LUT, RAM, RIPPLE, REG, X0, X1, X2, X6, ISB, ISBLUT, ISBCE, ISBLSR, ISBM, ISBCLK
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COMBINATORIAL = 7.0000, 10.0000^d^, 56, 0, 0, 0, 59, 23, 123, 31, 119, 70, 16, 6, 9, 2
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_devsel_c = 1.0000, 10.0000^d^, 15, 0, 0, 8, 18, 18, 55, 9, 61, 49, 8, 3, 1, 8
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fclk_c = 7.0000, 10.0000^d^, 43, 0, 0, 35, 50, 25, 66, 18, 301, 290, 5, 5, 1, 23
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[[Clocks]]
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Clk = F, Duty, Pfeed, Ptrunk, Pspine, Ptap, Pbranch, Strunk, Sspine, Stap, Sbranch, Etb, Ebg, Elr
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_devsel_c = 1.0000, 50.0000, 0, 0, 0, 0, 0, t4_1, c13_1, r4_2, b_10, 0, 0, 0
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fclk_c = 7.0000, 50.0000, 0, t3_1, s13_1, p13_1_p17_1, c14_4_c17_4, 0, 0, 0, b_0, 0, 0, 0
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[[Input Output]]
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Clk = _Type, _Mode, F, AF, IP, OP, PG, Cload, Bank, _ActualMode, _Pull, X0, X1, X2, X6, ISB
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COMBINATORIAL = LVCMOS25, none, 7.0000, 10.0000^d^, 4, 0, OFF, 5, 2, none, DOWN, 0, 0, 0, 0, 0
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COMBINATORIAL = LVCMOS25, none, 7.0000, 10.0000^d^, 11, 0, OFF, 5, 1, none, DOWN, 0, 0, 0, 0, 0
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COMBINATORIAL = LVCMOS25, none, 7.0000, 10.0000^d^, 5, 0, OFF, 5, 0, none, DOWN, 0, 0, 0, 0, 0
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COMBINATORIAL = LVCMOS25-8mA-SLEW:SLOW, none, 7.0000, 10.0000^d^, 0, 2, N/A, 5, 2, none, DOWN, 0, 0, 0, 0, 0
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_devsel_c = LVCMOS25-8mA-SLEW:SLOW, none, 1.0000, 10.0000^d^, 0, 1, N/A, 5, 1, none, DOWN, 0, 0, 0, 0, 0
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_devsel_c = LVCMOS25-8mA-SLEW:SLOW, none, 1.0000, 10.0000^d^, 0, 2, N/A, 5, 0, none, DOWN, 0, 0, 0, 0, 0
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_devsel_c = LVCMOS25-8mA-SLEW:SLOW, none, 1.0000, 10.0000^d^, 0, 4, N/A, 5, 3, none, DOWN, 0, 0, 0, 0, 0
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_devsel_c = LVCMOS25-8mA-SLEW:SLOW, none, 1.0000, 10.0000^d^, 0, 10, N/A, 5, 2, none, DOWN, 0, 0, 0, 0, 0
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_devsel_c = LVCMOS25, none, 1.0000, 10.0000^d^, 1, 0, OFF, 5, 3, none, UP, 0, 0, 0, 0, 0
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fclk_c = LVCMOS25-8mA-SLEW:SLOW, none, 7.0000, 10.0000^d^, 0, 1, N/A, 5, 0, none, DOWN, 0, 0, 0, 0, 0
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fclk_c = LVCMOS25, none, 7.0000, 10.0000^d^, 1, 0, OFF, 5, 2, none, DOWN, 0, 0, 0, 0, 0
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[[Bidi]]
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ClkInpName = _Type, _Mode, InpF, InpAF, Bidi, PG, ClkOutName, OutF, OutAF, Duty, Cload, Bank, _ActualMode, _Pull, X0, X1, X2, X6, ISB
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COMBINATORIAL = LVCMOS25-8mA-SLEW:SLOW, none, 7.0000, 10.0000^d^, 5, OFF, N/A, 0.0000^d^, 10.0000^d^, 50, 5, 1, none, DOWN, 0, 0, 0, 0, 0
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_devsel_c = LVCMOS25-8mA-SLEW:SLOW, none, 1.0000, 10.0000^d^, 3, OFF, N/A, 0.0000^d^, 10.0000^d^, 50, 5, 1, none, DOWN, 0, 0, 0, 0, 0
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[[Bank Voltage]]
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Bank = Voltage, InRD, LVDSO, PG
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0 = Vccio 2.5, No, No, OFF
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1 = Vccio 2.5, No, N/A, OFF
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2 = Vccio 2.5, No, N/A, OFF
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3 = Vccio 2.5, No, N/A, OFF
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[[Termination]]
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_Type = IP, OP, Bidi, Duty, Bank, Rth, Vth
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LVCMOS25 = 5, 0, 0, 0.0, 2, 1.0E12, 0
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LVCMOS25 = 11, 0, 0, 0.0, 1, 1.0E12, 0
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LVCMOS25 = 5, 0, 0, 0.0, 0, 1.0E12, 0
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LVCMOS25-8mA-SLEW:SLOW = 0, 12, 0, 0.0, 2, 1.0E12, 0
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LVCMOS25-8mA-SLEW:SLOW = 0, 1, 8, 31.8, 1, 1.0E12, 0
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LVCMOS25-8mA-SLEW:SLOW = 0, 3, 0, 0.0, 0, 1.0E12, 0
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LVCMOS25-8mA-SLEW:SLOW = 0, 4, 0, 0.0, 3, 1.0E12, 0
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LVCMOS25 = 1, 0, 0, 0.0, 3, 1.0E12, 0
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[[SP RAM]]
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Clk = EBR, F, AF, _Type, X0, X1, X2, X6, ISB
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[[DP RAM]]
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RdClk = RdF, RdAF, EBR, WrClk, WrF, WrAF, _TypeA, _TypeB, X0, X1, X2, X6, ISB
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[[DP RAM True]]
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ClkA = aF, aAF, EBR, ClkB, bF, bAF, _TypeA, _TypeB, X0, X1, X2, X6, ISB
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fclk_c = 7.0000, 10.0000^d^, 2, NoNe, 0.0000^d^, 10.0000^d^, DP8KC_NORM_PORTA, DP8KC_NORM_PORTB, 0, 0, 0, 0, 0
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[[FIFO DC]]
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RdClk = RdF, RdAF, EBR, WrClk, WrF, WrAF, _TypeA, _TypeB, X0, X1, X2, X6, ISB
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[[I2C1]]
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Clk = F, AF, I2C1
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[[I2C2]]
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Clk = F, AF, I2C2
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[[SPI]]
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Clk = F, AF, SPI
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[[TC]]
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Clk = F, AF, TC, WBUSED
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[[UFM]]
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Clk = F, AF, UFM
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[[WISHBONE]]
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Clk = F, AF, WISHBONE
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[[CLKDIV]]
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Clk = F, AF, CLKDIV
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[[CIBTEST]]
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CIBTEST =
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0 =
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[[MCLK]]
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STANDBY = Clk, F, AF, MCLK, MCLKF, SEDF
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No = _CLKNAME, 266.0000, 100.0000, 1, 2.0800, 2.0800
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[[POR]]
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STANDBY =
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No =
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[[BANDGAP]]
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STANDBY =
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No =
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[[JTAG]]
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Clk = F, AF, Input, Output
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COMBINATORIAL = 7.0000, 100.0000, 3, 1
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[[SED]]
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_Mode = SED, STATUS
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SEDFA = 0, Disabled
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[[PLL Clock]]
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Out = In
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[[Connections]]
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Clock = Comp, Type
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COMBINATORIAL = myIwm/SLICE_31, 0
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COMBINATORIAL = data[5], 1
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COMBINATORIAL = data[3], 1
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COMBINATORIAL = data[2], 1
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COMBINATORIAL = data[1], 1
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COMBINATORIAL = data[0], 1
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COMBINATORIAL = _wrreq, 1
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COMBINATORIAL = debugInfo[0], 1
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_devsel_c = _devsel, 1
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_devsel_c = spi_clk, 1
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_devsel_c = spi_mosi, 1
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_devsel_c = spi_cs, 1
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_devsel_c = debugInfo[7], 1
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_devsel_c = debugInfo[6], 1
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_devsel_c = debugInfo[5], 1
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_devsel_c = debugInfo[4], 1
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_devsel_c = debugInfo[3], 1
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_devsel_c = debugInfo[2], 1
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_devsel_c = debugInfo[1], 1
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_devsel_c = _en245, 1
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_devsel_c = phase[0], 1
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_devsel_c = data[7], 1
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_devsel_c = data[6], 1
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_devsel_c = data[4], 1
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_devsel_c = phase[2], 1
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_devsel_c = phase[3], 1
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_devsel_c = _enbl1, 1
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_devsel_c = _enbl2, 1
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_devsel_c = phase[1], 1
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fclk_c = fclk, 1
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fclk_c = wrdata, 1
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[[Hierarchical Connections]]
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Key = Name, Type
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SIGNAL = COMBINATORIAL, DUMMY
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INPUT = myIwm/SLICE_31, SLICE
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INPUT = myIwm/SLICE_32, SLICE
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INPUT = myIwm/SLICE_34, SLICE
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INPUT = myIwm/SLICE_35, SLICE
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INPUT = SLICE_36, SLICE
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INPUT = myIwm/SLICE_37, SLICE
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INPUT = myIwm/SLICE_38, SLICE
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INPUT = myIwm/SLICE_40, SLICE
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INPUT = myIwm/SLICE_41, SLICE
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INPUT = myIwm/SLICE_42, SLICE
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INPUT = myIwm/SLICE_44, SLICE
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INPUT = myIwm/SLICE_45, SLICE
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INPUT = myIwm/SLICE_46, SLICE
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INPUT = myIwm/SLICE_47, SLICE
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INPUT = myIwm/SLICE_48, SLICE
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INPUT = SLICE_49, SLICE
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INPUT = myIwm/SLICE_50, SLICE
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INPUT = myIwm/SLICE_52, SLICE
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INPUT = myIwm/SLICE_54, SLICE
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INPUT = myIwm/SLICE_55, SLICE
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INPUT = myIwm/SLICE_56, SLICE
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INPUT = myIwm/SLICE_59, SLICE
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INPUT = myIwm/SLICE_60, SLICE
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INPUT = myIwm/SLICE_61, SLICE
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INPUT = myIwm/SLICE_62, SLICE
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INPUT = myIwm/SLICE_63, SLICE
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INPUT = myIwm/SLICE_64, SLICE
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INPUT = SLICE_65, SLICE
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INPUT = data[5], PIO
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INPUT = data[3], PIO
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INPUT = data[2], PIO
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INPUT = data[1], PIO
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INPUT = data[0], PIO
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INPUT = _wrreq, PIO
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INPUT = debugInfo[0], PIO
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INPUT = addr[11], PIO
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INPUT = addr[10], PIO
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INPUT = addr[9], PIO
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INPUT = addr[8], PIO
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INPUT = addr[7], PIO
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INPUT = addr[6], PIO
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INPUT = addr[5], PIO
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INPUT = addr[4], PIO
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INPUT = addr[3], PIO
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INPUT = addr[2], PIO
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INPUT = addr[1], PIO
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INPUT = addr[0], PIO
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INPUT = q3, PIO
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INPUT = rw, PIO
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INPUT = _iostrobe, PIO
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INPUT = _iosel, PIO
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INPUT = _reset, PIO
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INPUT = sense, PIO
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INPUT = rddata, PIO
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INPUT = spi_miso, PIO
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INPUT = GSR_INST, GSR
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SIGNAL = _devsel_c, DUMMY
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INPUT = _devsel, PIO
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OUTPUT = SLICE_27, SLICE
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OUTPORT = GND_net, F0
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OUTPORT = q6, Q0
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OUTPUT = spi_clk, PIO
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OUTPUT = spi_mosi, PIO
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OUTPUT = spi_cs, PIO
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OUTPUT = debugInfo[7], PIO
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OUTPUT = debugInfo[6], PIO
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OUTPUT = debugInfo[5], PIO
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OUTPUT = debugInfo[4], PIO
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OUTPUT = debugInfo[3], PIO
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OUTPUT = debugInfo[2], PIO
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OUTPUT = debugInfo[1], PIO
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OUTPUT = SLICE_28, SLICE
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OUTPORT = n1748, F0
|
||
|
|
OUTPORT = q7, Q0
|
||
|
|
OUTPORT = VCC_net, F1
|
||
|
|
OUTPUT = _en245, PIO
|
||
|
|
OUTPUT = SLICE_33, SLICE
|
||
|
|
OUTPORT = n1717, F0
|
||
|
|
OUTPORT = phase_c_0, Q0
|
||
|
|
OUTPORT = data_7_N_1_7, F1
|
||
|
|
OUTPUT = phase[0], PIO
|
||
|
|
OUTPUT = data[7], PIO
|
||
|
|
OUTPUT = SLICE_39, SLICE
|
||
|
|
OUTPORT = iwmDataOut_6, F0
|
||
|
|
OUTPORT = myIwm/motorOn, Q0
|
||
|
|
OUTPORT = data_7_N_1_6, F1
|
||
|
|
OUTPUT = data[6], PIO
|
||
|
|
OUTPUT = SLICE_51, SLICE
|
||
|
|
OUTPORT = data_7_N_1_4, F0
|
||
|
|
OUTPORT = phase_c_2, Q0
|
||
|
|
OUTPORT = n1740, F1
|
||
|
|
OUTPUT = data[4], PIO
|
||
|
|
OUTPUT = phase[2], PIO
|
||
|
|
OUTPUT = myIwm/SLICE_57, SLICE
|
||
|
|
OUTPORT = myIwm/fclk_c_enable_27, F0
|
||
|
|
OUTPORT = phase_c_3, Q0
|
||
|
|
OUTPORT = myIwm/fclk_c_enable_21, F1
|
||
|
|
OUTPUT = phase[3], PIO
|
||
|
|
OUTPUT = myIwm/SLICE_58, SLICE
|
||
|
|
OUTPORT = _enbl1_N_121, F0
|
||
|
|
OUTPORT = myIwm/driveSelect, Q0
|
||
|
|
OUTPORT = _enbl2_N_125, F1
|
||
|
|
OUTPUT = _enbl1, PIO
|
||
|
|
OUTPUT = _enbl2, PIO
|
||
|
|
OUTPUT = SLICE_66, SLICE
|
||
|
|
OUTPORT = n1716, F0
|
||
|
|
OUTPORT = phase_c_1, Q0
|
||
|
|
OUTPORT = myIwm/n1733, F1
|
||
|
|
OUTPUT = phase[1], PIO
|
||
|
|
SIGNAL = fclk_c, DUMMY
|
||
|
|
INPUT = fclk, PIO
|
||
|
|
OUTPUT = myIwm/SLICE_0, SLICE
|
||
|
|
OUTPORT = myIwm/buffer_7_N_46_3, F0
|
||
|
|
OUTPORT = buffer_3, Q0
|
||
|
|
OUTPORT = myIwm/buffer_7_N_46_4, F1
|
||
|
|
OUTPORT = buffer_4, Q1
|
||
|
|
OUTPUT = myIwm/SLICE_1, SLICE
|
||
|
|
OUTPORT = myIwm/buffer_7_N_46_7, F0
|
||
|
|
OUTPORT = buffer_7, Q0
|
||
|
|
OUTPORT = myIwm/n11, F1
|
||
|
|
OUTPUT = SLICE_2, SLICE
|
||
|
|
OUTPORT = n1783, F0
|
||
|
|
OUTPORT = myAddrDecoder/romActive, Q0
|
||
|
|
OUTPUT = myIwm/SLICE_4, SLICE
|
||
|
|
OUTPORT = myIwm/n20_adj_144, F0
|
||
|
|
OUTPORT = myIwm/bitCounter_0, Q0
|
||
|
|
OUTPORT = myIwm/n19, F1
|
||
|
|
OUTPORT = myIwm/bitCounter_1, Q1
|
||
|
|
OUTPUT = myIwm/SLICE_5, SLICE
|
||
|
|
OUTPORT = myIwm/n18, F0
|
||
|
|
OUTPORT = myIwm/bitCounter_2, Q0
|
||
|
|
OUTPUT = myIwm/SLICE_6, SLICE
|
||
|
|
OUTPORT = myIwm/n1598, F0
|
||
|
|
OUTPORT = myIwm/bitTimer_0, Q0
|
||
|
|
OUTPORT = myIwm/n1586, F1
|
||
|
|
OUTPORT = myIwm/bitTimer_1, Q1
|
||
|
|
OUTPUT = myIwm/SLICE_7, SLICE
|
||
|
|
OUTPORT = myIwm/n258, F0
|
||
|
|
OUTPORT = myIwm/bitTimer_2, Q0
|
||
|
|
OUTPORT = myIwm/n259, F1
|
||
|
|
OUTPORT = myIwm/bitTimer_3, Q1
|
||
|
|
OUTPUT = myIwm/SLICE_8, SLICE
|
||
|
|
OUTPORT = myIwm/n260, F0
|
||
|
|
OUTPORT = myIwm/bitTimer_4, Q0
|
||
|
|
OUTPORT = myIwm/n261, F1
|
||
|
|
OUTPORT = myIwm/bitTimer_5, Q1
|
||
|
|
OUTPUT = myIwm/SLICE_9, SLICE
|
||
|
|
OUTPORT = myIwm/buffer_7_N_46_0, F0
|
||
|
|
OUTPORT = myIwm/buffer_0, Q0
|
||
|
|
OUTPORT = myIwm/buffer_7_N_46_1, F1
|
||
|
|
OUTPORT = myIwm/buffer_1, Q1
|
||
|
|
OUTPUT = myIwm/SLICE_10, SLICE
|
||
|
|
OUTPORT = myIwm/buffer_7_N_46_2, F0
|
||
|
|
OUTPORT = myIwm/buffer_2, Q0
|
||
|
|
OUTPORT = myIwm/buffer_7_N_46_5, F1
|
||
|
|
OUTPORT = myIwm/buffer_5, Q1
|
||
|
|
OUTPUT = myIwm/SLICE_11, SLICE
|
||
|
|
OUTPORT = myIwm/buffer_7_N_46_6, F0
|
||
|
|
OUTPORT = myIwm/buffer_6, Q0
|
||
|
|
OUTPUT = myIwm/SLICE_12, SLICE
|
||
|
|
OUTPORT = myIwm/clearBufferTimer_3_N_67_0, F0
|
||
|
|
OUTPORT = myIwm/clearBufferTimer_0, Q0
|
||
|
|
OUTPORT = myIwm/n7, F1
|
||
|
|
OUTPUT = myIwm/SLICE_13, SLICE
|
||
|
|
OUTPORT = myIwm/n71, F0
|
||
|
|
OUTPORT = myIwm/clearBufferTimer_1, Q0
|
||
|
|
OUTPORT = myIwm/n70, F1
|
||
|
|
OUTPORT = myIwm/clearBufferTimer_2, Q1
|
||
|
|
OUTPUT = myIwm/SLICE_14, SLICE
|
||
|
|
OUTPORT = myIwm/n69, F0
|
||
|
|
OUTPORT = myIwm/clearBufferTimer_3, Q0
|
||
|
|
OUTPORT = myIwm/n1750, F1
|
||
|
|
OUTPUT = myIwm/SLICE_18, SLICE
|
||
|
|
OUTPORT = myIwm/shifter_7_N_97_0, OFX0
|
||
|
|
OUTPORT = myIwm/shifter_0, Q0
|
||
|
|
OUTPUT = myIwm/SLICE_19, SLICE
|
||
|
|
OUTPORT = myIwm/shifter_7_N_97_1, F0
|
||
|
|
OUTPORT = myIwm/shifter_1, Q0
|
||
|
|
OUTPORT = myIwm/shifter_7_N_97_2, F1
|
||
|
|
OUTPORT = myIwm/shifter_2, Q1
|
||
|
|
OUTPUT = myIwm/SLICE_20, SLICE
|
||
|
|
OUTPORT = myIwm/shifter_7_N_97_3, F0
|
||
|
|
OUTPORT = myIwm/shifter_3, Q0
|
||
|
|
OUTPORT = myIwm/shifter_7_N_97_4, F1
|
||
|
|
OUTPORT = myIwm/shifter_4, Q1
|
||
|
|
OUTPUT = myIwm/SLICE_21, SLICE
|
||
|
|
OUTPORT = myIwm/shifter_7_N_97_5, F0
|
||
|
|
OUTPORT = myIwm/shifter_5, Q0
|
||
|
|
OUTPORT = myIwm/shifter_7_N_97_6, F1
|
||
|
|
OUTPORT = myIwm/shifter_6, Q1
|
||
|
|
OUTPUT = myIwm/SLICE_22, SLICE
|
||
|
|
OUTPORT = myIwm/shifter_7_N_97_7, F0
|
||
|
|
OUTPORT = myIwm/shifter_7, Q0
|
||
|
|
OUTPORT = myIwm/n230, F1
|
||
|
|
OUTPUT = myIwm/SLICE_29, SLICE
|
||
|
|
OUTPORT = myIwm/wrdata_N_112, F0
|
||
|
|
OUTPORT = wrdata_c, Q0
|
||
|
|
OUTPORT = myIwm/n8, F1
|
||
|
|
OUTPUT = wrdata, PIO
|
||
|
|
OUTPUT = myIwm/SLICE_30, SLICE
|
||
|
|
OUTPORT = myIwm/writeBufferEmpty_N_136, F0
|
||
|
|
OUTPORT = writeBufferEmpty, Q0
|
||
|
|
OUTPORT = myIwm/n1735, F1
|
||
|
|
OUTPUT = myIwm/SLICE_43, SLICE
|
||
|
|
OUTPORT = myIwm/fclk_c_enable_30, F0
|
||
|
|
OUTPORT = myIwm/rddataSync_0, Q0
|
||
|
|
OUTPORT = n1744, F1
|
||
|
|
OUTPORT = myIwm/rddataSync_1, Q1
|
||
|
|
OUTPUT = myIwm/SLICE_53, SLICE
|
||
|
|
OUTPORT = myIwm/_devsel_N_37_enable_3, F0
|
||
|
|
OUTPORT = myIwm/_underrun, Q0
|
||
|
|
OUTPORT = myIwm/_devsel_N_37_enable_4, F1
|
||
|
|
OUTPUT = myROM/codeROM_0_0_1_0, EBR
|
||
|
|
OUTPORT = romOutput_7, DOA3
|
||
|
|
OUTPORT = romOutput_6, DOA2
|
||
|
|
OUTPORT = romOutput_5, DOA1
|
||
|
|
OUTPORT = romOutput_4, DOA0
|
||
|
|
OUTPUT = myROM/codeROM_0_0_0_1, EBR
|
||
|
|
OUTPORT = romOutput_3, DOA3
|
||
|
|
OUTPORT = romOutput_2, DOA2
|
||
|
|
OUTPORT = romOutput_1, DOA1
|
||
|
|
OUTPORT = romOutput_0, DOA0
|
||
|
|
|