initial commit
This commit is contained in:
steve-chamberlin
commit
31488767c7
9
.run_manager.ini
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9
.run_manager.ini
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@ -0,0 +1,9 @@
|
||||
[Runmanager]
|
||||
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
|
||||
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
|
||||
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
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||||
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[yellowstone_blink%3CStrategy1%3E]
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isChecked=false
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isHidden=false
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||||
isExpanded=false
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||||
3
.setting.ini
Normal file
3
.setting.ini
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@ -0,0 +1,3 @@
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[General]
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||||
AutoAssign=false
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||||
Export.auto_tasks=Bitgen, Jedecgen
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3
.spread_sheet.ini
Normal file
3
.spread_sheet.ini
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@ -0,0 +1,3 @@
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||||
[General]
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||||
COLUMN_POS_INFO_NAME_-1_0=Prioritize
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||||
COLUMN_POS_INFO_NAME_-1_1=PIO Register
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||||
76
.spreadsheet_view.ini
Normal file
76
.spreadsheet_view.ini
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@ -0,0 +1,76 @@
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||||
[General]
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||||
pin_sort_type=0
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pin_sort_ascending=true
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||||
sig_sort_type=0
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||||
sig_sort_ascending=true
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active_Sheet=Port Assignments
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[Port%20Assignments]
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Name="140,0"
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Group%20By="84,1"
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Pin="50,2"
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BANK="62,3"
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BANK_VCC="90,4"
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VREF="60,5"
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IO_TYPE="80,6"
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PULLMODE="92,7"
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DRIVE="67,8"
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SLEWRATE="92,9"
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CLAMP="71,10"
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OPENDRAIN="97,11"
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DIFFRESISTOR="114,12"
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DIFFDRIVE="92,13"
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HYSTERESIS="101,14"
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Outload%20%28pF%29="103,15"
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MaxSkew="87,16"
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Clock%20Load%20Only="121,17"
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SwitchingID="100,18"
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Ground%20plane%20PCB%20noise%20%28mV%29="196,19"
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Power%20plane%20PCB%20noise%20%28mV%29="190,20"
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SSO%20Allowance%28%25%29="138,21"
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sort_columns="Name,Ascending"
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[Pin%20Assignments]
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Pin="90,0"
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Pad%20Name="89,1"
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Dual%20Function="158,2"
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Polarity="77,3"
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BANK="0,4"
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BANK_VCC="90,5"
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IO_TYPE="80,6"
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Signal%20Name="102,7"
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Signal%20Type="98,8"
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sort_columns="Pin,Ascending"
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[Clock%20Resource]
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Clock%20Type="100,ELLIPSIS"
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Clock%20Name="100,ELLIPSIS"
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Selection="100,ELLIPSIS"
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[Global%20Preferences]
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Preference%20Name="230,ELLIPSIS"
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Preference%20Value="236,ELLIPSIS"
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[Cell%20Mapping]
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Type="100,ELLIPSIS"
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Name="100,ELLIPSIS"
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Din\Dout="100,ELLIPSIS"
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PIO%20Register="100,ELLIPSIS"
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[Route%20Priority]
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Type="100,ELLIPSIS"
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Name="100,ELLIPSIS"
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Prioritize="100,ELLIPSIS"
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[Timing%20Preferences]
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Preference%20Name="138,ELLIPSIS"
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Preference%20Value="104,ELLIPSIS"
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Preference%20Unit="813,ELLIPSIS"
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||||
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[Group]
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Group%20Type\Name="134,ELLIPSIS"
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Value="921,ELLIPSIS"
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|
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[Misc%20Preferences]
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Preference%20Name="117,ELLIPSIS"
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Preference%20Value="938,ELLIPSIS"
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20
LICENSE.TXT
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20
LICENSE.TXT
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@ -0,0 +1,20 @@
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The FPGA disk controller card design is provided by Steve Chamberlin, Big Mess o' Wires, under the Creative Commons Attribution - ShareAlike 4.0 license.
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see https://creativecommons.org/licenses/by-sa/4.0/
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Please note that the marks "Yellowstone", "BMOW", and "Big Mess o' Wires" are not covered by this license, and are reserved for exclusive use by Steve Chamberlin. You are not permitted to use any of these words in the name of any clone or derivative products based on this design. You will need to choose a new name for any clone or derivative product you may create.
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-------
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You are free to:
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Share — copy and redistribute the material in any medium or format
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Adapt — remix, transform, and build upon the material
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for any purpose, even commercially.
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Under the following terms:
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Attribution — You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
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||||
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ShareAlike — If you remix, transform, or build upon the material, you must distribute your contributions under the same license as the original.
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BIN
LIRONALL.bin
Normal file
BIN
LIRONALL.bin
Normal file
Binary file not shown.
BIN
LIRONHI.bin
Normal file
BIN
LIRONHI.bin
Normal file
Binary file not shown.
BIN
LIRONLO1.bin
Normal file
BIN
LIRONLO1.bin
Normal file
Binary file not shown.
BIN
LIRONLO4.bin
Normal file
BIN
LIRONLO4.bin
Normal file
Binary file not shown.
BIN
LIRONLO5.bin
Normal file
BIN
LIRONLO5.bin
Normal file
Binary file not shown.
BIN
LIRONLO7.bin
Normal file
BIN
LIRONLO7.bin
Normal file
Binary file not shown.
105
README.TXT
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105
README.TXT
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@ -0,0 +1,105 @@
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Compiled by Steve Chamberlin
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steve@bigmessowires.com
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January 28, 2019
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//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\
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|
||||
I'm sharing the FPGA disk controller design because I don't currently have the time or resources to pursue its further development on my own, but want the Apple II collector community to get the benefit of the progress I've made to date.
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See LICENSE.TXT for details on the license terms for this design.
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||||
|
||||
The marks "Yellowstone", "BMOW", and "Big Mess o' Wires" are not covered by this license, and are reserved for my exclusive use. You are not permitted to use any of these words in the name of any clone or derivative products based on this design. You will need to choose a new name for your clone or derivative product.
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||||
|
||||
//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\//\\
|
||||
|
||||
GROUND RULES
|
||||
------------
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||||
|
||||
Please don't send me detailed questions and requests for help with this design, or expect me to be your engineering consultant. I'm releasing the design to the community because I don't have time to pursue it myself. That means I can't work on it for you, either. The design is released as-is, with no promise of technical support. I may be able to answer general questions, but the rest is up to you.
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||||
|
||||
|
||||
WHAT IS THIS?
|
||||
-------------
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||||
|
||||
Yellowstone is the code name for an Apple II disk controller card that's based on an FPGA, rather than using discrete logic chips and ROM chips. By reprogramming the FPGA, the card can be made to emulate various other disk controller cards made by Apple in the 1980s and 1990s. The work so far has focused on emulating an Apple Liron disk controller card, but it would also be easy to emulate a Disk II controller card. It's theoretically also possible to emulate a Disk 3.5 controller card, though this possibility has not been explored in detail.
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||||
|
||||
|
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WHAT'S LIRON?
|
||||
-------------
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||||
|
||||
The Liron disk controller was introduced by Apple in 1985. More formally known as the Apple II UniDisk 3.5 Controller, it's designed to work with a new generation of "smart" disk drives more sophisticated than the venerable Disk II 5.25 inch floppy drive. The smart disk port on the Liron is appropriately named the Smartport, and it can communicate with block-based storage devices such as the Unidisk 3.5 (an early 800K drive) and Smartport-based Apple II hard drives.
|
||||
|
||||
Why care about the Liron? The Apple IIc and Apple IIgs have integrated disk ports with built-in Smartport functionality, but for the earlier Apple II+ and IIe, the Liron is the only way to get a Smartport. For owners of the BMOW Floppy Emu disk emulator, having a Liron card makes it possible to use the Floppy Emu as an external hard drive for the II+ and IIe. Unfortunately finding a Liron is difficult, and although they occasionally turn up on eBay, they’re quite expensive. That makes cloning the Liron a desirable goal.
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||||
|
||||
|
||||
HOW IT WORKS
|
||||
------------
|
||||
|
||||
The FPGA disk controller card is little more than an FPGA, a voltage regulator, and a set of level-shifting bus transceivers. The FPGA replaces all of the 7400-series discrete logic chips typically found on a disk controller card. Verilog (hardware description language) replacements for all of the 7400-series parts and other logic were written and programmed into the FPGA. This also includes a full Verilog implmentation of the Apple IWM chip.
|
||||
|
||||
The FPGA also replaces the ROM chip containing the boot code for the card. The Apple II executes this code during power-up, and the code knows how to find and load sector 0 from the attached disk drive. The code was obtained from a ROM dump from a real Liron card.
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||||
|
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The prototype card also includes a footprint for an 8-pin SPI flash memory chip. It is not used by the current FPGA code, and the chip can be omitted. The idea was that a small number of disk images could be stored in SPI flash memory, so the card could function both as a disk controller and as a disk emulator, but this was never implemented.
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||||
|
||||
The card has a standard 10 x 2 pin disk connector on board. It can be connected directly to a BMOW Floppy Emu disk emulator, using a standard ribbon cable. But for a full Liron clone and connecton to a Unidisk 3.5, a DB-19 female connector is required. A design for a DB-19F adapter PCB is included here, and the adapter can be connected to the disk controller card with a short ribbon cable. The DB-19F is still available from surplus electronics suppliers in small quantities.
|
||||
|
||||
|
||||
PROJECT STATUS
|
||||
--------------
|
||||
|
||||
See https://www.bigmessowires.com/category/yellowstone/ for a complete history of work involving the FPGA disk controller.
|
||||
|
||||
The FPGA disk controller card was designed by Steve Chamberlin at Big Mess o' Wires during the summer of 2017, but the first prototype card wasn't built and tested until January 2018. The version 1.0 card had errors with the wiring for the output enable signal on one of the bus transceiver chips, and it required a few hand-soldered path wires to fix. After further development, the prototype card was demonstrated to work as a Liron clone, in both an Apple IIe enhanced computer and an Apple IIgs. It worked for controlling a real Unidisk 3.5 drive, as well as a BMOW Floppy Emu disk emulator configured for Smartport emulation mode.
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||||
|
||||
Later testing discovered that the FPGA disk controller card worked reliably when it was the only card installed, but other cards were also present, it sometimes malfunctioned. The more other cards present, the worse the rate of errors became. This was diagnosed as a likely termination or contention problem on the Apple II data bus, and various fixes were tried unsuccessfully. After March 2018, I lost interest in researching the problem further, and no more work has occurred since then.
|
||||
|
||||
The design provided here is version 1.1, and it fixes the output enable problem from version 1.0.
|
||||
|
||||
|
||||
WHERE TO START
|
||||
--------------
|
||||
|
||||
Open the FPGA disk controller design (Liron clone) in EAGLE. Export Gerber files and send them to your favorite PCB fabricator. If desired, do the same for the DB19F adapter design.
|
||||
|
||||
Purchase the chips and other parts listed in the BOM.
|
||||
|
||||
Assemble the card. I did it by hand, you can do it too. A syringe of solder paste and a hot plate or toaster oven works nicely.
|
||||
|
||||
Get a Lattice JTAG programmer or appropriate clone. Some clones don't handle 3.3V logic correctly. Maybe spend the extra money for a genuine Lattice programmer.
|
||||
|
||||
Install the Lattice Diamond software.
|
||||
|
||||
Apply 5V power to the card at jumper J4. Do not insert the card into your Apple II yet.
|
||||
|
||||
Program the FPGA with the bitstream for the Liron clone design - liron_fpgatop.jed
|
||||
|
||||
Insert the card in your Apple II. Remove any other cards that are present.
|
||||
|
||||
Connect a Smartport-compatible disk drive, such as a BMOW Floppy Emu disk emulator that's configured for Smartport emulation mode, or an Apple Unidisk 3.5 drive.
|
||||
|
||||
Turn on the Apple II. It should boot from the attached drive.
|
||||
|
||||
|
||||
NEXT STEPS
|
||||
----------
|
||||
|
||||
The bus termination or bus contention problem must be solved, in order to get a robust card that works smoothly when other cards are also present. See the blog posts from February-March 2018 for more details about what was already tried. A solution will require a person who's experienced at electronic design, and has appropriate test equipment such as an oscilloscope and logic analyzer.
|
||||
|
||||
The current design uses a Lattice MachXO2 1200HC FPGA, and a Lattice JTAG programmer (or compatible) is required for programming it. The XO2-1200HC has more logic resources than are actually necessary for the Liron clone design. The cheaper XO2-640 or XO2-256 could be substituted instead. They are mostly or entirely pin-compatible with the XO2-1200HC.
|
||||
|
||||
Programming the FPGA with a JTAG programmer is fine for development use, but end users are unlikely to have one. If reprogramming by the end user is desired (say to switch between Liron and Disk 3.5 emulation behaviors), a different method of FPGA programming will need to be developed.
|
||||
|
||||
|
||||
FILES
|
||||
-----
|
||||
|
||||
eagle/ - directory containing EAGLE designs for the FPGA disk controller card, the DB19F adapter, and a reverse-engineered schematic of the original Liron card.
|
||||
eagle/FPGA disk controller/bom.xslx - bill of materials needed to assemble the card.
|
||||
lattice/ - directory containing the Verilog and other code for the Liron clone design for the card.
|
||||
yellowstone_blink/ - directory containing the Verilog and other code for a simple LED blink example. This can be used to verify that the FPGA is working.
|
||||
yellowstone_blink_tcr.dir/ - directory containing some junk generated by the Lattice Diamond software.
|
||||
disasm.asm, liron.asm - two different disassemblies of the original Liron card's boot ROM
|
||||
LIRONALL.BIN - binary file with the original Liron card's boot ROM
|
||||
rom-full-4k.mem - the Liron boot ROM in a format compatible with the Lattice Diamond software.
|
||||
README.TXT - this file
|
||||
LICENSE.TXT - details about the license for the design
|
||||
3
control.txt
Normal file
3
control.txt
Normal file
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|
||||
load $C000 LIRONALL.bin
|
||||
entry $C700
|
||||
save disasm.asm
|
||||
1749
disasm.asm
Normal file
1749
disasm.asm
Normal file
File diff suppressed because it is too large
Load Diff
817
disk-II-boot-process.txt
Normal file
817
disk-II-boot-process.txt
Normal file
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|
||||
******************************************************************
|
||||
* *
|
||||
* THE BOOT PROCESS *
|
||||
* *
|
||||
******************************************************************
|
||||
* *
|
||||
* The following disassembly describes the boot process for *
|
||||
* a slave disk. In order to TRULY understand this listing, you *
|
||||
* should first be familiar with the exact sequence and coding of *
|
||||
* disk bytes used in track formatting. This information can be *
|
||||
* found in chapter 3 of the book BENEATH APPLE DOS. (The *
|
||||
* distinctions between booting a slave disk versus a master disk *
|
||||
* are described in chapter 8 of the same reference.) *
|
||||
* The boot process loads DOS into the machine as a series *
|
||||
* of discrete packages. After each package is loaded, it is *
|
||||
* executed to load in the next section of DOS. The last *
|
||||
* instruction of the boot process jumps into DOS's coldstart *
|
||||
* routine to build the DOS buffers, set up the page-three vector *
|
||||
* table and run the "HELLO" program. *
|
||||
* Because DOS is loaded in stages, any protected disk can *
|
||||
* cracked by tracing the boot. If you modify each section of *
|
||||
* the boot to stop after loading the next section, you can *
|
||||
* inspect the different stages of the boot to discover the *
|
||||
* protection scheme(s) used. (P.S. In order to modify BOOT0, *
|
||||
* you must first move it down to a RAM location defined by: *
|
||||
* $hs00, where h = high nibble of an address that is low enough *
|
||||
* to accomodate DOS in free memory above and, s = present slot *
|
||||
* number housing the disk controller card.) *
|
||||
* *
|
||||
******************************************************************
|
||||
|
||||
|
||||
|
||||
|
||||
*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::*
|
||||
* *
|
||||
* BOOT 0 *
|
||||
* *
|
||||
*----------------------------------------------------------------*
|
||||
* *
|
||||
* - relocatable code resident on the disk controller's ROM. *
|
||||
* - because the code is relocatable, the disk controllers card *
|
||||
* can be used in different slots. Execution begins at $Cs00, *
|
||||
* where s = slot number (ex. $C600 for card in slot 6). *
|
||||
* - When BOOT0 is executed it: *
|
||||
* (1) builds a table of indices which are used to convert *
|
||||
* the disk bytes into 6/2 encoded bytes which are *
|
||||
* needed by RWTS to translate the disk bytes into *
|
||||
* normal memory bytes. *
|
||||
* (2) recalibrates the disk arm by moving it to trk0/sec0. *
|
||||
* (3) reads BOOT1 into $800 to $8FF (from trk0/sec0). *
|
||||
* (4) jumps to $801 to begin the execution of BOOT1. *
|
||||
* *
|
||||
*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::*
|
||||
|
||||
(Cs00)
|
||||
BOOT0 LDX #$20 ;Controller card's identification byte.
|
||||
|
||||
* Construct a read-translate table which
|
||||
* we will need to convert disk bytes to
|
||||
* encoded memory bytes. (The encoded memory
|
||||
* bytes later go trough further decoding to
|
||||
* convert them to normal memory bytes.)
|
||||
*
|
||||
* We construct the table by sequentially
|
||||
* incrementing (x) and testing it to see
|
||||
* if it meets the folowing criteria of a
|
||||
* disk byte:
|
||||
* (1) it must have at least one pair of
|
||||
* adjacent 1's in bits 0 to 6.
|
||||
* (2) it must not have more than one pair
|
||||
* of adjacent 0's in bits 0 to 6.
|
||||
* (Note that we use the x-value to represent
|
||||
* only the lower seven bits of a disk byte
|
||||
* because all disk bytes are negative.)
|
||||
*
|
||||
* Each time we find an (x) that represents
|
||||
* a simulated disk byte, we increment (y).
|
||||
* (Y) is then placed in the read table at an
|
||||
* offset of (x) from the beginning of the table.
|
||||
* The table generated is shown below. The
|
||||
* empty bytes represent offsets where (x)
|
||||
* did not meet the criteria of a disk byte.
|
||||
* The values in parentheses represent the
|
||||
* (x)-values tested.
|
||||
* 36C- 00 01 -- --
|
||||
* (16) (17) (18) (19)
|
||||
* 370- 02 03 -- 04 05 06 -- --
|
||||
* (1A) (1B) (1C) (1D) (1E) (1F) (20) (21)
|
||||
* 378- -- -- -- -- 07 08 -- --
|
||||
* (22) (23) (24) (25) (26) (27) (28) (29)
|
||||
* 380- -- 09 0A 0B 0C 0D -- --
|
||||
* (2A) (2B) (2C) (2D) (2E) (2F) (30) (31)
|
||||
* 388- 0E 0F 10 11 12 13 -- 14
|
||||
* (32) (22) (34) (35) (36) (37) (38) (39)
|
||||
* 390- 15 16 17 18 19 1A -- --
|
||||
* (3A) (3B) (3C) (3D) (3E) (3F) (40) (41)
|
||||
* 398- -- -- -- -- -- -- -- --
|
||||
* (42) (43) (44) (45) (46) (47) (48) (49)
|
||||
* 3A0- -- 1B -- 1C 1D 1E -- --
|
||||
* (4A) (4B) (4C) (4D) (4E) (4F) (50) (51)
|
||||
* 3A8- -- 1F -- -- 20 21 -- 22
|
||||
* (52) (53) (54) (55) (56) (57) (58) (59)
|
||||
* 3B0- 23 24 25 26 27 28 -- --
|
||||
* (5A) (5B) (5C) (5D) (5E) (5F) (60) (61)
|
||||
* 3B8- -- -- -- 29 2A 2B -- 2C
|
||||
* (62) (63) (64) (65) (66) (67) (68) (69)
|
||||
* 3C0- 2D 2E 2F 30 31 32 -- --
|
||||
* (6A) (6B) (6C) (6D) (6E) (6F) (70) (71)
|
||||
* 3C8- 33 34 35 36 37 38 -- 39
|
||||
* (72) (73) (74) (75) (76) (77) (78) (79)
|
||||
* 3D0- 3A 3B 3C 3D 3E 3F -- --
|
||||
* (7A) (7B) (7C) (7D) (7E) (7F)
|
||||
|
||||
|
||||
(Cs02) LDY #0 ;Initialize the (y) index.
|
||||
(Cs04) LDX #3 ;"3" is used for controller ID. Any number
|
||||
;between 0 and #$16 could be used. Except
|
||||
;for ID purposes, the operand isn't even
|
||||
;relevant until it is #$16 (dec #22).
|
||||
BUILDTBL STX BT0SCRTH ;Save potential index seed in the zero page.
|
||||
(Cs06)
|
||||
|
||||
* Transfer (x) to (a) and test to see if it
|
||||
* meets the following disk byte criteria:
|
||||
* (1) has at least one pair of adjacent 1's
|
||||
* in bits 0 to 6.
|
||||
* (2) has no more than one pair of adjacent
|
||||
* 0's in bits 0 to 6.
|
||||
|
||||
* Test for adjacent 1's.
|
||||
*
|
||||
* Note: by comparing a shifted version of
|
||||
* the seed (in accumulator) with the original
|
||||
* version of the seed (in BT0SCRTH, $3C) we are
|
||||
* actually testing adjacent bits as shown below:
|
||||
* Shifted: b6 b5 b4 b3 b2 b1 b0 0
|
||||
* Orignal: b7 b6 b5 b4 b3 b2 b1 b0
|
||||
* -----------------------------------
|
||||
* Testing: b6,7 b5,6 b4,5 b3,4 b2,3 b1,2 b0,1 -
|
||||
|
||||
(Cs08) TXA
|
||||
ASL
|
||||
(Cs0A) BIT BT0SCRTH ;Conditions the z-flag of the status.
|
||||
;(If any bits match, z-flag=1.)
|
||||
(Cs0C) BEQ GETNEWX ;Branch if value was illegal.
|
||||
;Illegal value = z-flag=1 = no match = no
|
||||
;adjacent 1's.
|
||||
|
||||
* Got at least 1 pair of adjacent 1's, so
|
||||
* now prepare to test for adjacent 0's.
|
||||
* (Note: the previous "BIT" instruction
|
||||
* alters the z-flag in the status but
|
||||
* does not affect the accumulator.)
|
||||
(Cs0E) ORA BT0SCRTH ;Merge shifted version of seed with orig.
|
||||
(Cs10) EOR #$FF ;Take 1's compliment of shifted version to
|
||||
;swap 1's for 0's and 0's for 1's.
|
||||
(Cs12) AND #%01111110 ;Throw away the hi and least significant
|
||||
;bits so will be testing:
|
||||
; b5,6 b4,5 b3,4 b2,3 b1,2 b0,1.
|
||||
|
||||
* Test for pairs of adjacent 0's.
|
||||
* Remember, only 1 pair of adjacent 0's is
|
||||
* allowed. Because we did a 1's compliment
|
||||
* of the merged bits above, a SET BIT NOW
|
||||
* DENOTES A PAIR OF ADJACENT 0's. We can
|
||||
* therefore test for a pair of adjacent 0's
|
||||
* by shifting a bit into the carry:
|
||||
* - if (c) = 1 = at least one pair of adjacent 0's
|
||||
* is present.
|
||||
* - if (c) = 1 AND the remaining byte = 0 then
|
||||
* we have only one pair of adjacent 0's so
|
||||
* value is legal.
|
||||
* - if (c) = 1 AND the remaining byte < > 0, we
|
||||
* have more than one pair of adjacent 0's so
|
||||
* value is illegal.
|
||||
(Cs14)
|
||||
TESTCARY BCS GETNEWX ;Always fall through on very first entry.
|
||||
;If branch is taken, got illegal value
|
||||
;because more than 1 pr of adjacent 0's.
|
||||
(Cs16) LSR ;Shift a bit into the carry (if carry set
|
||||
;have at least 1 pr of adjacent 0's).
|
||||
(Cs17) BNE TESTCARY ;Take branch when remaining byte is not
|
||||
;zero. Got at least 1 pr of adjacent 0's.
|
||||
;Go test carry to see if another pair has
|
||||
;already been detected.
|
||||
|
||||
* Index byte was legal. We either got no
|
||||
* adjacent 0's or else only one pair of
|
||||
* adjacent 0's.
|
||||
(Cs19) TYA ;Store the counter that corresponds to a
|
||||
(Cs1A) STA BTNIBL-$16,X ;legal nibble. The first (x) value used
|
||||
;is #$16, last is #$7F. The first (y) value
|
||||
;stored is 0, the last is #$3F.
|
||||
(Cs1D) INY
|
||||
GETNEWX INX
|
||||
(Cs1F) BPL BUILDTBL ;Keep on trying to build table until (x)
|
||||
;increments to #$80.
|
||||
|
||||
* Find out which slot the disk controller
|
||||
* card resides in.
|
||||
(Cs21) JSR MONRTS ;Jsr to an RTS to put the present address on
|
||||
;the stack. The hi byte of the present addr
|
||||
;($Cs) tells us what slot (s) the card is
|
||||
;located in.
|
||||
|
||||
* An RTS instruction in monitor ROM.
|
||||
(FF58)
|
||||
MONRTS RTS
|
||||
|
||||
(Cs24) TSX ;Put the value of the stack pointer in (x).
|
||||
(Cs25) LDA STACK,X ;Get the hi byte of the controllers address
|
||||
;($Cs) from the stack.
|
||||
(Cs28) ASL ;Multiply by 16 (throwing away original hi
|
||||
ASL ;nibble) so we are left with #$s0.
|
||||
ASL
|
||||
ASL ;(a) = slot * 16.
|
||||
STA SLT16ZPG ;Save slot*16 in a zero-page location.
|
||||
(Cs2E) TAX ;Set (x) = slot * 16 so we can index the
|
||||
;base addresses associated with the drive
|
||||
;functions.
|
||||
(Cs2F) LDA Q7L,X ;Set the READ mode.
|
||||
LDA Q6L,X
|
||||
LDA SELDRV1 ;Select drive 1.
|
||||
(Cs38) LDA MTRON,X ;Spin the disk.
|
||||
|
||||
* Move disk arm to track 0 by doing a
|
||||
* recalibration. (That is, force the arm
|
||||
* against the stop by pretending that it
|
||||
* is presently at trk decimal 40.)
|
||||
* (The arm is moved by sequentially turning
|
||||
* a series of magnets off and on.)
|
||||
(Cs3B) LDY #80 ;Pretend arm is at trk40 (dec 80 half-trks).
|
||||
MAGNTOFF LDA MAG0FF,X ;Turn the presently aligned magnet off.
|
||||
(Cs40) TYA ;Calculate the next magnet that should be
|
||||
;turned on to suck the arm over.
|
||||
(Cs41) AND #%00000011 ;Only keep the lower two bits because we
|
||||
;only want a maximum value of 3 because
|
||||
;there are only 4 magnets (which are indexed
|
||||
;by values 0 to 3). The sequence used in
|
||||
;this loop is: 3,2,1,0,3...
|
||||
(Cs43) ASL ;Multiply by 2 so the index is directed to
|
||||
;an address that turns a magnet ON. The
|
||||
;sequence used is: 6,4,2,0,6...0.
|
||||
(Cs44) ORA SLT16ZPG ;Merge the index with the slot * 16 value.
|
||||
TAX ;Put the calculated index in (x).
|
||||
LDA MAG0N,X ;Turn the appropriate magnet ON.
|
||||
(Cs4A) LDA #$56 ;Delay approximately 20 000 machine cycles
|
||||
;(approximately 20 milliseconds.) (Gives
|
||||
(Cs4C) JSR WAIT ;arm time to align with energized magnet
|
||||
;and reduces overshoot or bounce.)
|
||||
|
||||
* Monitor ROM's main delay routine.
|
||||
* Delay z number of cycles based on
|
||||
* the formula:
|
||||
* z = ((5 * a^2) + (27 * a) +26) / 2
|
||||
* where a = value in the accumulator on entry.
|
||||
(FCA8)
|
||||
WAIT SEC ;Prepare for subtraction.
|
||||
WAIT2 PHA ;Save (a) on the stack.
|
||||
WAIT3 SBC #1 ;Keep on reducing (a) until it equals 0.
|
||||
BNE WAIT3
|
||||
PLA
|
||||
SBC #1 ;Reduce the original (a) down to 0 again.
|
||||
BNE WAIT2
|
||||
(FCB3) RTS
|
||||
|
||||
(Cs4F) DEY ;Reduce trk # count.
|
||||
(Cs50) BPL MAGNTOFF ;Not at trk0 yet, so go move arm some more.
|
||||
|
||||
* Initialize the buffer pointer and trk/sec values.
|
||||
* (On entry: (x) = slot *16, (y) = #$FF & (a) = $00.)
|
||||
(Cs52) STA PT2BTBUF ;Set the low byte of the buf pointer to $00.
|
||||
STA BOOTSEC ;Initialize for sector 0 on track 0.
|
||||
STA BOOTRK
|
||||
LDA #8 ;Set the hi byte of the buf pointer to $08
|
||||
(Cs5A) STA PT2BTBUF+1 ;(that is, direct pointer at $800).
|
||||
|
||||
* Prepare to start reading a prologue.
|
||||
(Cs5C)
|
||||
BTRDSEC CLC ;(c) = 0 = signal to read an addr prologue.
|
||||
|
||||
* Begin reading a prologue.
|
||||
(Cs5D)
|
||||
PRSRVFLG PHP ;Preserve the status denoting if reading
|
||||
;address ((c)=0) or data ((c)=1) prologue.
|
||||
|
||||
* Look for an address prologue ("D5 AA 96")
|
||||
* or a data prologue ("D5 AA AD").
|
||||
(Cs5E)
|
||||
STARTSEQ LDA Q6L,X ;Read a disk byte.
|
||||
BPL STARTSEQ ;Wait for a full byte.
|
||||
BTRYD5 EOR #$D5 ;Is it a "D5"?
|
||||
BNE STARTSEQ ;No - restart sequence.
|
||||
BTRYAA LDA Q6L,X ;Read next byte in header.
|
||||
BPL BTRYAA ;Wait for a full byte.
|
||||
CMP #$AA ;Is it an "AA"?
|
||||
BNE BTRYD5 ;No - restart sequence.
|
||||
NOP ;Delay 2 cycles.
|
||||
BTRY96 LDA Q6L,X ;Read third byte in header.
|
||||
BPL BTRY96 ;Wait for a full byte.
|
||||
CMP #$96 ;Is it a "96"?
|
||||
Cs78) BEQ RDVLTKSC ;Found an address prologue, so now go read
|
||||
;the vol, trk, sec values in the header.
|
||||
|
||||
* The first two bytes were "D5 AA".
|
||||
* The 3rd byte was not "96". Therefore,
|
||||
* although we know this isn't an address
|
||||
* prologue, maybe it is a data prologue.
|
||||
(Cs7A) PLP ;Get the status back off the stack so we can
|
||||
;check if we were looking for an address or
|
||||
;data prologue.
|
||||
(Cs7B) BCC BTRDSEC ;Branch back to try again if we were looking
|
||||
;for an address prologue but didn't find it.
|
||||
|
||||
* We were looking for a data prologue so
|
||||
* now compare the 3rd byte with that of a
|
||||
* data prologue.
|
||||
(Cs7D)
|
||||
BTRYAD EOR #$AD ;Is it an "AD"?
|
||||
BEQ RDBTDATA ;Yes - found data prol so now read in data.
|
||||
(Cs81) BNE BTRDSEC ;No - go try again to find sequence 4 data.
|
||||
|
||||
* Read volume, track and sector values in
|
||||
* the address header.
|
||||
* Remember, @ of these pieces of information
|
||||
* are housed in two bytes in an odd-even encoded
|
||||
* format: 1rst byte: 1 b7 1 b5 1 b3 1 b1 (odd-encoded).
|
||||
* 2nd byte: 1 b6 1 b4 1 b2 1 b1 (even-encoded).
|
||||
* We must decode these bytes to check if we located
|
||||
* the correct volume, track and sector.
|
||||
(Cs83)
|
||||
RDVLTKSC LDY #3 ;Set counter for 3 decoded bytes.
|
||||
MOREBYTS STA BOOTEMP ;Only relevant the last time through the
|
||||
(Cs85) ;loop at which time it contains the decoded
|
||||
(Cs87) ;track number read off the disk.
|
||||
BTRDODD LDA Q6L,X ;Read odd-encoded byte.
|
||||
BPL BTRDODD ;Wait for a full byte.
|
||||
(Cs8C) ROL ;Throw away the hi bit & shift the odd bits
|
||||
;to their regular position.
|
||||
(Cs8D) STA BT0SCRTH ;Save realigned version of odd-encoded byte.
|
||||
BTRDEVEN LDA Q6L,X ;Read the even-encoded byte.
|
||||
BPL BTRDEVEN ;Wait for a full byte.
|
||||
AND BT0SCRTH ;Merge the two bytes.
|
||||
DEY ;Reduce counter for # of bytes to rebuild.
|
||||
BNE MOREBYTS ;Branch if more bytes to patch back together.
|
||||
PLP ;Throw the status on the stack away.
|
||||
CMP BOOTSEC ;Is the sector read = sector wanted?
|
||||
BNE BTRDSEC ;No - go back to find correct sector.
|
||||
LDA BOOTEMP ;Get decoded trk # just read off disk.
|
||||
CMP BOOTRK ;Is trk found = trk wanted?
|
||||
BNE BTRDSEC ;No - go back to try again.
|
||||
(CsA4) BCS PRSRVFLG ;ALWAYS - just read addr field, so now go
|
||||
; read the data prologue.
|
||||
|
||||
* Read the sector's data bytes.
|
||||
|
||||
* Read the first 86 ($56) bytes of the sector. Use
|
||||
* the disk byte as an index to the BTNIBL table ($36C-$3D5).
|
||||
* Get the value from BTNIBL table & EOR it with the
|
||||
* previous EOR result (except on entry, use
|
||||
* #0 EOR BTNIBL-$96,Y) to produce a 2-encoded nibble.
|
||||
* (On entry, (a) = 0.)
|
||||
(CsA6)
|
||||
BTRDATA LDY #$56 ;Read $56 (dec #86) bytes.
|
||||
KEEPCNT1 STY BT0SCRTH ;Save the counter.
|
||||
RDDSK1 LDY Q6L,X ;Read a disk data byte.
|
||||
BPL RDDSK1 ;Wait for a full byte.
|
||||
(CsAF) EOR BTNIBL-$96,Y ;Use disk byte as an index to the table
|
||||
;and EOR to decode to a 2-encoded nibble.
|
||||
(CsB2) LDY BT0SCRTH ;Retrieve the counter.
|
||||
DEY ;Reduce the counter (& condition z-flag).
|
||||
STA BUF300,Y ;Store 2-encoded nibble in page 3 buffer.
|
||||
(CSB8) BNE KEEPCNT1 ;Branch if more bytes to read.
|
||||
|
||||
* Read the rest of the sector (256 disk bytes
|
||||
* remaining). Use disk byte as an index to BTNIBL
|
||||
* table. Get value from nibble table and EOR it
|
||||
* with previous EOR result to yeild a 6-encoded
|
||||
* nibble. (On entry, (y) = 0.)
|
||||
(CsBA)
|
||||
KEEPCNT2 STY BT0SCRTH ;Set disk byte counter = 0.
|
||||
RDDSK2 LDY Q6L,X ;Read a disk byte.
|
||||
BPL RDDSK2 ;Wait for a full byte.
|
||||
(CsC1) EOR BTNIBL-$96,Y ;Use disk byte as an index to the nibble
|
||||
;table and EOR it with previous result to
|
||||
;produce a 6-encoded nibble.
|
||||
(CsC4) LDY BT0SCRTH ;Get index to buffer.
|
||||
STA (PT2BTBUF),Y ;Store 6-encoded nibble in buffer.
|
||||
INY ;Kick up offset into buffer.
|
||||
(CsC9) BNE KEEPCNT2
|
||||
|
||||
* Read and test the data checksum.
|
||||
* On entry, (a) = result of previous cummulative
|
||||
* EORing. Therefore, any non-cancelling errors are
|
||||
* detected at the BNE instruction below.
|
||||
(CsCB)
|
||||
RDCK LDY Q6L,X ;Read the data checksum.
|
||||
BPL RDCK ;Wait for a full byte.
|
||||
(CsD0) EOR BTNIBL-$96,Y ;EOR byte read with the previous
|
||||
;cummulative result.
|
||||
TSTRERD BNE BTRDSEC ;Bad checksum so branch back to re-read.
|
||||
(CsD3) ;(Also branches to here if got a good read
|
||||
;but there are more sectors to read if the
|
||||
;first byte of BOOT1 is modified to allow
|
||||
;BOOT0 to read more than 1 sector (see
|
||||
;comments below).
|
||||
|
||||
* Convert 6-and-2 encoded buffer bytes to
|
||||
* normal 8-bit memory bytes.
|
||||
(CsD5) LDY #0 ;Initialize index to target memory byte.
|
||||
SETX56 LDX #$56 ;Set index to buf containing encoded bytes.
|
||||
DOWNX DEX ;Reduce index for next buffer byte.
|
||||
BMI SETX56 ;Reset index to encoded buffer.
|
||||
LDA (PT2BTBUF),Y ;Get (a) = 6-encoded nibble.
|
||||
LSR BUF300,Y ;Put a bit from the 2-encoded buffer in (c)
|
||||
ROL ;and then roll it into the 6-encoded nibble.
|
||||
LSR BUF300,Y ;Do the same with the next bit of the pair.
|
||||
ROL
|
||||
STA (PT2BTBUF),Y ;Store the re-constructed 8-bit byte in memory.
|
||||
INY ;Increase the offset to the buffer.
|
||||
(CsE9) BNE DOWNX ;Branch back if more bytes to reconstruct.
|
||||
|
||||
* Prepare to read in the next sector.
|
||||
* NOTE: Normaly only trk0/sec0 (which
|
||||
* represents BOOT1) is read in by BOOT0.
|
||||
* The number of sectors read in by BOOT0 is
|
||||
* determined by the first byte of BOOT1.
|
||||
* Whereas BOOT1 resides in memory on an 48K
|
||||
* INITed disk at $B600 - $B6FF, we can zap a
|
||||
* disk at $B600 with the # of sectors we
|
||||
* we would like BOOT0 to read in if we want
|
||||
* it to read in more than 1 sector.
|
||||
(CsEB) INC PT2BTBUF+1 ;Just crossed page boundary, so kick up
|
||||
;the hi byte of the target address.
|
||||
(CsED) INC BOOTSEC ;Set value for next sector wanted.
|
||||
LDA BOOTSEC ;Get next sector wanted.
|
||||
(CsF1) CMP $800 ;Test if read enough sectors.
|
||||
;First byte of image of BOOT1 normally
|
||||
;contains #$01 which denotes only 1 sector
|
||||
;(sec0/trk0) should be read in by BOOT0.
|
||||
(CsF4) LDX SLT16ZPG ;(x) = slot *16.
|
||||
BCC TSTRERD ;Branch back to read more sectors.
|
||||
(CsF8) JMP BT1EXC08 ;Jumps into BOOT1 (which was copied into
|
||||
------------ ;page 8 from trk0/sec0) to begin execution
|
||||
;of BOOT1.
|
||||
|
||||
|
||||
*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::*
|
||||
* *
|
||||
* BOOT 1 *
|
||||
* *
|
||||
*----------------------------------------------------------------*
|
||||
* *
|
||||
* - stored on trk0/sec0. *
|
||||
* - IMAGE in memory on a 48K system resides at $B600 - $B6FF. *
|
||||
* - read into $800 to $8FF by the disk controller ROM (BOOT0). *
|
||||
* - execution begins at $801 & uses the controller's read sector *
|
||||
* subroutine (BTRDSEC, Cs00, where s = slot # of card) to read *
|
||||
* in trk0/sec9 down to trk0/sec1 ($BFFF --> $B600). *
|
||||
* - NOTE: In order to generate an accurate symbol table that *
|
||||
* can be applied 2 both the formatted & linear disassemblies, *
|
||||
* and because different assemblers vary in their abilities to *
|
||||
* accept certain OBJect values or re-ORG during assembly, the *
|
||||
* following special label system has been created: *
|
||||
* Image label/adr Execution label/adr Comments *
|
||||
* --------------- ------------------- -------------------- *
|
||||
* SEC2RDB6, $B600 SEC2RD08, $800 ;Defines # of secs to *
|
||||
* ;be read in by boot0. *
|
||||
* BT1EXCB6, $B601 BT1EXC08, $801 ;Start of boot1. *
|
||||
* ;Boot0 jumps to this *
|
||||
* ;location. *
|
||||
* SKPRELB6, $B61F SKPREL08, $81F ;Target labl 4 brnch. *
|
||||
* PRP4B2B6, $B639 PRP4B208, $839 ;Target labl 4 brnch. *
|
||||
* IMG8FD, $B6FD BT1LDADR, $8FD ;Boot1 load address. *
|
||||
* ;Varies from $B600 to *
|
||||
* ;$BF00. Eventually *
|
||||
* ;pts 2 start of boot2 *
|
||||
* ;($B700). *
|
||||
* IMG8FF, $B6FF BT1PG2RD, $8FF ;Contains # of secs 2 *
|
||||
* ;be read in when *
|
||||
* ;executing boot1. Also*
|
||||
* ;doubles as logical *
|
||||
* ;sec #. Varies from: *
|
||||
* ;$09 --> $00 --> $FF. *
|
||||
* - As indicated above, SEC2RD08 ($800) defines the number of *
|
||||
* sectors to be read in by boot0. This value is normally $01 *
|
||||
* (meaning read only sector0 of track0). However, you can zap *
|
||||
* trk0/sec0/offset0 with a larger value ($01 to $10) to read *
|
||||
* more sectors from trk0. Also note that most references say *
|
||||
* that SEC2RD08 normally contains a "$00" (rather than a *
|
||||
* "$01"). Because the test at $CsF6 uses the carry, either *
|
||||
* value will only cause one sector to be read in. However, *
|
||||
* "$01" is the value used by DOS. (Confusion may stem from *
|
||||
* the fact that Applesoft later stores a $00 in memory at *
|
||||
* $800.) *
|
||||
* *
|
||||
*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::*
|
||||
|
||||
|
||||
(B600) <============= image address.
|
||||
SEC2RDB6
|
||||
(800) <============== execution address.
|
||||
SEC2RD08 HEX 01 ;Defines the number of sectors to be read
|
||||
;in from track 0 during BOOT0.
|
||||
|
||||
(B601)
|
||||
BT1EXCB6
|
||||
(801)
|
||||
BT1EXC08 LDA PT2BUF+1 ;Get the next page to read in.
|
||||
CMP #$09 ;Is it page 9 (ie. first page read by BOOT1)?
|
||||
BNE SKPREL08 ;No - already used by BOOT1 to read page 9,
|
||||
;so skip pointer initialization given below.
|
||||
|
||||
* Initialize the pointer (PT2RDSC) to point
|
||||
* at BOOT0's read sector subroutine (BTRDSEC,
|
||||
* $Cs5C, where s = slot #, normally $C65C).
|
||||
(B607)
|
||||
(807) LDA SLT16ZPG ;(a) = slot *16.
|
||||
LSR ;Divide by 16.
|
||||
LSR
|
||||
LSR
|
||||
LSR
|
||||
ORA $C0 ;Merge with $C0 to get $Cs, where s=slot#.
|
||||
STA PTR2RDSC+1 ;Store the hi byte of the address of the
|
||||
;controller's read sector subroutine.
|
||||
LDA #<BTRDSEC ;Get low byte of addr of subroutine.
|
||||
STA PTR2RDSC ;Low byte is a constant (#$5C) and is
|
||||
;therefore not variable with the slot used
|
||||
;(as is the hi byte).
|
||||
|
||||
* Read in the 9 sectors represented by
|
||||
* trk0/sec9 down to trk0/sec1 into
|
||||
* $BFFF to $B600. Note that the sectors
|
||||
* are read in from higher to lower memory.
|
||||
* These sectors contain the IMAGE of BOOT1,
|
||||
* part of the File Manager and almost all
|
||||
* of RWTS and it's associated routines.
|
||||
|
||||
* Calculate target address for the first sector
|
||||
* to be read in.
|
||||
(B615)
|
||||
(815) CLC
|
||||
LDA BT1LDADR+1 ;Contains $B6 on 48K slave.
|
||||
ADC BT1PG2RD ;Contains #$09 on 48K slave.
|
||||
STA BT1LDADR+1 ;(a) = #$BF on 48K slave.
|
||||
|
||||
* Determine the number of sectors left to read,
|
||||
* the physical sector number & the target address.
|
||||
* Then, go read in the next sector.
|
||||
(B61F)
|
||||
SKPRELB6
|
||||
(81F)
|
||||
SKPREL08 LDX BT1PG2RD ;(x) = pages left to read in less 1.
|
||||
;(Also doubles as logical sector number.
|
||||
;Varies from $09 --> $FF.)
|
||||
BMI PRP4B208 ;When (x) = $FF, we have read all the
|
||||
;sectors in so go exit.
|
||||
LDA PHYSECP8-$AE00,X ;Convert the logical sector number
|
||||
;to a physical sector number. (Equivalent
|
||||
;to "LDA $84D,X".)
|
||||
STA BOOTSEC ;Store physical sector number in page0.
|
||||
DEC BT1PG2RD ;Reduce sectors (pages) left to read for
|
||||
;the next time around.
|
||||
LDA BT1LDADR+1 ;Point the buffer pointer at the target
|
||||
STA PT2BTBUF+1 ;address. (Varies from $BF to $B6 on a
|
||||
;48K slave.)
|
||||
DEC BT1LDADR+1 ;Reduce the hi byte of the I/O buffer for
|
||||
;the next time around. (Varies from $BF to
|
||||
;$B5 on a 48K slave.)
|
||||
LDX SLT16ZPG ;Set (x) = slot*16.
|
||||
(836) JMP (PTR2RDSC) ;Equivalent to "JMP ($8FD)" or "JMP $Cs5C"
|
||||
(B636) ------------ ;to go read in the next sector.
|
||||
;***************** NOTE *******************
|
||||
;* GOES TO BT1EXC08 ($801) AFTER @ SECTOR *
|
||||
;* IS READ IN. (BT1EXCB6 is a carbon copy *
|
||||
;* of BT1EXC08.) *
|
||||
;******************************************
|
||||
|
||||
* Prepare for BOOT2.
|
||||
(B639)
|
||||
PRP4B2B6
|
||||
(839)
|
||||
PRP4B208 INC BT1LDADR+1 ;Point at the load address for BOOT2.
|
||||
INC BT1LDADR+1 ;(After the INCs = $B7 on 48K slave.)
|
||||
|
||||
* Set full screen text & designate the
|
||||
* keyboard and screen as the I/O devices.
|
||||
(B63F)
|
||||
(83F) JSR SETKBD ;Simulate an IN#0. (See dis'mbly below.)
|
||||
JSR SETVID ;Simulate an PR#0. (See dis'mbly below.)
|
||||
JSR INIT ;Simulate a "TEXT" statement. (See dis'mbly
|
||||
;in APPLE II REFERENCE MANUAL at $FB2F.)
|
||||
LDX SLT16ZPG ;(x) = slot * 16.
|
||||
|
||||
* Go to BOOT2.
|
||||
(B64A)
|
||||
(84A) JMP (BT1LDADR) ;Jump to BOOT2 ($B700 on 48K slave).
|
||||
--------------
|
||||
|
||||
|
||||
*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::*
|
||||
* *
|
||||
* BOOT2 *
|
||||
* *
|
||||
*----------------------------------------------------------------*
|
||||
* *
|
||||
* - Reads in the rest of DOS starting at trk02/sec04 down to *
|
||||
* trk00/sec0A ($B5FF --> $9B00). (P.S. Sectors 0A and 0B of *
|
||||
* track 0 are empty ($9CFF - $9B00).) *
|
||||
* - After the rest of DOS is read in, execution jumps to DOS's *
|
||||
* coldstart routine (DOSCLD, $9D84). *
|
||||
* - Note that on entry: (x) = slot * 16 *
|
||||
* *
|
||||
*::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::*
|
||||
|
||||
|
||||
* Prepare RWTS's input-output block (IOB)
|
||||
* and designate the number of sectors to read.
|
||||
(B700)
|
||||
BOOT2 STX IBSLOT ;(x) = slot*16 wanted.
|
||||
STX IOBPSN ;Last-used slot*16 value.
|
||||
LDA #1 ;Set both the last-used and wanted drives
|
||||
STA IOBDPDN ;as drive #1.
|
||||
STA IBDRVN
|
||||
LDA NMPG2RD ;Set number of pages (ie. secs) to read.
|
||||
STA BT2PGCTR ;Counter for for number of pages to read.
|
||||
LDA #2 ;Start with trk02/sec04.
|
||||
STA IBTRK ;Track.
|
||||
LDA #4
|
||||
STA IBSECT ;Sector.
|
||||
(B71E) LDY BT1MGADR+1 ;(y) = hi byte of the address of the image
|
||||
;of BOOT1 (#$B6 on a 48K slave).
|
||||
(B721) DEY ;Define I/O buf as 1 page below boot1.
|
||||
STY IBBUFP+1
|
||||
LDA #1 ;Opcode for read.
|
||||
(B727) STA IBCMD
|
||||
|
||||
* Convert from (x) = slot*16 to (x) = slot.
|
||||
(B72A) TXA ;(x) = slot * 16.
|
||||
LSR ;Divide by 16.
|
||||
LSR
|
||||
LSR
|
||||
LSR
|
||||
(B72F) TAX ;(x) = slot.
|
||||
|
||||
* Initialize the page-four locations with
|
||||
* the track numbers associated with the drives.
|
||||
(B730) LDA #0
|
||||
STA TRK4DRV2,X
|
||||
(B735) STA TRK4DRV1,X
|
||||
|
||||
* Call the routine to read in the rest of DOS.
|
||||
(B738) JSR RWPAGES
|
||||
|
||||
* READ/write a group of pages.
|
||||
(B793)
|
||||
RWPAGES LDA ADROFIOB+1 ;Init (a)/(y) with the hi/low bytes of the
|
||||
LDY ADROFIOB ;addr of RWTS's IOB for entry to RWTS.
|
||||
(B799) JSR ENTERWTS ;Enter RWTS to read/write sector.
|
||||
|
||||
* Entry to RWTS.
|
||||
(B7B5)
|
||||
ENTERWTS PHP ;Save status register on the stack.
|
||||
(B7B6) SEI ;Set the interrupt disable flag to prevent
|
||||
;any further maskable interrupts when doing
|
||||
;real-time programming.
|
||||
(B7B7) JSR RWTS ;Enter RWTS proper to do the operation:
|
||||
; $00=seek, $01=read, $02=write, $03=format.
|
||||
|
||||
* RWTS proper.
|
||||
(BD00)
|
||||
RWTS .
|
||||
.
|
||||
(See dis'mbly in RWTSDRVR using READ.)
|
||||
.
|
||||
.
|
||||
(RTS)
|
||||
|
||||
(B7BA) BCS ERRENTER ;Operation was NOT successful.
|
||||
PLP ;Retrieve saved status off the stack.
|
||||
(B7BE) RTS
|
||||
============
|
||||
|
||||
(B7BF)
|
||||
ERRENTER PLP ;Throw the saved status off the stack.
|
||||
SEC ;Signal operation was unsuccessful.
|
||||
(B7C1) RTS
|
||||
============
|
||||
|
||||
(B79C) LDY IBSECT ;Get # of the sector just read or written.
|
||||
(B79F) DEY ;Set value for next sector 2 read. When
|
||||
;executing BOOT1, goes from $09 to $FF.
|
||||
(B7A0) BPL SAMETRK ;Branch to use the same track.
|
||||
|
||||
* Start a new track.
|
||||
(B7A2) LDY #$0F ;Start with sector 15.
|
||||
NOP
|
||||
NOP
|
||||
(B7A6) DEC IBTRK ;Reduce number of track wanted.
|
||||
|
||||
* Reduce the addr of the target memory location.
|
||||
* Test if more sectors to read.
|
||||
(B7A9)
|
||||
SAMETRK STY IBSECT ;Store the sector wanted.
|
||||
DEC IBBUFP+1 ;Reduce buf addr of target memory location.
|
||||
DEC BT2PGCTR ;Reduce counter for # of sectors to read.
|
||||
BNE RWPAGES ;More sectors to read.
|
||||
(B7B4) RTS
|
||||
|
||||
(B73B) LDX #$FF ;Completely clear out the stack.
|
||||
TXS
|
||||
STX IBVOL ;Set the volume to $FF (compliment of 0).
|
||||
(B741) JMP CLOBCARD
|
||||
------------
|
||||
|
||||
* Patch to clobber the language card
|
||||
* and set video output.
|
||||
(BFC8)
|
||||
CLOBCARD JSR SETVID ;Select the video screen.
|
||||
|
||||
* Monitor ROM's routine to designate the
|
||||
* video screen as the output device.
|
||||
* (Simulate a "PR#0" statement.)
|
||||
(FE93)
|
||||
SETVID LDA #0 ;Designate slot 0.
|
||||
OUTPORT STA A2L
|
||||
OUTPRT LDX #<CSW ;Set offset from start of zero page to OUTPUT hook.
|
||||
LDY #<COUT1
|
||||
IOPRT LDA A2L
|
||||
AND #$0F
|
||||
(FE9F) BEQ IOPRT1 ;ALWAYS.
|
||||
|
||||
(FEA7)
|
||||
IOPRT1 LDA #>COUT1 ;(Hi byte of addr of KEYIN & COUT1 are equal.)
|
||||
IOPRT2 STY LOC0,X ;Set CSW: COUT1.
|
||||
STA LOC1,X
|
||||
(FEAD) RTS
|
||||
|
||||
(BFCB) LDA $C081 ;Write enable the RAM card.
|
||||
LDA $C081 ;(Read motherboard / write card bank 2.)
|
||||
LDA #0 ;Set the language identifying byte on the
|
||||
(BFD3) STA BASICCLD ;card to $00 so if card is tested (during
|
||||
;an FP command), the machine will be forced
|
||||
;to use the motherboard version of FP.
|
||||
(BFD6) JSR CONTCLOB ;Now clobber the 80-column card.
|
||||
|
||||
* Clobber the 80-column card.
|
||||
(BA76)
|
||||
CONTCLOB LDA #$FF ;Set the mode flag for card.
|
||||
STA $4FB ;Scratch pad memory for slot 3 peripheral.
|
||||
STA $C00C ;Turn off the alternate character set.
|
||||
STA $C00E
|
||||
(BA81) JMP INIT ;Simimulate a TEXT statement.
|
||||
------------
|
||||
|
||||
* Monitor ROM's Init routine.
|
||||
(FB2F)
|
||||
INIT .
|
||||
.
|
||||
(See dis'mbly in APPLE II REFERENCE MANUAL.)
|
||||
.
|
||||
.
|
||||
- simulate a text statement.
|
||||
(Ie. set window to full screen text.)
|
||||
.
|
||||
.
|
||||
(RTS)
|
||||
|
||||
(BFD9) JMP BK2BOOT2 ;Return to original part of BOOT2.
|
||||
------------
|
||||
|
||||
* Return back to original part of BOOT2.
|
||||
(B744)
|
||||
BK2BOOT2 JSR SETKBD ;Select the keyboard.
|
||||
|
||||
* Monitor ROM's routine to designate the
|
||||
* keyboard as the input device.
|
||||
* (Simulate a "IN#0" statement.)
|
||||
(FE89)
|
||||
SETKBD LDA #0 ;Pretend using slot 0.
|
||||
INPORT STA A2L
|
||||
INPRT LDX #<KSW ;Set offset from start of zero page to INPUT hook.
|
||||
LDY #<KEYIN
|
||||
(FE91) BNE IOPRT ;ALWAYS.
|
||||
|
||||
(FE9B)
|
||||
IOPRT LDA A2L
|
||||
AND #$0F
|
||||
(FE9F) BEQ IOPRT1 ;ALWAYS.
|
||||
|
||||
(FEA7)
|
||||
IOPRT1 LDA #>COUT1 ;(Hi byte of the addr of KEYIN & COUT1 are equal.)
|
||||
IOPRT2 STY LOC0,X ;Set KSW: KEYIN.
|
||||
STA LOC1,X
|
||||
(FEAD) RTS
|
||||
|
||||
(B747) JMP DOSCOLD ;Jump into DOS's coldstart routine to build
|
||||
------------ ;the DOS buffers and the page-three vector
|
||||
. ;table and then run the "HELLO" program.
|
||||
. ;*************** N O T E *****************
|
||||
. ;* This instruction is a hacker's dream. *
|
||||
. ;* For instance, you can change the jump *
|
||||
. ;* to point to you own password or time- *
|
||||
. ;* bomb routine that you have deviously *
|
||||
. ;* embedded in an unused section of DOS. *
|
||||
. ;*****************************************
|
||||
.
|
||||
.
|
||||
.
|
||||
*---------------------*
|
||||
* SEE dis'mbly titled *
|
||||
* "DOSCOLDSTART" *
|
||||
*---------------------*
|
||||
.
|
||||
.
|
||||
.
|
||||
526
eagle/DB19F adapter/big-mess-o-wires.lbr
Normal file
526
eagle/DB19F adapter/big-mess-o-wires.lbr
Normal file
@ -0,0 +1,526 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.6.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="no" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
|
||||
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="50" name="dxf" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="53" name="tGND_GNDA" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="54" name="bGND_GNDA" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="56" name="wert" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="93" name="Pins" color="2" fill="1" visible="yes" active="yes"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<layer number="102" name="Vscore" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="103" name="fp3" color="7" fill="1" visible="yes" active="yes"/>
|
||||
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|
||||
<layer number="105" name="Beschreib" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="106" name="BGA-Top" color="7" fill="1" visible="yes" active="yes"/>
|
||||
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|
||||
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|
||||
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|
||||
<layer number="110" name="fp0" color="7" fill="1" visible="yes" active="yes"/>
|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
<layer number="144" name="Drill_legend" color="7" fill="1" visible="yes" active="yes"/>
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
<layer number="213" name="213bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="214" name="214bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="215" name="215bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="216" name="216bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="217" name="217bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="218" name="218bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="219" name="219bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="220" name="220bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="221" name="221bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="222" name="222bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="223" name="223bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="224" name="224bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="250" name="Descript" color="7" fill="1" visible="yes" active="yes"/>
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||||
<layer number="251" name="SMDround" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="254" name="cooling" color="7" fill="1" visible="yes" active="yes"/>
|
||||
</layers>
|
||||
<library>
|
||||
<packages>
|
||||
<package name="DB19EDGE">
|
||||
<description><b>SUB-D</b></description>
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
<wire x1="-16.165" y1="-0.695" x2="-16.419" y2="-0.695" width="0.1524" layer="51"/>
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<description><b>CONNECTOR</b><p>
|
||||
series 057 contact pc board low profile headers<p>
|
||||
straight</description>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<pad name="16" x="6.35" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="17" x="8.89" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="18" x="8.89" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="19" x="11.43" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="20" x="11.43" y="1.27" drill="1" diameter="1.778"/>
|
||||
<text x="-11.41" y="-6.88" size="1.778" layer="25">>NAME</text>
|
||||
<text x="-12.16" y="4.55" size="1.778" layer="27">>VALUE</text>
|
||||
</package>
|
||||
<package name="DB19F-EDGE">
|
||||
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||||
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|
||||
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|
||||
<circle x="-23.5204" y="2.54" radius="2.667" width="0" layer="43"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<smd name="8" x="-6.925" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="7" x="-4.155" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="6" x="-1.385" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="5" x="1.385" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="4" x="4.155" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="3" x="6.925" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="2" x="9.695" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="1" x="12.465" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="19" x="-11.08" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="18" x="-8.31" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="17" x="-5.54" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="16" x="-2.77" y="5.54" dx="1.8" dy="5" layer="16"/>
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||||
<smd name="15" x="0" y="5.54" dx="1.8" dy="5" layer="16"/>
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||||
<smd name="14" x="2.77" y="5.54" dx="1.8" dy="5" layer="16"/>
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||||
<smd name="13" x="5.54" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="12" x="8.31" y="5.54" dx="1.8" dy="5" layer="16"/>
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||||
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||||
<text x="-21.59" y="11.43" size="1.778" layer="25" ratio="10">>NAME</text>
|
||||
<text x="-21.59" y="8.89" size="1.778" layer="27" ratio="10">>VALUE</text>
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||||
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|
||||
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|
||||
<symbols>
|
||||
<symbol name="DB19">
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<pin name="9" x="7.62" y="-7.62" visible="pad" length="middle" direction="pas" rot="R180"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<pin name="15" x="-7.62" y="2.54" visible="pad" length="middle" direction="pas"/>
|
||||
<pin name="16" x="-7.62" y="0" visible="pad" length="middle" direction="pas"/>
|
||||
<pin name="17" x="-7.62" y="-2.54" visible="pad" length="middle" direction="pas"/>
|
||||
<pin name="18" x="-7.62" y="-5.08" visible="pad" length="middle" direction="pas"/>
|
||||
<pin name="19" x="-7.62" y="-7.62" visible="pad" length="middle" direction="pas"/>
|
||||
<text x="-3.81" y="-15.875" size="1.778" layer="96">>VALUE</text>
|
||||
<text x="-3.81" y="16.51" size="1.778" layer="95">>NAME</text>
|
||||
</symbol>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<wire x1="3.81" y1="-15.24" x2="3.81" y2="12.7" width="0.4064" layer="94"/>
|
||||
<wire x1="-3.81" y1="12.7" x2="3.81" y2="12.7" width="0.4064" layer="94"/>
|
||||
<wire x1="1.27" y1="-2.54" x2="2.54" y2="-2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="-5.08" x2="2.54" y2="-5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="0" x2="2.54" y2="0" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="2.54" x2="2.54" y2="2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="5.08" x2="2.54" y2="5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="7.62" x2="2.54" y2="7.62" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="10.16" x2="2.54" y2="10.16" width="0.6096" layer="94"/>
|
||||
<pin name="1" x="-7.62" y="10.16" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="2" x="7.62" y="10.16" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="3" x="-7.62" y="7.62" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="4" x="7.62" y="7.62" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="5" x="-7.62" y="5.08" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="6" x="7.62" y="5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="7" x="-7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="8" x="7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="9" x="-7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="10" x="7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="11" x="-7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="12" x="7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="13" x="-7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="14" x="7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="15" x="-7.62" y="-7.62" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="16" x="7.62" y="-7.62" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="17" x="-7.62" y="-10.16" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="18" x="7.62" y="-10.16" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="19" x="-7.62" y="-12.7" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="20" x="7.62" y="-12.7" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<text x="-2.54" y="-17.78" size="1.778" layer="96">>VALUE</text>
|
||||
<text x="-2.54" y="13.97" size="1.778" layer="95">>NAME</text>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="DB19" prefix="X" uservalue="yes">
|
||||
<description><b>SUB-D</b></description>
|
||||
<gates>
|
||||
<gate name="-1" symbol="DB19" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="EDGE" package="DB19EDGE">
|
||||
<connects>
|
||||
<connect gate="-1" pin="1" pad="1"/>
|
||||
<connect gate="-1" pin="10" pad="10"/>
|
||||
<connect gate="-1" pin="11" pad="11"/>
|
||||
<connect gate="-1" pin="12" pad="12"/>
|
||||
<connect gate="-1" pin="13" pad="13"/>
|
||||
<connect gate="-1" pin="14" pad="14"/>
|
||||
<connect gate="-1" pin="15" pad="15"/>
|
||||
<connect gate="-1" pin="16" pad="16"/>
|
||||
<connect gate="-1" pin="17" pad="17"/>
|
||||
<connect gate="-1" pin="18" pad="18"/>
|
||||
<connect gate="-1" pin="19" pad="19"/>
|
||||
<connect gate="-1" pin="2" pad="2"/>
|
||||
<connect gate="-1" pin="3" pad="3"/>
|
||||
<connect gate="-1" pin="4" pad="4"/>
|
||||
<connect gate="-1" pin="5" pad="5"/>
|
||||
<connect gate="-1" pin="6" pad="6"/>
|
||||
<connect gate="-1" pin="7" pad="7"/>
|
||||
<connect gate="-1" pin="8" pad="8"/>
|
||||
<connect gate="-1" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="IDC20">
|
||||
<gates>
|
||||
<gate name="G$1" symbol="M10X2" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="IDC20">
|
||||
<connects>
|
||||
<connect gate="G$1" pin="1" pad="1"/>
|
||||
<connect gate="G$1" pin="10" pad="10"/>
|
||||
<connect gate="G$1" pin="11" pad="11"/>
|
||||
<connect gate="G$1" pin="12" pad="12"/>
|
||||
<connect gate="G$1" pin="13" pad="13"/>
|
||||
<connect gate="G$1" pin="14" pad="14"/>
|
||||
<connect gate="G$1" pin="15" pad="15"/>
|
||||
<connect gate="G$1" pin="16" pad="16"/>
|
||||
<connect gate="G$1" pin="17" pad="17"/>
|
||||
<connect gate="G$1" pin="18" pad="18"/>
|
||||
<connect gate="G$1" pin="19" pad="19"/>
|
||||
<connect gate="G$1" pin="2" pad="2"/>
|
||||
<connect gate="G$1" pin="20" pad="20"/>
|
||||
<connect gate="G$1" pin="3" pad="3"/>
|
||||
<connect gate="G$1" pin="4" pad="4"/>
|
||||
<connect gate="G$1" pin="5" pad="5"/>
|
||||
<connect gate="G$1" pin="6" pad="6"/>
|
||||
<connect gate="G$1" pin="7" pad="7"/>
|
||||
<connect gate="G$1" pin="8" pad="8"/>
|
||||
<connect gate="G$1" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="DB19F">
|
||||
<gates>
|
||||
<gate name="1" symbol="DB19" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="DB19F-EDGE">
|
||||
<connects>
|
||||
<connect gate="1" pin="1" pad="1"/>
|
||||
<connect gate="1" pin="10" pad="10"/>
|
||||
<connect gate="1" pin="11" pad="11"/>
|
||||
<connect gate="1" pin="12" pad="12"/>
|
||||
<connect gate="1" pin="13" pad="13"/>
|
||||
<connect gate="1" pin="14" pad="14"/>
|
||||
<connect gate="1" pin="15" pad="15"/>
|
||||
<connect gate="1" pin="16" pad="16"/>
|
||||
<connect gate="1" pin="17" pad="17"/>
|
||||
<connect gate="1" pin="18" pad="18"/>
|
||||
<connect gate="1" pin="19" pad="19"/>
|
||||
<connect gate="1" pin="2" pad="2"/>
|
||||
<connect gate="1" pin="3" pad="3"/>
|
||||
<connect gate="1" pin="4" pad="4"/>
|
||||
<connect gate="1" pin="5" pad="5"/>
|
||||
<connect gate="1" pin="6" pad="6"/>
|
||||
<connect gate="1" pin="7" pad="7"/>
|
||||
<connect gate="1" pin="8" pad="8"/>
|
||||
<connect gate="1" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
</eagle>
|
||||
575
eagle/DB19F adapter/db19f.brd
Normal file
575
eagle/DB19F adapter/db19f.brd
Normal file
@ -0,0 +1,575 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.6.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="yes"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.025" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="14" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="yes"/>
|
||||
<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="yes"/>
|
||||
<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="yes"/>
|
||||
<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="yes"/>
|
||||
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="45" name="Holes" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
|
||||
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="48" name="Document" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="49" name="Reference" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="50" name="dxf" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="51" name="tDocu" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="53" name="tGND_GNDA" color="7" fill="9" visible="no" active="no"/>
|
||||
<layer number="54" name="bGND_GNDA" color="1" fill="9" visible="no" active="no"/>
|
||||
<layer number="56" name="wert" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="91" name="Nets" color="2" fill="1" visible="no" active="no"/>
|
||||
<layer number="92" name="Busses" color="1" fill="1" visible="no" active="no"/>
|
||||
<layer number="93" name="Pins" color="2" fill="1" visible="no" active="no"/>
|
||||
<layer number="94" name="Symbols" color="4" fill="1" visible="no" active="no"/>
|
||||
<layer number="95" name="Names" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="96" name="Values" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="97" name="Info" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="98" name="Guide" color="6" fill="1" visible="no" active="no"/>
|
||||
<layer number="100" name="Muster" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="101" name="Patch_Top" color="12" fill="4" visible="no" active="yes"/>
|
||||
<layer number="102" name="Vscore" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="103" name="fp3" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="104" name="Name" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="105" name="Beschreib" color="9" fill="1" visible="no" active="yes"/>
|
||||
<layer number="106" name="BGA-Top" color="4" fill="1" visible="no" active="yes"/>
|
||||
<layer number="107" name="BD-Top" color="5" fill="1" visible="no" active="yes"/>
|
||||
<layer number="108" name="fp8" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="109" name="fp9" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="110" name="fp0" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="116" name="Patch_BOT" color="9" fill="4" visible="no" active="yes"/>
|
||||
<layer number="121" name="_tsilk" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="122" name="_bsilk" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="123" name="tTestmark" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="124" name="bTestmark" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="125" name="_tNames" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="131" name="tAdjust" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="132" name="bAdjust" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="144" name="Drill_legend" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="151" name="HeatSink" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="199" name="Contour" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="200" name="200bmp" color="1" fill="10" visible="no" active="yes"/>
|
||||
<layer number="201" name="201bmp" color="2" fill="10" visible="no" active="yes"/>
|
||||
<layer number="202" name="202bmp" color="3" fill="1" visible="no" active="no"/>
|
||||
<layer number="203" name="203bmp" color="4" fill="10" visible="no" active="yes"/>
|
||||
<layer number="204" name="204bmp" color="5" fill="10" visible="no" active="yes"/>
|
||||
<layer number="205" name="205bmp" color="6" fill="10" visible="no" active="yes"/>
|
||||
<layer number="206" name="206bmp" color="7" fill="10" visible="no" active="yes"/>
|
||||
<layer number="207" name="207bmp" color="8" fill="10" visible="no" active="yes"/>
|
||||
<layer number="208" name="208bmp" color="9" fill="10" visible="no" active="yes"/>
|
||||
<layer number="209" name="209bmp" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="210" name="210bmp" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="211" name="211bmp" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="212" name="212bmp" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="213" name="213bmp" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="214" name="214bmp" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="215" name="215bmp" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="216" name="216bmp" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="217" name="217bmp" color="18" fill="1" visible="no" active="no"/>
|
||||
<layer number="218" name="218bmp" color="19" fill="1" visible="no" active="no"/>
|
||||
<layer number="219" name="219bmp" color="20" fill="1" visible="no" active="no"/>
|
||||
<layer number="220" name="220bmp" color="21" fill="1" visible="no" active="no"/>
|
||||
<layer number="221" name="221bmp" color="22" fill="1" visible="no" active="no"/>
|
||||
<layer number="222" name="222bmp" color="23" fill="1" visible="no" active="no"/>
|
||||
<layer number="223" name="223bmp" color="24" fill="1" visible="no" active="no"/>
|
||||
<layer number="224" name="224bmp" color="25" fill="1" visible="no" active="no"/>
|
||||
<layer number="250" name="Descript" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="251" name="SMDround" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="254" name="cooling" color="7" fill="1" visible="no" active="yes"/>
|
||||
</layers>
|
||||
<board>
|
||||
<plain>
|
||||
<wire x1="0" y1="0" x2="17.45" y2="0" width="0" layer="20"/>
|
||||
<wire x1="17.45" y1="0" x2="17.45" y2="44.492" width="0" layer="20"/>
|
||||
<wire x1="17.45" y1="44.492" x2="0" y2="44.492" width="0" layer="20"/>
|
||||
<wire x1="0" y1="44.492" x2="0" y2="0" width="0" layer="20"/>
|
||||
<text x="7.0612" y="37.0332" size="1.27" layer="22" font="vector" ratio="15" rot="MR270">DB19F WWW.BIGMESSOWIRES.COM</text>
|
||||
</plain>
|
||||
<libraries>
|
||||
<library name="big-mess-o-wires">
|
||||
<packages>
|
||||
<package name="DB19F-EDGE">
|
||||
<circle x="23.5204" y="2.54" radius="2.667" width="0" layer="42"/>
|
||||
<circle x="23.5204" y="2.54" radius="2.667" width="0" layer="43"/>
|
||||
<circle x="-23.5204" y="2.54" radius="2.667" width="0" layer="42"/>
|
||||
<circle x="-23.5204" y="2.54" radius="2.667" width="0" layer="43"/>
|
||||
<wire x1="15.839" y1="-8.061" x2="16.347" y2="-7.553" width="0.1524" layer="51" curve="90"/>
|
||||
<wire x1="-15.657" y1="-7.553" x2="-15.149" y2="-8.061" width="0.1524" layer="51" curve="90"/>
|
||||
<wire x1="17.998" y1="-1.203" x2="17.998" y2="-1.711" width="0.1524" layer="51"/>
|
||||
<wire x1="17.998" y1="-1.203" x2="17.871" y2="-1.203" width="0.1524" layer="51"/>
|
||||
<wire x1="17.236" y1="1.845" x2="17.871" y2="1.21" width="0.1524" layer="51" curve="-90"/>
|
||||
<wire x1="17.109" y1="1.845" x2="16.855" y2="1.845" width="0.1524" layer="51"/>
|
||||
<wire x1="17.871" y1="1.21" x2="17.871" y2="-1.203" width="0.1524" layer="51"/>
|
||||
<wire x1="16.855" y1="1.845" x2="16.855" y2="2.607" width="0.1524" layer="51"/>
|
||||
<wire x1="16.855" y1="1.845" x2="-16.165" y2="1.845" width="0.1524" layer="51"/>
|
||||
<wire x1="16.855" y1="2.607" x2="-16.165" y2="2.607" width="0.1524" layer="51"/>
|
||||
<wire x1="-16.165" y1="1.845" x2="-16.165" y2="2.607" width="0.1524" layer="51"/>
|
||||
<wire x1="-16.165" y1="1.845" x2="-16.419" y2="1.845" width="0.1524" layer="51"/>
|
||||
<wire x1="-17.308" y1="-1.203" x2="-17.308" y2="-1.711" width="0.1524" layer="51"/>
|
||||
<wire x1="-17.181" y1="1.21" x2="-17.181" y2="-1.203" width="0.1524" layer="51"/>
|
||||
<wire x1="-17.181" y1="-1.203" x2="-17.308" y2="-1.203" width="0.1524" layer="51"/>
|
||||
<wire x1="-17.181" y1="1.21" x2="-16.546" y2="1.845" width="0.1524" layer="51" curve="-90"/>
|
||||
<wire x1="22.5125" y1="-2.219" x2="18.252" y2="-2.219" width="0.1524" layer="51"/>
|
||||
<wire x1="18.252" y1="-2.219" x2="-16.292" y2="-2.219" width="0.1524" layer="51"/>
|
||||
<wire x1="-16.292" y1="-2.219" x2="-22.388" y2="-2.219" width="0.1524" layer="51"/>
|
||||
<wire x1="-15.657" y1="-2.854" x2="-15.657" y2="-7.553" width="0.1524" layer="51"/>
|
||||
<wire x1="-16.292" y1="-2.219" x2="-15.657" y2="-2.854" width="0.1524" layer="51" curve="-90"/>
|
||||
<wire x1="16.347" y1="-2.854" x2="16.347" y2="-7.553" width="0.1524" layer="51"/>
|
||||
<wire x1="16.347" y1="-2.854" x2="18.252" y2="-2.219" width="0.1524" layer="51" curve="-90"/>
|
||||
<wire x1="15.839" y1="-8.061" x2="-15.149" y2="-8.061" width="0.1524" layer="51"/>
|
||||
<wire x1="-12.465" y1="2.54" x2="-12.465" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="-9.695" y1="2.54" x2="-9.695" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="-6.925" y1="2.54" x2="-6.925" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="-4.155" y1="2.54" x2="-4.155" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="-1.385" y1="2.54" x2="-1.385" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="1.385" y1="2.54" x2="1.385" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="4.155" y1="2.54" x2="4.155" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="6.925" y1="2.54" x2="6.925" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="9.695" y1="2.54" x2="9.695" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="12.465" y1="2.54" x2="12.465" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="-11.08" y1="2.54" x2="-11.08" y2="5.31" width="1.27" layer="52"/>
|
||||
<wire x1="-8.31" y1="2.54" x2="-8.31" y2="5.31" width="1.27" layer="52"/>
|
||||
<wire x1="-5.54" y1="2.54" x2="-5.54" y2="5.31" width="1.27" layer="52"/>
|
||||
<wire x1="-2.77" y1="2.54" x2="-2.77" y2="5.31" width="1.27" layer="52"/>
|
||||
<wire x1="0" y1="2.54" x2="0" y2="5.31" width="1.27" layer="52"/>
|
||||
<wire x1="2.77" y1="2.54" x2="2.77" y2="5.31" width="1.27" layer="52"/>
|
||||
<wire x1="5.54" y1="2.54" x2="5.54" y2="5.31" width="1.27" layer="52"/>
|
||||
<wire x1="8.31" y1="2.54" x2="8.31" y2="5.31" width="1.27" layer="52"/>
|
||||
<wire x1="11.08" y1="2.54" x2="11.08" y2="5.31" width="1.27" layer="52"/>
|
||||
<wire x1="-16.62" y1="2.54" x2="-16.62" y2="8.08" width="0.127" layer="21"/>
|
||||
<wire x1="-16.62" y1="8.08" x2="16.62" y2="8.08" width="0.127" layer="21"/>
|
||||
<wire x1="16.62" y1="8.08" x2="16.62" y2="2.54" width="0.127" layer="21"/>
|
||||
<wire x1="-22.16" y1="-1.615" x2="-22.16" y2="8.08" width="0.127" layer="51"/>
|
||||
<wire x1="-22.16" y1="8.08" x2="-16.62" y2="8.08" width="0.127" layer="51"/>
|
||||
<wire x1="16.62" y1="8.08" x2="22.16" y2="8.08" width="0.127" layer="51"/>
|
||||
<wire x1="22.16" y1="8.08" x2="22.16" y2="-1.615" width="0.127" layer="51"/>
|
||||
<rectangle x1="-22.388" y1="-2.219" x2="22.388" y2="-1.711" layer="51"/>
|
||||
<smd name="10" x="-12.465" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="9" x="-9.695" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="8" x="-6.925" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="7" x="-4.155" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="6" x="-1.385" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="5" x="1.385" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="4" x="4.155" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="3" x="6.925" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="2" x="9.695" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="1" x="12.465" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="19" x="-11.08" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="18" x="-8.31" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="17" x="-5.54" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="16" x="-2.77" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="15" x="0" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="14" x="2.77" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="13" x="5.54" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="12" x="8.31" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="11" x="11.08" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<text x="-21.59" y="11.43" size="1.778" layer="25" ratio="10">>NAME</text>
|
||||
<text x="-21.59" y="8.89" size="1.778" layer="27" ratio="10">>VALUE</text>
|
||||
<text x="15.9375" y="5.31" size="1.6764" layer="21" rot="R90">1</text>
|
||||
<text x="-14.5525" y="3.925" size="1.6764" layer="21" rot="R90">10</text>
|
||||
<text x="15.36" y="6.7525" size="1.6764" layer="22" rot="MR270">11</text>
|
||||
<text x="-13.975" y="6.7525" size="1.6764" layer="22" rot="MR270">19</text>
|
||||
</package>
|
||||
<package name="IDC20">
|
||||
<description><b>CONNECTOR</b><p>
|
||||
series 057 contact pc board low profile headers<p>
|
||||
straight</description>
|
||||
<wire x1="-1.9" y1="-3.0025" x2="-1.9" y2="-4.03" width="0.2032" layer="21"/>
|
||||
<wire x1="1.9" y1="-3.0025" x2="1.9" y2="-4.03" width="0.2032" layer="21"/>
|
||||
<wire x1="-13.85" y1="-1.97" x2="-13.15" y2="-3.04" width="0.4064" layer="21"/>
|
||||
<wire x1="-13.15" y1="-3.04" x2="-12.45" y2="-1.97" width="0.4064" layer="21"/>
|
||||
<wire x1="-12.45" y1="-1.97" x2="-13.85" y2="-1.97" width="0.4064" layer="21"/>
|
||||
<wire x1="-16.56" y1="-4.1" x2="-16.56" y2="4.1" width="0.2032" layer="21"/>
|
||||
<wire x1="-16.56" y1="-4.1" x2="16.56" y2="-4.1" width="0.2032" layer="21"/>
|
||||
<wire x1="16.56" y1="-4.1" x2="16.56" y2="4.1" width="0.2032" layer="21"/>
|
||||
<wire x1="16.56" y1="4.1" x2="-16.56" y2="4.1" width="0.2032" layer="21"/>
|
||||
<wire x1="-15.76" y1="-3.3" x2="-15.76" y2="3.3" width="0.2032" layer="51"/>
|
||||
<wire x1="-15.76" y1="3.3" x2="15.76" y2="3.3" width="0.2032" layer="51"/>
|
||||
<wire x1="15.76" y1="3.3" x2="15.76" y2="-3.3" width="0.2032" layer="51"/>
|
||||
<wire x1="15.76" y1="-3.3" x2="1.9" y2="-3.3" width="0.2032" layer="51"/>
|
||||
<wire x1="-1.9" y1="-3.3" x2="-15.76" y2="-3.3" width="0.2032" layer="51"/>
|
||||
<wire x1="-1.905" y1="-2.8575" x2="1.905" y2="-2.8575" width="0.2032" layer="21"/>
|
||||
<pad name="1" x="-11.43" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="2" x="-11.43" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="3" x="-8.89" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="4" x="-8.89" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="5" x="-6.35" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="6" x="-6.35" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="7" x="-3.81" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="8" x="-3.81" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="9" x="-1.27" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="10" x="-1.27" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="11" x="1.27" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="12" x="1.27" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="13" x="3.81" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="14" x="3.81" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="15" x="6.35" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="16" x="6.35" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="17" x="8.89" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="18" x="8.89" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="19" x="11.43" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="20" x="11.43" y="1.27" drill="1" diameter="1.778"/>
|
||||
<text x="-11.41" y="-6.88" size="1.778" layer="25">>NAME</text>
|
||||
<text x="-12.16" y="4.55" size="1.778" layer="27">>VALUE</text>
|
||||
</package>
|
||||
</packages>
|
||||
</library>
|
||||
</libraries>
|
||||
<attributes>
|
||||
</attributes>
|
||||
<variantdefs>
|
||||
</variantdefs>
|
||||
<classes>
|
||||
<class number="0" name="default" width="0" drill="0">
|
||||
</class>
|
||||
</classes>
|
||||
<designrules name="oshpark-2layer *">
|
||||
<description language="de"><b>EAGLE Design Rules</b>
|
||||
<p>
|
||||
Die Standard-Design-Rules sind so gewählt, dass sie für
|
||||
die meisten Anwendungen passen. Sollte ihre Platine
|
||||
besondere Anforderungen haben, treffen Sie die erforderlichen
|
||||
Einstellungen hier und speichern die Design Rules unter
|
||||
einem neuen Namen ab.</description>
|
||||
<description language="en"><b>Laen's PCB Order Design Rules</b>
|
||||
<p>
|
||||
Please make sure your boards conform to these design rules.</description>
|
||||
<param name="layerSetup" value="(1*16)"/>
|
||||
<param name="mtCopper" value="0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm"/>
|
||||
<param name="mtIsolate" value="1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm"/>
|
||||
<param name="mdWireWire" value="6mil"/>
|
||||
<param name="mdWirePad" value="6mil"/>
|
||||
<param name="mdWireVia" value="6mil"/>
|
||||
<param name="mdPadPad" value="6mil"/>
|
||||
<param name="mdPadVia" value="6mil"/>
|
||||
<param name="mdViaVia" value="6mil"/>
|
||||
<param name="mdSmdPad" value="6mil"/>
|
||||
<param name="mdSmdVia" value="6mil"/>
|
||||
<param name="mdSmdSmd" value="6mil"/>
|
||||
<param name="mdViaViaSameLayer" value="8mil"/>
|
||||
<param name="mnLayersViaInSmd" value="2"/>
|
||||
<param name="mdCopperDimension" value="15mil"/>
|
||||
<param name="mdDrill" value="6mil"/>
|
||||
<param name="mdSmdStop" value="0mil"/>
|
||||
<param name="msWidth" value="6mil"/>
|
||||
<param name="msDrill" value="13mil"/>
|
||||
<param name="msMicroVia" value="13mil"/>
|
||||
<param name="msBlindViaRatio" value="0.5"/>
|
||||
<param name="rvPadTop" value="0.25"/>
|
||||
<param name="rvPadInner" value="0.25"/>
|
||||
<param name="rvPadBottom" value="0.25"/>
|
||||
<param name="rvViaOuter" value="0.25"/>
|
||||
<param name="rvViaInner" value="0.25"/>
|
||||
<param name="rvMicroViaOuter" value="0.25"/>
|
||||
<param name="rvMicroViaInner" value="0.25"/>
|
||||
<param name="rlMinPadTop" value="7mil"/>
|
||||
<param name="rlMaxPadTop" value="20mil"/>
|
||||
<param name="rlMinPadInner" value="7mil"/>
|
||||
<param name="rlMaxPadInner" value="20mil"/>
|
||||
<param name="rlMinPadBottom" value="7mil"/>
|
||||
<param name="rlMaxPadBottom" value="20mil"/>
|
||||
<param name="rlMinViaOuter" value="7mil"/>
|
||||
<param name="rlMaxViaOuter" value="20mil"/>
|
||||
<param name="rlMinViaInner" value="7mil"/>
|
||||
<param name="rlMaxViaInner" value="20mil"/>
|
||||
<param name="rlMinMicroViaOuter" value="4mil"/>
|
||||
<param name="rlMaxMicroViaOuter" value="20mil"/>
|
||||
<param name="rlMinMicroViaInner" value="4mil"/>
|
||||
<param name="rlMaxMicroViaInner" value="20mil"/>
|
||||
<param name="psTop" value="-1"/>
|
||||
<param name="psBottom" value="-1"/>
|
||||
<param name="psFirst" value="-1"/>
|
||||
<param name="psElongationLong" value="100"/>
|
||||
<param name="psElongationOffset" value="100"/>
|
||||
<param name="mvStopFrame" value="1"/>
|
||||
<param name="mvCreamFrame" value="0"/>
|
||||
<param name="mlMinStopFrame" value="2.5mil"/>
|
||||
<param name="mlMaxStopFrame" value="2.5mil"/>
|
||||
<param name="mlMinCreamFrame" value="0mil"/>
|
||||
<param name="mlMaxCreamFrame" value="0mil"/>
|
||||
<param name="mlViaStopLimit" value="15mil"/>
|
||||
<param name="srRoundness" value="0"/>
|
||||
<param name="srMinRoundness" value="0mil"/>
|
||||
<param name="srMaxRoundness" value="0mil"/>
|
||||
<param name="slThermalIsolate" value="10mil"/>
|
||||
<param name="slThermalsForVias" value="0"/>
|
||||
<param name="dpMaxLengthDifference" value="10mm"/>
|
||||
<param name="dpGapFactor" value="2.5"/>
|
||||
<param name="checkGrid" value="0"/>
|
||||
<param name="checkAngle" value="0"/>
|
||||
<param name="checkFont" value="1"/>
|
||||
<param name="checkRestrict" value="1"/>
|
||||
<param name="useDiameter" value="13"/>
|
||||
<param name="maxErrors" value="50"/>
|
||||
</designrules>
|
||||
<autorouter>
|
||||
<pass name="Default">
|
||||
<param name="RoutingGrid" value="50mil"/>
|
||||
<param name="tpViaShape" value="round"/>
|
||||
<param name="PrefDir.1" value="|"/>
|
||||
<param name="PrefDir.2" value="0"/>
|
||||
<param name="PrefDir.3" value="0"/>
|
||||
<param name="PrefDir.4" value="0"/>
|
||||
<param name="PrefDir.5" value="0"/>
|
||||
<param name="PrefDir.6" value="0"/>
|
||||
<param name="PrefDir.7" value="0"/>
|
||||
<param name="PrefDir.8" value="0"/>
|
||||
<param name="PrefDir.9" value="0"/>
|
||||
<param name="PrefDir.10" value="0"/>
|
||||
<param name="PrefDir.11" value="0"/>
|
||||
<param name="PrefDir.12" value="0"/>
|
||||
<param name="PrefDir.13" value="0"/>
|
||||
<param name="PrefDir.14" value="0"/>
|
||||
<param name="PrefDir.15" value="0"/>
|
||||
<param name="PrefDir.16" value="-"/>
|
||||
<param name="cfVia" value="8"/>
|
||||
<param name="cfNonPref" value="5"/>
|
||||
<param name="cfChangeDir" value="2"/>
|
||||
<param name="cfOrthStep" value="2"/>
|
||||
<param name="cfDiagStep" value="3"/>
|
||||
<param name="cfExtdStep" value="0"/>
|
||||
<param name="cfBonusStep" value="1"/>
|
||||
<param name="cfMalusStep" value="1"/>
|
||||
<param name="cfPadImpact" value="4"/>
|
||||
<param name="cfSmdImpact" value="4"/>
|
||||
<param name="cfBusImpact" value="0"/>
|
||||
<param name="cfHugging" value="3"/>
|
||||
<param name="cfAvoid" value="4"/>
|
||||
<param name="cfPolygon" value="10"/>
|
||||
<param name="cfBase.1" value="0"/>
|
||||
<param name="cfBase.2" value="1"/>
|
||||
<param name="cfBase.3" value="1"/>
|
||||
<param name="cfBase.4" value="1"/>
|
||||
<param name="cfBase.5" value="1"/>
|
||||
<param name="cfBase.6" value="1"/>
|
||||
<param name="cfBase.7" value="1"/>
|
||||
<param name="cfBase.8" value="1"/>
|
||||
<param name="cfBase.9" value="1"/>
|
||||
<param name="cfBase.10" value="1"/>
|
||||
<param name="cfBase.11" value="1"/>
|
||||
<param name="cfBase.12" value="1"/>
|
||||
<param name="cfBase.13" value="1"/>
|
||||
<param name="cfBase.14" value="1"/>
|
||||
<param name="cfBase.15" value="1"/>
|
||||
<param name="cfBase.16" value="0"/>
|
||||
<param name="mnVias" value="20"/>
|
||||
<param name="mnSegments" value="9999"/>
|
||||
<param name="mnExtdSteps" value="9999"/>
|
||||
<param name="mnRipupLevel" value="10"/>
|
||||
<param name="mnRipupSteps" value="100"/>
|
||||
<param name="mnRipupTotal" value="100"/>
|
||||
</pass>
|
||||
<pass name="Follow-me" refer="Default" active="yes">
|
||||
</pass>
|
||||
<pass name="Busses" refer="Default" active="yes">
|
||||
<param name="cfNonPref" value="4"/>
|
||||
<param name="cfBusImpact" value="4"/>
|
||||
<param name="cfHugging" value="0"/>
|
||||
<param name="mnVias" value="0"/>
|
||||
</pass>
|
||||
<pass name="Route" refer="Default" active="yes">
|
||||
</pass>
|
||||
</autorouter>
|
||||
<elements>
|
||||
<element name="J3" library="big-mess-o-wires" package="DB19F-EDGE" value="DB19" x="-2.5146" y="22.225" rot="R270"/>
|
||||
<element name="J2" library="big-mess-o-wires" package="IDC20" value="IDC20" x="11.43" y="22.225" rot="R90"/>
|
||||
</elements>
|
||||
<signals>
|
||||
<signal name="GND">
|
||||
<contactref element="J2" pad="3"/>
|
||||
<contactref element="J2" pad="1"/>
|
||||
<contactref element="J3" pad="1"/>
|
||||
<contactref element="J3" pad="2"/>
|
||||
<polygon width="0.1524" layer="1" isolate="0.6096">
|
||||
<vertex x="0.508" y="0.508"/>
|
||||
<vertex x="16.764" y="0.508"/>
|
||||
<vertex x="16.764" y="43.688"/>
|
||||
<vertex x="0.508" y="43.688"/>
|
||||
</polygon>
|
||||
<polygon width="0.1524" layer="16" isolate="0.6096">
|
||||
<vertex x="0.508" y="0.508"/>
|
||||
<vertex x="16.764" y="0.508"/>
|
||||
<vertex x="16.764" y="43.688"/>
|
||||
<vertex x="0.508" y="43.688"/>
|
||||
</polygon>
|
||||
<contactref element="J3" pad="3"/>
|
||||
<wire x1="3.0254" y1="9.76" x2="3.0254" y2="12.53" width="0.6096" layer="1"/>
|
||||
<wire x1="3.0254" y1="12.53" x2="3.0254" y2="15.3" width="0.6096" layer="1"/>
|
||||
<wire x1="12.7" y1="13.335" x2="12.7" y2="10.795" width="0.6096" layer="1"/>
|
||||
<wire x1="12.7" y1="13.335" x2="12.7" y2="9.525" width="0.6096" layer="1"/>
|
||||
<wire x1="12.7" y1="9.525" x2="11.43" y2="8.255" width="0.6096" layer="1"/>
|
||||
<wire x1="11.43" y1="8.255" x2="8.89" y2="8.255" width="0.6096" layer="1"/>
|
||||
<wire x1="8.89" y1="8.255" x2="7.385" y2="9.76" width="0.6096" layer="1"/>
|
||||
<wire x1="7.385" y1="9.76" x2="3.0254" y2="9.76" width="0.6096" layer="1"/>
|
||||
</signal>
|
||||
<signal name="+5V">
|
||||
<contactref element="J2" pad="11"/>
|
||||
<contactref element="J3" pad="6"/>
|
||||
<wire x1="12.7" y1="23.495" x2="11.43" y2="22.225" width="0.6096" layer="1"/>
|
||||
<wire x1="11.43" y1="22.225" x2="8.89" y2="22.225" width="0.254" layer="1"/>
|
||||
<wire x1="8.89" y1="22.225" x2="7.62" y2="23.495" width="0.6096" layer="1"/>
|
||||
<wire x1="7.62" y1="23.495" x2="7.505" y2="23.61" width="0.6096" layer="1"/>
|
||||
<wire x1="7.505" y1="23.61" x2="3.0254" y2="23.61" width="0.6096" layer="1"/>
|
||||
<wire x1="12.7" y1="23.495" x2="11.43" y2="22.225" width="0.6096" layer="16"/>
|
||||
<wire x1="11.43" y1="22.225" x2="8.89" y2="22.225" width="0.254" layer="16"/>
|
||||
<wire x1="8.89" y1="22.225" x2="7.62" y2="23.495" width="0.6096" layer="16"/>
|
||||
<via x="7.62" y="23.495" extent="1-16" drill="0.381"/>
|
||||
</signal>
|
||||
<signal name="PH0">
|
||||
<contactref element="J2" pad="2"/>
|
||||
<contactref element="J3" pad="11"/>
|
||||
<wire x1="10.16" y1="10.795" x2="9.81" y2="11.145" width="0.6096" layer="16"/>
|
||||
<wire x1="9.81" y1="11.145" x2="3.0254" y2="11.145" width="0.6096" layer="16"/>
|
||||
</signal>
|
||||
<signal name="PH1">
|
||||
<contactref element="J2" pad="4"/>
|
||||
<contactref element="J3" pad="12"/>
|
||||
<wire x1="10.16" y1="13.335" x2="9.58" y2="13.915" width="0.6096" layer="16"/>
|
||||
<wire x1="9.58" y1="13.915" x2="3.0254" y2="13.915" width="0.6096" layer="16"/>
|
||||
</signal>
|
||||
<signal name="PH2">
|
||||
<contactref element="J2" pad="6"/>
|
||||
<contactref element="J3" pad="13"/>
|
||||
<wire x1="10.16" y1="15.875" x2="9.35" y2="16.685" width="0.6096" layer="16"/>
|
||||
<wire x1="9.35" y1="16.685" x2="3.0254" y2="16.685" width="0.6096" layer="16"/>
|
||||
</signal>
|
||||
<signal name="PH3">
|
||||
<contactref element="J2" pad="8"/>
|
||||
<contactref element="J3" pad="14"/>
|
||||
<wire x1="10.16" y1="18.415" x2="6.985" y2="18.415" width="0.6096" layer="16"/>
|
||||
<wire x1="6.985" y1="18.415" x2="5.945" y2="19.455" width="0.6096" layer="16"/>
|
||||
<wire x1="5.945" y1="19.455" x2="3.0254" y2="19.455" width="0.6096" layer="16"/>
|
||||
</signal>
|
||||
<signal name="/WREQ">
|
||||
<contactref element="J2" pad="10"/>
|
||||
<contactref element="J3" pad="15"/>
|
||||
<wire x1="7.62" y1="22.225" x2="3.0254" y2="22.225" width="0.254" layer="16"/>
|
||||
<wire x1="7.62" y1="22.225" x2="8.89" y2="20.955" width="0.254" layer="16"/>
|
||||
<wire x1="8.89" y1="20.955" x2="10.16" y2="20.955" width="0.254" layer="16"/>
|
||||
</signal>
|
||||
<signal name="SEL">
|
||||
<contactref element="J2" pad="12"/>
|
||||
<contactref element="J3" pad="16"/>
|
||||
<wire x1="10.16" y1="23.495" x2="8.66" y2="24.995" width="0.6096" layer="16"/>
|
||||
<wire x1="8.66" y1="24.995" x2="3.0254" y2="24.995" width="0.6096" layer="16"/>
|
||||
</signal>
|
||||
<signal name="RD">
|
||||
<contactref element="J2" pad="16"/>
|
||||
<contactref element="J3" pad="18"/>
|
||||
<wire x1="10.16" y1="28.575" x2="8.2" y2="30.535" width="0.6096" layer="16"/>
|
||||
<wire x1="8.2" y1="30.535" x2="3.0254" y2="30.535" width="0.6096" layer="16"/>
|
||||
</signal>
|
||||
<signal name="WR">
|
||||
<contactref element="J2" pad="18"/>
|
||||
<contactref element="J3" pad="19"/>
|
||||
<wire x1="10.16" y1="31.115" x2="7.97" y2="33.305" width="0.6096" layer="16"/>
|
||||
<wire x1="7.97" y1="33.305" x2="3.0254" y2="33.305" width="0.6096" layer="16"/>
|
||||
</signal>
|
||||
<signal name="/ENBL1">
|
||||
<contactref element="J3" pad="17"/>
|
||||
<contactref element="J2" pad="14"/>
|
||||
<wire x1="10.16" y1="26.035" x2="8.43" y2="27.765" width="0.6096" layer="16"/>
|
||||
<wire x1="8.43" y1="27.765" x2="3.0254" y2="27.765" width="0.6096" layer="16"/>
|
||||
</signal>
|
||||
<signal name="SENSE">
|
||||
<contactref element="J3" pad="10"/>
|
||||
<contactref element="J2" pad="20"/>
|
||||
<wire x1="10.16" y1="33.655" x2="6.731" y2="37.084" width="0.6096" layer="16"/>
|
||||
<wire x1="6.731" y1="37.084" x2="5.08" y2="37.084" width="0.6096" layer="16"/>
|
||||
<via x="5.08" y="37.084" extent="1-16" drill="0.381"/>
|
||||
<wire x1="5.08" y1="37.084" x2="3.0254" y2="35.0294" width="0.6096" layer="1"/>
|
||||
<wire x1="3.0254" y1="35.0294" x2="3.0254" y2="34.69" width="0.6096" layer="1"/>
|
||||
</signal>
|
||||
<signal name="/ENBL2">
|
||||
<contactref element="J3" pad="9"/>
|
||||
<contactref element="J2" pad="5"/>
|
||||
<wire x1="3.0254" y1="31.92" x2="3.1094" y2="32.004" width="0.6096" layer="1"/>
|
||||
<wire x1="3.1094" y1="32.004" x2="6.096" y2="32.004" width="0.254" layer="1"/>
|
||||
<wire x1="6.096" y1="32.004" x2="7.112" y2="33.02" width="0.254" layer="1"/>
|
||||
<wire x1="7.112" y1="33.02" x2="7.112" y2="36.068" width="0.254" layer="1"/>
|
||||
<wire x1="7.112" y1="36.068" x2="8.255" y2="37.211" width="0.254" layer="1"/>
|
||||
<wire x1="8.255" y1="37.211" x2="8.89" y2="37.465" width="0.254" layer="1"/>
|
||||
<wire x1="8.89" y1="37.465" x2="12.7" y2="37.465" width="0.254" layer="1"/>
|
||||
<wire x1="12.7" y1="37.465" x2="14.605" y2="35.56" width="0.254" layer="1"/>
|
||||
<wire x1="14.605" y1="35.56" x2="14.605" y2="17.78" width="0.254" layer="1"/>
|
||||
<wire x1="14.605" y1="17.78" x2="12.7" y2="15.875" width="0.254" layer="1"/>
|
||||
</signal>
|
||||
<signal name="/EN35">
|
||||
<contactref element="J2" pad="7"/>
|
||||
<contactref element="J3" pad="4"/>
|
||||
<wire x1="12.7" y1="18.415" x2="11.43" y2="17.145" width="0.254" layer="1"/>
|
||||
<wire x1="11.43" y1="17.145" x2="8.89" y2="17.145" width="0.254" layer="1"/>
|
||||
<wire x1="8.89" y1="17.145" x2="7.965" y2="18.07" width="0.254" layer="1"/>
|
||||
<wire x1="7.965" y1="18.07" x2="3.0254" y2="18.07" width="0.254" layer="1"/>
|
||||
</signal>
|
||||
<signal name="-12V">
|
||||
<contactref element="J2" pad="9"/>
|
||||
<contactref element="J3" pad="5"/>
|
||||
<wire x1="12.7" y1="20.955" x2="11.43" y2="19.685" width="0.6096" layer="1"/>
|
||||
<wire x1="11.43" y1="19.685" x2="8.89" y2="19.685" width="0.254" layer="1"/>
|
||||
<wire x1="8.89" y1="19.685" x2="7.62" y2="20.955" width="0.6096" layer="1"/>
|
||||
<wire x1="7.62" y1="20.955" x2="3.1404" y2="20.955" width="0.6096" layer="1"/>
|
||||
<wire x1="3.1404" y1="20.955" x2="3.0254" y2="20.84" width="0.254" layer="1"/>
|
||||
<via x="7.62" y="20.955" extent="1-16" drill="0.381"/>
|
||||
<wire x1="12.7" y1="20.955" x2="11.43" y2="19.685" width="0.6096" layer="16"/>
|
||||
<wire x1="11.43" y1="19.685" x2="8.89" y2="19.685" width="0.254" layer="16"/>
|
||||
<wire x1="8.89" y1="19.685" x2="7.62" y2="20.955" width="0.6096" layer="16"/>
|
||||
</signal>
|
||||
<signal name="+12V">
|
||||
<contactref element="J2" pad="13"/>
|
||||
<contactref element="J2" pad="15"/>
|
||||
<contactref element="J3" pad="7"/>
|
||||
<contactref element="J3" pad="8"/>
|
||||
<contactref element="J2" pad="17"/>
|
||||
<contactref element="J2" pad="19"/>
|
||||
<wire x1="3.0254" y1="26.38" x2="3.0254" y2="29.15" width="0.6096" layer="1"/>
|
||||
<wire x1="12.7" y1="33.655" x2="12.7" y2="31.115" width="0.6096" layer="1"/>
|
||||
<wire x1="12.7" y1="31.115" x2="12.7" y2="28.575" width="0.6096" layer="1"/>
|
||||
<wire x1="12.7" y1="28.575" x2="12.7" y2="26.035" width="0.6096" layer="1"/>
|
||||
<wire x1="12.7" y1="28.575" x2="12.7" y2="35.052" width="0.6096" layer="1"/>
|
||||
<wire x1="12.7" y1="35.052" x2="11.684" y2="36.068" width="0.6096" layer="1"/>
|
||||
<wire x1="11.684" y1="36.068" x2="9.652" y2="36.068" width="0.6096" layer="1"/>
|
||||
<wire x1="9.652" y1="36.068" x2="8.128" y2="34.544" width="0.6096" layer="1"/>
|
||||
<wire x1="8.128" y1="34.544" x2="8.128" y2="30.48" width="0.6096" layer="1"/>
|
||||
<wire x1="8.128" y1="30.48" x2="6.798" y2="29.15" width="0.6096" layer="1"/>
|
||||
<wire x1="6.798" y1="29.15" x2="3.0254" y2="29.15" width="0.6096" layer="1"/>
|
||||
</signal>
|
||||
</signals>
|
||||
<errors>
|
||||
<approved hash="3,1,11522d222d2e115e"/>
|
||||
<approved hash="3,16,11522d222d2e115e"/>
|
||||
</errors>
|
||||
</board>
|
||||
</drawing>
|
||||
</eagle>
|
||||
707
eagle/DB19F adapter/db19f.sch
Normal file
707
eagle/DB19F adapter/db19f.sch
Normal file
@ -0,0 +1,707 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.6.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="yes"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
|
||||
<layer number="21" name="tPlace" color="16" fill="1" visible="no" active="no"/>
|
||||
<layer number="22" name="bPlace" color="14" fill="1" visible="no" active="no"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
|
||||
<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
|
||||
<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
|
||||
<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="no"/>
|
||||
<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
|
||||
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="no"/>
|
||||
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="48" name="Document" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="49" name="Reference" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="50" name="dxf" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="51" name="tDocu" color="6" fill="1" visible="no" active="no"/>
|
||||
<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="53" name="tGND_GNDA" color="7" fill="9" visible="no" active="no"/>
|
||||
<layer number="54" name="bGND_GNDA" color="1" fill="9" visible="no" active="no"/>
|
||||
<layer number="56" name="wert" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
|
||||
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="100" name="Muster" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="101" name="Patch_Top" color="12" fill="4" visible="yes" active="yes"/>
|
||||
<layer number="102" name="Vscore" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="103" name="fp3" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="104" name="Name" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="105" name="Beschreib" color="9" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="106" name="BGA-Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="107" name="BD-Top" color="5" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="108" name="fp8" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="109" name="fp9" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="110" name="fp0" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="116" name="Patch_BOT" color="9" fill="4" visible="yes" active="yes"/>
|
||||
<layer number="121" name="_tsilk" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="122" name="_bsilk" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="123" name="tTestmark" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="124" name="bTestmark" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="125" name="_tNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="131" name="tAdjust" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="132" name="bAdjust" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="144" name="Drill_legend" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="151" name="HeatSink" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="199" name="Contour" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="200" name="200bmp" color="1" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="201" name="201bmp" color="2" fill="1" visible="no" active="no"/>
|
||||
<layer number="202" name="202bmp" color="3" fill="1" visible="no" active="no"/>
|
||||
<layer number="203" name="203bmp" color="4" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="204" name="204bmp" color="5" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="205" name="205bmp" color="6" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="206" name="206bmp" color="7" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="207" name="207bmp" color="8" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="208" name="208bmp" color="9" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="209" name="209bmp" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="210" name="210bmp" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="211" name="211bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="212" name="212bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="213" name="213bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="214" name="214bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="215" name="215bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="216" name="216bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="217" name="217bmp" color="18" fill="1" visible="no" active="no"/>
|
||||
<layer number="218" name="218bmp" color="19" fill="1" visible="no" active="no"/>
|
||||
<layer number="219" name="219bmp" color="20" fill="1" visible="no" active="no"/>
|
||||
<layer number="220" name="220bmp" color="21" fill="1" visible="no" active="no"/>
|
||||
<layer number="221" name="221bmp" color="22" fill="1" visible="no" active="no"/>
|
||||
<layer number="222" name="222bmp" color="23" fill="1" visible="no" active="no"/>
|
||||
<layer number="223" name="223bmp" color="24" fill="1" visible="no" active="no"/>
|
||||
<layer number="224" name="224bmp" color="25" fill="1" visible="no" active="no"/>
|
||||
<layer number="250" name="Descript" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="251" name="SMDround" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="254" name="cooling" color="7" fill="1" visible="yes" active="yes"/>
|
||||
</layers>
|
||||
<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
|
||||
<libraries>
|
||||
<library name="big-mess-o-wires">
|
||||
<packages>
|
||||
<package name="DB19F-EDGE">
|
||||
<circle x="23.5204" y="2.54" radius="2.667" width="0" layer="42"/>
|
||||
<circle x="23.5204" y="2.54" radius="2.667" width="0" layer="43"/>
|
||||
<circle x="-23.5204" y="2.54" radius="2.667" width="0" layer="42"/>
|
||||
<circle x="-23.5204" y="2.54" radius="2.667" width="0" layer="43"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<wire x1="4.155" y1="2.54" x2="4.155" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="6.925" y1="2.54" x2="6.925" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="9.695" y1="2.54" x2="9.695" y2="5.31" width="1.27" layer="51"/>
|
||||
<wire x1="12.465" y1="2.54" x2="12.465" y2="5.31" width="1.27" layer="51"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<wire x1="-16.62" y1="8.08" x2="16.62" y2="8.08" width="0.127" layer="21"/>
|
||||
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|
||||
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|
||||
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|
||||
<wire x1="16.62" y1="8.08" x2="22.16" y2="8.08" width="0.127" layer="51"/>
|
||||
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|
||||
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|
||||
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|
||||
<smd name="9" x="-9.695" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="8" x="-6.925" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="7" x="-4.155" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="6" x="-1.385" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="5" x="1.385" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="4" x="4.155" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="3" x="6.925" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="2" x="9.695" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="1" x="12.465" y="5.54" dx="1.8" dy="5" layer="1"/>
|
||||
<smd name="19" x="-11.08" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="18" x="-8.31" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="17" x="-5.54" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="16" x="-2.77" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="15" x="0" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="14" x="2.77" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="13" x="5.54" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
<smd name="12" x="8.31" y="5.54" dx="1.8" dy="5" layer="16"/>
|
||||
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|
||||
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|
||||
<text x="-21.59" y="8.89" size="1.778" layer="27" ratio="10">>VALUE</text>
|
||||
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||||
<text x="-14.5525" y="3.925" size="1.6764" layer="21" rot="R90">10</text>
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||||
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||||
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|
||||
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|
||||
<package name="IDC20">
|
||||
<description><b>CONNECTOR</b><p>
|
||||
series 057 contact pc board low profile headers<p>
|
||||
straight</description>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<pad name="2" x="-11.43" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="3" x="-8.89" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="4" x="-8.89" y="1.27" drill="1" diameter="1.778"/>
|
||||
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|
||||
<pad name="6" x="-6.35" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="7" x="-3.81" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="8" x="-3.81" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="9" x="-1.27" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="10" x="-1.27" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="11" x="1.27" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="12" x="1.27" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="13" x="3.81" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="14" x="3.81" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="15" x="6.35" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="16" x="6.35" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="17" x="8.89" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="18" x="8.89" y="1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="19" x="11.43" y="-1.27" drill="1" diameter="1.778"/>
|
||||
<pad name="20" x="11.43" y="1.27" drill="1" diameter="1.778"/>
|
||||
<text x="-11.41" y="-6.88" size="1.778" layer="25">>NAME</text>
|
||||
<text x="-12.16" y="4.55" size="1.778" layer="27">>VALUE</text>
|
||||
</package>
|
||||
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|
||||
<symbols>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<wire x1="4.064" y1="14.5512" x2="4.064" y2="-12.0112" width="0.4064" layer="94"/>
|
||||
<wire x1="2.5226" y1="15.7918" x2="-3.0654" y2="14.5694" width="0.4064" layer="94"/>
|
||||
<wire x1="2.5226" y1="15.7919" x2="4.064" y2="14.5512" width="0.4064" layer="94" curve="-102.337599" cap="flat"/>
|
||||
<pin name="1" x="7.62" y="12.7" visible="pad" length="middle" direction="pas" rot="R180"/>
|
||||
<pin name="2" x="7.62" y="10.16" visible="pad" length="middle" direction="pas" rot="R180"/>
|
||||
<pin name="3" x="7.62" y="7.62" visible="pad" length="middle" direction="pas" rot="R180"/>
|
||||
<pin name="4" x="7.62" y="5.08" visible="pad" length="middle" direction="pas" rot="R180"/>
|
||||
<pin name="5" x="7.62" y="2.54" visible="pad" length="middle" direction="pas" rot="R180"/>
|
||||
<pin name="6" x="7.62" y="0" visible="pad" length="middle" direction="pas" rot="R180"/>
|
||||
<pin name="7" x="7.62" y="-2.54" visible="pad" length="middle" direction="pas" rot="R180"/>
|
||||
<pin name="8" x="7.62" y="-5.08" visible="pad" length="middle" direction="pas" rot="R180"/>
|
||||
<pin name="9" x="7.62" y="-7.62" visible="pad" length="middle" direction="pas" rot="R180"/>
|
||||
<pin name="10" x="7.62" y="-10.16" visible="pad" length="middle" direction="pas" rot="R180"/>
|
||||
<pin name="11" x="-7.62" y="12.7" visible="pad" length="middle" direction="pas"/>
|
||||
<pin name="12" x="-7.62" y="10.16" visible="pad" length="middle" direction="pas"/>
|
||||
<pin name="13" x="-7.62" y="7.62" visible="pad" length="middle" direction="pas"/>
|
||||
<pin name="14" x="-7.62" y="5.08" visible="pad" length="middle" direction="pas"/>
|
||||
<pin name="15" x="-7.62" y="2.54" visible="pad" length="middle" direction="pas"/>
|
||||
<pin name="16" x="-7.62" y="0" visible="pad" length="middle" direction="pas"/>
|
||||
<pin name="17" x="-7.62" y="-2.54" visible="pad" length="middle" direction="pas"/>
|
||||
<pin name="18" x="-7.62" y="-5.08" visible="pad" length="middle" direction="pas"/>
|
||||
<pin name="19" x="-7.62" y="-7.62" visible="pad" length="middle" direction="pas"/>
|
||||
<text x="-3.81" y="-15.875" size="1.778" layer="96">>VALUE</text>
|
||||
<text x="-3.81" y="16.51" size="1.778" layer="95">>NAME</text>
|
||||
</symbol>
|
||||
<symbol name="M10X2">
|
||||
<wire x1="-1.27" y1="5.08" x2="-2.54" y2="5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="-1.27" y1="7.62" x2="-2.54" y2="7.62" width="0.6096" layer="94"/>
|
||||
<wire x1="-1.27" y1="10.16" x2="-2.54" y2="10.16" width="0.6096" layer="94"/>
|
||||
<wire x1="-3.81" y1="12.7" x2="-3.81" y2="-15.24" width="0.4064" layer="94"/>
|
||||
<wire x1="-1.27" y1="0" x2="-2.54" y2="0" width="0.6096" layer="94"/>
|
||||
<wire x1="-1.27" y1="2.54" x2="-2.54" y2="2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="-1.27" y1="-2.54" x2="-2.54" y2="-2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="-1.27" y1="-5.08" x2="-2.54" y2="-5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="-1.27" y1="-7.62" x2="-2.54" y2="-7.62" width="0.6096" layer="94"/>
|
||||
<wire x1="-1.27" y1="-10.16" x2="-2.54" y2="-10.16" width="0.6096" layer="94"/>
|
||||
<wire x1="-1.27" y1="-12.7" x2="-2.54" y2="-12.7" width="0.6096" layer="94"/>
|
||||
<wire x1="3.81" y1="-15.24" x2="-3.81" y2="-15.24" width="0.4064" layer="94"/>
|
||||
<wire x1="1.27" y1="-7.62" x2="2.54" y2="-7.62" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="-10.16" x2="2.54" y2="-10.16" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="-12.7" x2="2.54" y2="-12.7" width="0.6096" layer="94"/>
|
||||
<wire x1="3.81" y1="-15.24" x2="3.81" y2="12.7" width="0.4064" layer="94"/>
|
||||
<wire x1="-3.81" y1="12.7" x2="3.81" y2="12.7" width="0.4064" layer="94"/>
|
||||
<wire x1="1.27" y1="-2.54" x2="2.54" y2="-2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="-5.08" x2="2.54" y2="-5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="0" x2="2.54" y2="0" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="2.54" x2="2.54" y2="2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="5.08" x2="2.54" y2="5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="7.62" x2="2.54" y2="7.62" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="10.16" x2="2.54" y2="10.16" width="0.6096" layer="94"/>
|
||||
<text x="-2.54" y="-17.78" size="1.778" layer="96">>VALUE</text>
|
||||
<text x="-2.54" y="13.97" size="1.778" layer="95">>NAME</text>
|
||||
<pin name="1" x="-7.62" y="10.16" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="2" x="7.62" y="10.16" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="3" x="-7.62" y="7.62" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="4" x="7.62" y="7.62" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="5" x="-7.62" y="5.08" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="6" x="7.62" y="5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="7" x="-7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="8" x="7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="9" x="-7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="10" x="7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="11" x="-7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="12" x="7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="13" x="-7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="14" x="7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="15" x="-7.62" y="-7.62" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="16" x="7.62" y="-7.62" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="17" x="-7.62" y="-10.16" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="18" x="7.62" y="-10.16" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="19" x="-7.62" y="-12.7" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="20" x="7.62" y="-12.7" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="DB19F">
|
||||
<gates>
|
||||
<gate name="1" symbol="DB19" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="DB19F-EDGE">
|
||||
<connects>
|
||||
<connect gate="1" pin="1" pad="1"/>
|
||||
<connect gate="1" pin="10" pad="10"/>
|
||||
<connect gate="1" pin="11" pad="11"/>
|
||||
<connect gate="1" pin="12" pad="12"/>
|
||||
<connect gate="1" pin="13" pad="13"/>
|
||||
<connect gate="1" pin="14" pad="14"/>
|
||||
<connect gate="1" pin="15" pad="15"/>
|
||||
<connect gate="1" pin="16" pad="16"/>
|
||||
<connect gate="1" pin="17" pad="17"/>
|
||||
<connect gate="1" pin="18" pad="18"/>
|
||||
<connect gate="1" pin="19" pad="19"/>
|
||||
<connect gate="1" pin="2" pad="2"/>
|
||||
<connect gate="1" pin="3" pad="3"/>
|
||||
<connect gate="1" pin="4" pad="4"/>
|
||||
<connect gate="1" pin="5" pad="5"/>
|
||||
<connect gate="1" pin="6" pad="6"/>
|
||||
<connect gate="1" pin="7" pad="7"/>
|
||||
<connect gate="1" pin="8" pad="8"/>
|
||||
<connect gate="1" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="IDC20">
|
||||
<gates>
|
||||
<gate name="G$1" symbol="M10X2" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="IDC20">
|
||||
<connects>
|
||||
<connect gate="G$1" pin="1" pad="1"/>
|
||||
<connect gate="G$1" pin="10" pad="10"/>
|
||||
<connect gate="G$1" pin="11" pad="11"/>
|
||||
<connect gate="G$1" pin="12" pad="12"/>
|
||||
<connect gate="G$1" pin="13" pad="13"/>
|
||||
<connect gate="G$1" pin="14" pad="14"/>
|
||||
<connect gate="G$1" pin="15" pad="15"/>
|
||||
<connect gate="G$1" pin="16" pad="16"/>
|
||||
<connect gate="G$1" pin="17" pad="17"/>
|
||||
<connect gate="G$1" pin="18" pad="18"/>
|
||||
<connect gate="G$1" pin="19" pad="19"/>
|
||||
<connect gate="G$1" pin="2" pad="2"/>
|
||||
<connect gate="G$1" pin="20" pad="20"/>
|
||||
<connect gate="G$1" pin="3" pad="3"/>
|
||||
<connect gate="G$1" pin="4" pad="4"/>
|
||||
<connect gate="G$1" pin="5" pad="5"/>
|
||||
<connect gate="G$1" pin="6" pad="6"/>
|
||||
<connect gate="G$1" pin="7" pad="7"/>
|
||||
<connect gate="G$1" pin="8" pad="8"/>
|
||||
<connect gate="G$1" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
<library name="supply1">
|
||||
<packages>
|
||||
</packages>
|
||||
<symbols>
|
||||
<symbol name="GND">
|
||||
<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
|
||||
<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text>
|
||||
<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
|
||||
</symbol>
|
||||
<symbol name="+5V">
|
||||
<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/>
|
||||
<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/>
|
||||
<text x="-2.54" y="-5.08" size="1.778" layer="96" rot="R90">>VALUE</text>
|
||||
<pin name="+5V" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="GND" prefix="GND">
|
||||
<description><b>SUPPLY SYMBOL</b></description>
|
||||
<gates>
|
||||
<gate name="1" symbol="GND" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="">
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="+5V" prefix="P+">
|
||||
<description><b>SUPPLY SYMBOL</b></description>
|
||||
<gates>
|
||||
<gate name="1" symbol="+5V" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="">
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</libraries>
|
||||
<attributes>
|
||||
</attributes>
|
||||
<variantdefs>
|
||||
</variantdefs>
|
||||
<classes>
|
||||
<class number="0" name="default" width="0" drill="0">
|
||||
</class>
|
||||
</classes>
|
||||
<parts>
|
||||
<part name="J3" library="big-mess-o-wires" deviceset="DB19F" device="" value="DB19"/>
|
||||
<part name="J2" library="big-mess-o-wires" deviceset="IDC20" device=""/>
|
||||
<part name="GND10" library="supply1" deviceset="GND" device=""/>
|
||||
<part name="P+6" library="supply1" deviceset="+5V" device=""/>
|
||||
<part name="GND11" library="supply1" deviceset="GND" device=""/>
|
||||
<part name="P+7" library="supply1" deviceset="+5V" device=""/>
|
||||
</parts>
|
||||
<sheets>
|
||||
<sheet>
|
||||
<plain>
|
||||
</plain>
|
||||
<instances>
|
||||
<instance part="J3" gate="1" x="-22.86" y="27.94" rot="MR0"/>
|
||||
<instance part="J2" gate="G$1" x="-22.86" y="68.58"/>
|
||||
<instance part="GND10" gate="1" x="-45.72" y="76.2"/>
|
||||
<instance part="P+6" gate="1" x="-45.72" y="71.12"/>
|
||||
<instance part="GND11" gate="1" x="-45.72" y="38.1"/>
|
||||
<instance part="P+7" gate="1" x="-45.72" y="33.02"/>
|
||||
</instances>
|
||||
<busses>
|
||||
</busses>
|
||||
<nets>
|
||||
<net name="GND" class="0">
|
||||
<segment>
|
||||
<wire x1="-30.48" y1="76.2" x2="-30.48" y2="78.74" width="0.1524" layer="91"/>
|
||||
<wire x1="-45.72" y1="78.74" x2="-30.48" y2="78.74" width="0.1524" layer="91"/>
|
||||
<junction x="-30.48" y="78.74"/>
|
||||
<pinref part="J2" gate="G$1" pin="1"/>
|
||||
<pinref part="J2" gate="G$1" pin="3"/>
|
||||
<pinref part="GND10" gate="1" pin="GND"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<wire x1="-45.72" y1="40.64" x2="-30.48" y2="40.64" width="0.1524" layer="91"/>
|
||||
<wire x1="-30.48" y1="40.64" x2="-30.48" y2="38.1" width="0.1524" layer="91"/>
|
||||
<junction x="-30.48" y="40.64"/>
|
||||
<pinref part="GND11" gate="1" pin="GND"/>
|
||||
<pinref part="J3" gate="1" pin="1"/>
|
||||
<pinref part="J3" gate="1" pin="2"/>
|
||||
<pinref part="J3" gate="1" pin="3"/>
|
||||
<wire x1="-30.48" y1="38.1" x2="-30.48" y2="35.56" width="0.1524" layer="91"/>
|
||||
<junction x="-30.48" y="38.1"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="+5V" class="0">
|
||||
<segment>
|
||||
<wire x1="-30.48" y1="66.04" x2="-45.72" y2="66.04" width="0.1524" layer="91"/>
|
||||
<wire x1="-45.72" y1="66.04" x2="-45.72" y2="68.58" width="0.1524" layer="91"/>
|
||||
<pinref part="J2" gate="G$1" pin="11"/>
|
||||
<pinref part="P+6" gate="1" pin="+5V"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<wire x1="-45.72" y1="30.48" x2="-45.72" y2="27.94" width="0.1524" layer="91"/>
|
||||
<wire x1="-30.48" y1="27.94" x2="-45.72" y2="27.94" width="0.1524" layer="91"/>
|
||||
<pinref part="P+7" gate="1" pin="+5V"/>
|
||||
<pinref part="J3" gate="1" pin="6"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="PH0" class="0">
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="78.74" x2="-2.54" y2="78.74" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="78.74" size="1.778" layer="95"/>
|
||||
<pinref part="J2" gate="G$1" pin="2"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="40.64" x2="-2.54" y2="40.64" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="40.64" size="1.778" layer="95"/>
|
||||
<pinref part="J3" gate="1" pin="11"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="PH1" class="0">
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="76.2" x2="-2.54" y2="76.2" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="76.2" size="1.778" layer="95"/>
|
||||
<pinref part="J2" gate="G$1" pin="4"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="38.1" x2="-2.54" y2="38.1" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="38.1" size="1.778" layer="95"/>
|
||||
<pinref part="J3" gate="1" pin="12"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="PH2" class="0">
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="73.66" x2="-2.54" y2="73.66" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="73.66" size="1.778" layer="95"/>
|
||||
<pinref part="J2" gate="G$1" pin="6"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="35.56" x2="-2.54" y2="35.56" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="35.56" size="1.778" layer="95"/>
|
||||
<pinref part="J3" gate="1" pin="13"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="PH3" class="0">
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="71.12" x2="-2.54" y2="71.12" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="71.12" size="1.778" layer="95"/>
|
||||
<pinref part="J2" gate="G$1" pin="8"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="33.02" x2="-2.54" y2="33.02" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="33.02" size="1.778" layer="95"/>
|
||||
<pinref part="J3" gate="1" pin="14"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="/WREQ" class="0">
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="68.58" x2="-2.54" y2="68.58" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="68.58" size="1.778" layer="95"/>
|
||||
<pinref part="J2" gate="G$1" pin="10"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="30.48" x2="-2.54" y2="30.48" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="30.48" size="1.778" layer="95"/>
|
||||
<pinref part="J3" gate="1" pin="15"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="SEL" class="0">
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="66.04" x2="-2.54" y2="66.04" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="66.04" size="1.778" layer="95"/>
|
||||
<pinref part="J2" gate="G$1" pin="12"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="27.94" x2="-2.54" y2="27.94" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="27.94" size="1.778" layer="95"/>
|
||||
<pinref part="J3" gate="1" pin="16"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="RD" class="0">
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="60.96" x2="-2.54" y2="60.96" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="60.96" size="1.778" layer="95"/>
|
||||
<pinref part="J2" gate="G$1" pin="16"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="22.86" x2="-2.54" y2="22.86" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="22.86" size="1.778" layer="95"/>
|
||||
<pinref part="J3" gate="1" pin="18"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="WR" class="0">
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="58.42" x2="-2.54" y2="58.42" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="58.42" size="1.778" layer="95"/>
|
||||
<pinref part="J2" gate="G$1" pin="18"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="20.32" x2="-2.54" y2="20.32" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="20.32" size="1.778" layer="95"/>
|
||||
<pinref part="J3" gate="1" pin="19"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="/ENBL1" class="0">
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="25.4" x2="-2.54" y2="25.4" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="25.4" size="1.778" layer="95"/>
|
||||
<pinref part="J3" gate="1" pin="17"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<wire x1="-15.24" y1="63.5" x2="-2.54" y2="63.5" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="63.5" size="1.778" layer="95"/>
|
||||
<pinref part="J2" gate="G$1" pin="14"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="SENSE" class="0">
|
||||
<segment>
|
||||
<pinref part="J3" gate="1" pin="10"/>
|
||||
<wire x1="-30.48" y1="17.78" x2="-40.64" y2="17.78" width="0.1524" layer="91"/>
|
||||
<label x="-40.64" y="17.78" size="1.778" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="J2" gate="G$1" pin="20"/>
|
||||
<wire x1="-15.24" y1="55.88" x2="-2.54" y2="55.88" width="0.1524" layer="91"/>
|
||||
<label x="-12.7" y="55.88" size="1.778" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="/ENBL2" class="0">
|
||||
<segment>
|
||||
<pinref part="J3" gate="1" pin="9"/>
|
||||
<wire x1="-40.64" y1="20.32" x2="-30.48" y2="20.32" width="0.1524" layer="91"/>
|
||||
<label x="-40.64" y="20.32" size="1.778" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="J2" gate="G$1" pin="5"/>
|
||||
<wire x1="-40.64" y1="73.66" x2="-30.48" y2="73.66" width="0.1524" layer="91"/>
|
||||
<label x="-40.64" y="73.66" size="1.778" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="/EN35" class="0">
|
||||
<segment>
|
||||
<pinref part="J2" gate="G$1" pin="7"/>
|
||||
<wire x1="-40.64" y1="71.12" x2="-30.48" y2="71.12" width="0.1524" layer="91"/>
|
||||
<label x="-40.64" y="71.12" size="1.778" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="J3" gate="1" pin="4"/>
|
||||
<wire x1="-40.64" y1="33.02" x2="-30.48" y2="33.02" width="0.1524" layer="91"/>
|
||||
<label x="-40.64" y="33.02" size="1.778" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="-12V" class="0">
|
||||
<segment>
|
||||
<pinref part="J2" gate="G$1" pin="9"/>
|
||||
<wire x1="-40.64" y1="68.58" x2="-30.48" y2="68.58" width="0.1524" layer="91"/>
|
||||
<label x="-40.64" y="68.58" size="1.778" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="J3" gate="1" pin="5"/>
|
||||
<wire x1="-40.64" y1="30.48" x2="-30.48" y2="30.48" width="0.1524" layer="91"/>
|
||||
<label x="-40.64" y="30.48" size="1.778" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="+12V" class="0">
|
||||
<segment>
|
||||
<pinref part="J2" gate="G$1" pin="13"/>
|
||||
<wire x1="-40.64" y1="63.5" x2="-30.48" y2="63.5" width="0.1524" layer="91"/>
|
||||
<label x="-40.64" y="63.5" size="1.778" layer="95"/>
|
||||
<pinref part="J2" gate="G$1" pin="15"/>
|
||||
<wire x1="-30.48" y1="63.5" x2="-30.48" y2="60.96" width="0.1524" layer="91"/>
|
||||
<junction x="-30.48" y="63.5"/>
|
||||
<pinref part="J2" gate="G$1" pin="17"/>
|
||||
<wire x1="-30.48" y1="60.96" x2="-30.48" y2="58.42" width="0.1524" layer="91"/>
|
||||
<junction x="-30.48" y="60.96"/>
|
||||
<pinref part="J2" gate="G$1" pin="19"/>
|
||||
<wire x1="-30.48" y1="58.42" x2="-30.48" y2="55.88" width="0.1524" layer="91"/>
|
||||
<junction x="-30.48" y="58.42"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="J3" gate="1" pin="7"/>
|
||||
<wire x1="-40.64" y1="25.4" x2="-30.48" y2="25.4" width="0.1524" layer="91"/>
|
||||
<label x="-40.64" y="25.4" size="1.778" layer="95"/>
|
||||
<pinref part="J3" gate="1" pin="8"/>
|
||||
<wire x1="-30.48" y1="25.4" x2="-30.48" y2="22.86" width="0.1524" layer="91"/>
|
||||
<junction x="-30.48" y="25.4"/>
|
||||
</segment>
|
||||
</net>
|
||||
</nets>
|
||||
</sheet>
|
||||
</sheets>
|
||||
</schematic>
|
||||
</drawing>
|
||||
</eagle>
|
||||
6152
eagle/FPGA disk controller/ELL-i-DigitalIC.lbr
Normal file
6152
eagle/FPGA disk controller/ELL-i-DigitalIC.lbr
Normal file
File diff suppressed because it is too large
Load Diff
4034
eagle/FPGA disk controller/bmowdisk.b#1
Normal file
4034
eagle/FPGA disk controller/bmowdisk.b#1
Normal file
File diff suppressed because it is too large
Load Diff
2923
eagle/FPGA disk controller/bmowdisk.brd
Normal file
2923
eagle/FPGA disk controller/bmowdisk.brd
Normal file
File diff suppressed because it is too large
Load Diff
4703
eagle/FPGA disk controller/bmowdisk.lbr
Normal file
4703
eagle/FPGA disk controller/bmowdisk.lbr
Normal file
File diff suppressed because it is too large
Load Diff
7427
eagle/FPGA disk controller/bmowdisk.sch
Normal file
7427
eagle/FPGA disk controller/bmowdisk.sch
Normal file
File diff suppressed because it is too large
Load Diff
7576
eagle/FPGA disk controller/bmowdisk.scr
Normal file
7576
eagle/FPGA disk controller/bmowdisk.scr
Normal file
File diff suppressed because it is too large
Load Diff
502
eagle/FPGA disk controller/bmowdisk1.lbr
Normal file
502
eagle/FPGA disk controller/bmowdisk1.lbr
Normal file
@ -0,0 +1,502 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.6.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
|
||||
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="93" name="Pins" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
|
||||
</layers>
|
||||
<library>
|
||||
<packages>
|
||||
<package name="TQFP100">
|
||||
<wire x1="-7" y1="6.25" x2="-6.25" y2="7" width="0.254" layer="21"/>
|
||||
<wire x1="-6.25" y1="7" x2="6.75" y2="7" width="0.254" layer="21"/>
|
||||
<wire x1="6.75" y1="7" x2="7" y2="6.75" width="0.254" layer="21"/>
|
||||
<wire x1="7" y1="6.75" x2="7" y2="-6.75" width="0.254" layer="21"/>
|
||||
<wire x1="7" y1="-6.75" x2="6.75" y2="-7" width="0.254" layer="21"/>
|
||||
<wire x1="6.75" y1="-7" x2="-6.75" y2="-7" width="0.254" layer="21"/>
|
||||
<wire x1="-6.75" y1="-7" x2="-7" y2="-6.75" width="0.254" layer="21"/>
|
||||
<wire x1="-7" y1="-6.75" x2="-7" y2="6.25" width="0.254" layer="21"/>
|
||||
<circle x="-6" y="6" radius="0.2499" width="0.254" layer="21"/>
|
||||
<smd name="1" x="-8" y="6" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="2" x="-8" y="5.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="3" x="-8" y="5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="4" x="-8" y="4.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="5" x="-8" y="4" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="6" x="-8" y="3.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="7" x="-8" y="3" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="8" x="-8" y="2.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="9" x="-8" y="2" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="10" x="-8" y="1.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="11" x="-8" y="1" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="12" x="-8" y="0.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="13" x="-8" y="0" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="14" x="-8" y="-0.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="15" x="-8" y="-1" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="16" x="-8" y="-1.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="17" x="-8" y="-2" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="18" x="-8" y="-2.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="19" x="-8" y="-3" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="20" x="-8" y="-3.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="21" x="-8" y="-4" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="22" x="-8" y="-4.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="23" x="-8" y="-5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="24" x="-8" y="-5.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="25" x="-8" y="-6" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="26" x="-6" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="27" x="-5.5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="28" x="-5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="29" x="-4.5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="30" x="-4" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="31" x="-3.5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="32" x="-3" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="33" x="-2.5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="34" x="-2" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="35" x="-1.5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="36" x="-1" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="37" x="-0.5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="38" x="0" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="39" x="0.5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="40" x="1" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="41" x="1.5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="42" x="2" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="43" x="2.5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="44" x="3" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="45" x="3.5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="46" x="4" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="47" x="4.5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="48" x="5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="49" x="5.5" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="50" x="6" y="-8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="51" x="8" y="-6" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="52" x="8" y="-5.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="53" x="8" y="-5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="54" x="8" y="-4.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="55" x="8" y="-4" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="56" x="8" y="-3.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="57" x="8" y="-3" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="58" x="8" y="-2.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="59" x="8" y="-2" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="60" x="8" y="-1.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="61" x="8" y="-1" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="62" x="8" y="-0.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="63" x="8" y="0" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="64" x="8" y="0.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="65" x="8" y="1" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="66" x="8" y="1.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="67" x="8" y="2" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="68" x="8" y="2.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="69" x="8" y="3" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="70" x="8" y="3.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="71" x="8" y="4" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="72" x="8" y="4.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="73" x="8" y="5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="74" x="8" y="5.5" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="75" x="8" y="6" dx="1.5" dy="0.35" layer="1"/>
|
||||
<smd name="76" x="6" y="8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="77" x="5.5" y="8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="78" x="5" y="8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="79" x="4.5" y="8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="80" x="4" y="8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="81" x="3.5" y="8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="82" x="3" y="8" dx="0.35" dy="1.5" layer="1"/>
|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
<smd name="92" x="-2" y="8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="93" x="-2.5" y="8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<smd name="94" x="-3" y="8" dx="0.35" dy="1.5" layer="1"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
<smd name="100" x="-6" y="8" dx="0.35" dy="1.5" layer="1"/>
|
||||
<text x="-6.395" y="9.2451" size="1.27" layer="25">>NAME</text>
|
||||
<text x="-3.1801" y="2.8001" size="1.27" layer="27">>VALUE</text>
|
||||
<text x="-2.81" y="-2.4801" size="0.8128" layer="51">TQFP 100</text>
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||||
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|
||||
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|
||||
<symbols>
|
||||
<symbol name="LCMXO2-640HC-4TG100C">
|
||||
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||||
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||||
<text x="-5.08" y="1.27" size="1.778" layer="95">>NAME</text>
|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<pin name="PR5C/PCLKT1_0" x="50.8" y="0" length="short" rot="R180"/>
|
||||
<pin name="PR5B" x="50.8" y="2.54" length="short" rot="R180"/>
|
||||
<pin name="PR5A" x="50.8" y="5.08" length="short" rot="R180"/>
|
||||
<pin name="PR3D" x="50.8" y="7.62" length="short" rot="R180"/>
|
||||
<pin name="PR3C" x="50.8" y="10.16" length="short" rot="R180"/>
|
||||
<pin name="PR3B" x="50.8" y="12.7" length="short" rot="R180"/>
|
||||
<pin name="PR3A" x="50.8" y="15.24" length="short" rot="R180"/>
|
||||
<pin name="PR2D" x="50.8" y="17.78" length="short" rot="R180"/>
|
||||
<pin name="PR2C" x="50.8" y="20.32" length="short" rot="R180"/>
|
||||
<pin name="GND@6" x="50.8" y="22.86" length="short" direction="pwr" rot="R180"/>
|
||||
<pin name="VCCIO1@2" x="50.8" y="25.4" length="short" direction="pwr" rot="R180"/>
|
||||
<pin name="PR2B" x="50.8" y="27.94" length="short" rot="R180"/>
|
||||
<pin name="PR2A" x="50.8" y="30.48" length="short" rot="R180"/>
|
||||
<pin name="NC@2" x="50.8" y="-5.08" length="short" direction="nc" rot="R180"/>
|
||||
<pin name="DONE/PT11D" x="27.94" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="INITN/PT11C" x="25.4" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="PT11A" x="22.86" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="GND@7" x="20.32" y="53.34" length="short" direction="pwr" rot="R270"/>
|
||||
<pin name="VCCIO0@1" x="17.78" y="53.34" length="short" direction="pwr" rot="R270"/>
|
||||
<pin name="PROGRAMN/PT10D" x="15.24" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="JTAGENB/PT10C" x="12.7" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="PT10B" x="10.16" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="PT10A" x="7.62" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="SDA/PCLKC0_0/PT9D" x="5.08" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="SCL/PCLKT0_0" x="2.54" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="PT9B/PCLKC0_1" x="0" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="PT9A/PCLKT0_1" x="-2.54" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="TMS/PT7D" x="-7.62" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="TCK/PT7C" x="-10.16" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="GND@8" x="-12.7" y="53.34" length="short" direction="pwr" rot="R270"/>
|
||||
<pin name="VCCIO0@2" x="-15.24" y="53.34" length="short" direction="pwr" rot="R270"/>
|
||||
<pin name="TDI/PT7B" x="-17.78" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="TDO/PT7A" x="-20.32" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="PT6D" x="-22.86" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="PT6C" x="-25.4" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="PT6B" x="-27.94" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="PT6A" x="-30.48" y="53.34" length="short" rot="R270"/>
|
||||
<pin name="VCC@2" x="-33.02" y="53.34" length="short" direction="pwr" rot="R270"/>
|
||||
<pin name="NC" x="-5.08" y="53.34" length="short" direction="nc" rot="R270"/>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="LCMXO2-640HC-4TG100C">
|
||||
<gates>
|
||||
<gate name="G$1" symbol="LCMXO2-640HC-4TG100C" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="TQFP100">
|
||||
<connects>
|
||||
<connect gate="G$1" pin="CSSPIN/PB4A" pad="27"/>
|
||||
<connect gate="G$1" pin="DONE/PT11D" pad="76"/>
|
||||
<connect gate="G$1" pin="GND@1" pad="6"/>
|
||||
<connect gate="G$1" pin="GND@2" pad="22"/>
|
||||
<connect gate="G$1" pin="GND@3" pad="33"/>
|
||||
<connect gate="G$1" pin="GND@4" pad="44"/>
|
||||
<connect gate="G$1" pin="GND@5" pad="56"/>
|
||||
<connect gate="G$1" pin="GND@6" pad="72"/>
|
||||
<connect gate="G$1" pin="GND@7" pad="79"/>
|
||||
<connect gate="G$1" pin="GND@8" pad="92"/>
|
||||
<connect gate="G$1" pin="INITN/PT11C" pad="77"/>
|
||||
<connect gate="G$1" pin="JTAGENB/PT10C" pad="82"/>
|
||||
<connect gate="G$1" pin="MCLK/CCLK/PB6A" pad="31"/>
|
||||
<connect gate="G$1" pin="NC" pad="89"/>
|
||||
<connect gate="G$1" pin="NC@1" pad="11"/>
|
||||
<connect gate="G$1" pin="NC@2" pad="61"/>
|
||||
<connect gate="G$1" pin="PB10A" pad="36"/>
|
||||
<connect gate="G$1" pin="PB10B" pad="37"/>
|
||||
<connect gate="G$1" pin="PB10C/PCLKT2_1" pad="38"/>
|
||||
<connect gate="G$1" pin="PB10D/PCLKC2_0" pad="39"/>
|
||||
<connect gate="G$1" pin="PB12A" pad="40"/>
|
||||
<connect gate="G$1" pin="PB12B" pad="41"/>
|
||||
<connect gate="G$1" pin="PB12C" pad="42"/>
|
||||
<connect gate="G$1" pin="PB12D" pad="43"/>
|
||||
<connect gate="G$1" pin="PB14A" pad="45"/>
|
||||
<connect gate="G$1" pin="PB14B" pad="47"/>
|
||||
<connect gate="G$1" pin="PB4B" pad="28"/>
|
||||
<connect gate="G$1" pin="PB4C" pad="29"/>
|
||||
<connect gate="G$1" pin="PB4D" pad="30"/>
|
||||
<connect gate="G$1" pin="PB6C/PCLKT2_0" pad="34"/>
|
||||
<connect gate="G$1" pin="PB6D/PCLKC2_0" pad="35"/>
|
||||
<connect gate="G$1" pin="PL2A" pad="1"/>
|
||||
<connect gate="G$1" pin="PL2B" pad="2"/>
|
||||
<connect gate="G$1" pin="PL2C/PCLKT3_2" pad="3"/>
|
||||
<connect gate="G$1" pin="PL2D/PCLKC3_2" pad="4"/>
|
||||
<connect gate="G$1" pin="PL3A" pad="7"/>
|
||||
<connect gate="G$1" pin="PL3B" pad="8"/>
|
||||
<connect gate="G$1" pin="PL3C" pad="9"/>
|
||||
<connect gate="G$1" pin="PL3D" pad="10"/>
|
||||
<connect gate="G$1" pin="PL5A/PCLKT3_1" pad="12"/>
|
||||
<connect gate="G$1" pin="PL5B/PCLKC3_1" pad="13"/>
|
||||
<connect gate="G$1" pin="PL5C" pad="14"/>
|
||||
<connect gate="G$1" pin="PL5D" pad="15"/>
|
||||
<connect gate="G$1" pin="PL6A" pad="16"/>
|
||||
<connect gate="G$1" pin="PL6B" pad="17"/>
|
||||
<connect gate="G$1" pin="PL6C" pad="18"/>
|
||||
<connect gate="G$1" pin="PL6D" pad="19"/>
|
||||
<connect gate="G$1" pin="PL7A/PCLKT3_0" pad="20"/>
|
||||
<connect gate="G$1" pin="PL7B/PCLKC3_0" pad="21"/>
|
||||
<connect gate="G$1" pin="PL7C" pad="24"/>
|
||||
<connect gate="G$1" pin="PL7D" pad="25"/>
|
||||
<connect gate="G$1" pin="PR2A" pad="75"/>
|
||||
<connect gate="G$1" pin="PR2B" pad="74"/>
|
||||
<connect gate="G$1" pin="PR2C" pad="71"/>
|
||||
<connect gate="G$1" pin="PR2D" pad="70"/>
|
||||
<connect gate="G$1" pin="PR3A" pad="69"/>
|
||||
<connect gate="G$1" pin="PR3B" pad="68"/>
|
||||
<connect gate="G$1" pin="PR3C" pad="67"/>
|
||||
<connect gate="G$1" pin="PR3D" pad="66"/>
|
||||
<connect gate="G$1" pin="PR5A" pad="65"/>
|
||||
<connect gate="G$1" pin="PR5B" pad="64"/>
|
||||
<connect gate="G$1" pin="PR5C/PCLKT1_0" pad="63"/>
|
||||
<connect gate="G$1" pin="PR5D/PCLKC1_0" pad="62"/>
|
||||
<connect gate="G$1" pin="PR6A" pad="60"/>
|
||||
<connect gate="G$1" pin="PR6B" pad="59"/>
|
||||
<connect gate="G$1" pin="PR6C" pad="58"/>
|
||||
<connect gate="G$1" pin="PR6D" pad="57"/>
|
||||
<connect gate="G$1" pin="PR7A" pad="54"/>
|
||||
<connect gate="G$1" pin="PR7B" pad="53"/>
|
||||
<connect gate="G$1" pin="PR7C" pad="52"/>
|
||||
<connect gate="G$1" pin="PR7D" pad="51"/>
|
||||
<connect gate="G$1" pin="PROGRAMN/PT10D" pad="81"/>
|
||||
<connect gate="G$1" pin="PT10A" pad="84"/>
|
||||
<connect gate="G$1" pin="PT10B" pad="83"/>
|
||||
<connect gate="G$1" pin="PT11A" pad="78"/>
|
||||
<connect gate="G$1" pin="PT6A" pad="99"/>
|
||||
<connect gate="G$1" pin="PT6B" pad="98"/>
|
||||
<connect gate="G$1" pin="PT6C" pad="97"/>
|
||||
<connect gate="G$1" pin="PT6D" pad="96"/>
|
||||
<connect gate="G$1" pin="PT9A/PCLKT0_1" pad="88"/>
|
||||
<connect gate="G$1" pin="PT9B/PCLKC0_1" pad="87"/>
|
||||
<connect gate="G$1" pin="SCL/PCLKT0_0" pad="86"/>
|
||||
<connect gate="G$1" pin="SDA/PCLKC0_0/PT9D" pad="85"/>
|
||||
<connect gate="G$1" pin="SI/SISPI/PB14D" pad="49"/>
|
||||
<connect gate="G$1" pin="SN/PB14C" pad="48"/>
|
||||
<connect gate="G$1" pin="SO/SPISO/PB6B" pad="32"/>
|
||||
<connect gate="G$1" pin="TCK/PT7C" pad="91"/>
|
||||
<connect gate="G$1" pin="TDI/PT7B" pad="94"/>
|
||||
<connect gate="G$1" pin="TDO/PT7A" pad="95"/>
|
||||
<connect gate="G$1" pin="TMS/PT7D" pad="90"/>
|
||||
<connect gate="G$1" pin="VCC@1" pad="50"/>
|
||||
<connect gate="G$1" pin="VCC@2" pad="100"/>
|
||||
<connect gate="G$1" pin="VCCIO0@1" pad="80"/>
|
||||
<connect gate="G$1" pin="VCCIO0@2" pad="93"/>
|
||||
<connect gate="G$1" pin="VCCIO1@1" pad="55"/>
|
||||
<connect gate="G$1" pin="VCCIO1@2" pad="73"/>
|
||||
<connect gate="G$1" pin="VCCIO2@1" pad="26"/>
|
||||
<connect gate="G$1" pin="VCCIO2@2" pad="46"/>
|
||||
<connect gate="G$1" pin="VCCIO3@1" pad="5"/>
|
||||
<connect gate="G$1" pin="VCCIO3@2" pad="23"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
</eagle>
|
||||
BIN
eagle/FPGA disk controller/bom.xlsx
Normal file
BIN
eagle/FPGA disk controller/bom.xlsx
Normal file
Binary file not shown.
913
eagle/FPGA disk controller/con-apple2.lbr
Normal file
913
eagle/FPGA disk controller/con-apple2.lbr
Normal file
@ -0,0 +1,913 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.6.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.05" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
|
||||
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="51" name="tDocu" color="10" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
|
||||
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
|
||||
</layers>
|
||||
<library>
|
||||
<description><b>Apple ][ Expansion Card Templates</b>
|
||||
<br />
|
||||
Dimensions are taken from the Apple IIgs Tech Note #28</description>
|
||||
<packages>
|
||||
<package name="A2-50PIN-SL1-3">
|
||||
<description><B>Apple ][ Peripheral Card</B>
|
||||
<br />
|
||||
Standard 50-pin edge connector for Apple ][ systems
|
||||
<br />
|
||||
Dimensions for slot #1 to #3
|
||||
<br />
|
||||
Dimensions taken from Tech Note #28</description>
|
||||
<wire x1="-9.652" y1="0.508" x2="-10.287" y2="-0.127" width="0.2032" layer="21"/>
|
||||
<wire x1="-10.287" y1="-0.127" x2="-74.803" y2="-0.127" width="0.2032" layer="21"/>
|
||||
<wire x1="-74.803" y1="-0.127" x2="-75.438" y2="0.508" width="0.2032" layer="21"/>
|
||||
<wire x1="-9.652" y1="7.747" x2="-9.652" y2="0.508" width="0.2032" layer="21"/>
|
||||
<wire x1="-0.127" y1="7.747" x2="-9.652" y2="7.747" width="0.2032" layer="21"/>
|
||||
<wire x1="-75.438" y1="7.747" x2="-177.927" y2="7.747" width="0.2032" layer="21"/>
|
||||
<wire x1="-75.438" y1="7.747" x2="-75.438" y2="0.508" width="0.2032" layer="21"/>
|
||||
<wire x1="-82.5246" y1="-0.127" x2="-87.5284" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="-0.127" x2="-86.8426" y2="1.4986" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="-0.127" x2="-88.4174" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-88.2142" y1="1.4986" x2="-87.5284" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="7.747" x2="-88.2396" y2="6.2484" width="0" layer="48"/>
|
||||
<wire x1="-88.2396" y1="6.2484" x2="-86.8172" y2="6.2484" width="0" layer="48"/>
|
||||
<wire x1="-86.8172" y1="6.2484" x2="-87.5284" y2="7.747" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="7.747" x2="-87.5284" y2="5.5372" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="-0.127" x2="-87.5284" y2="1.9558" width="0" layer="48"/>
|
||||
<wire x1="-86.8426" y1="1.4986" x2="-88.2142" y2="1.4986" width="0" layer="48"/>
|
||||
<wire x1="-75.438" y1="-1.143" x2="-75.438" y2="-8.382" width="0" layer="48"/>
|
||||
<wire x1="-9.652" y1="-0.2286" x2="-9.652" y2="-8.128" width="0" layer="48"/>
|
||||
<wire x1="-9.6774" y1="-6.985" x2="-75.4126" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-75.4126" y1="-6.985" x2="-73.025" y2="-5.715" width="0" layer="48"/>
|
||||
<wire x1="-73.025" y1="-5.715" x2="-73.025" y2="-8.255" width="0" layer="48"/>
|
||||
<wire x1="-73.025" y1="-8.255" x2="-75.4126" y2="-6.985" width="0" layer="48"/>
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<rectangle x1="-41.402" y1="1.778" x2="-39.878" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-41.402" y1="1.778" x2="-39.878" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-38.862" y1="1.778" x2="-37.338" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-38.862" y1="1.778" x2="-37.338" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-36.322" y1="1.778" x2="-34.798" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-36.322" y1="1.778" x2="-34.798" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-33.782" y1="1.778" x2="-32.258" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-33.782" y1="1.778" x2="-32.258" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-31.242" y1="1.778" x2="-29.718" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-31.242" y1="1.778" x2="-29.718" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-28.702" y1="1.778" x2="-27.178" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-28.702" y1="1.778" x2="-27.178" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-26.162" y1="1.778" x2="-24.638" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-26.162" y1="1.778" x2="-24.638" y2="8.382" layer="33"/>
|
||||
<wire x1="-177.927" y1="77.597" x2="-177.927" y2="7.747" width="0.2032" layer="21"/>
|
||||
</package>
|
||||
<package name="A2-50PIN-SL4-7">
|
||||
<description><B>Apple ][ Peripheral Card</B>
|
||||
<br />
|
||||
Standard 50-pin edge connector for Apple ][ systems
|
||||
<br />
|
||||
Dimensions for slot #4 to #7
|
||||
<br />
|
||||
Dimensions taken from Tech Note #28</description>
|
||||
<wire x1="-9.652" y1="0.508" x2="-10.287" y2="-0.127" width="0.2032" layer="21"/>
|
||||
<wire x1="-10.287" y1="-0.127" x2="-74.803" y2="-0.127" width="0.2032" layer="21"/>
|
||||
<wire x1="-74.803" y1="-0.127" x2="-75.438" y2="0.508" width="0.2032" layer="21"/>
|
||||
<wire x1="-9.652" y1="7.747" x2="-9.652" y2="0.508" width="0.2032" layer="21"/>
|
||||
<wire x1="-0.127" y1="7.747" x2="-9.652" y2="7.747" width="0.2032" layer="21"/>
|
||||
<wire x1="-75.438" y1="7.747" x2="-254.127" y2="7.747" width="0.2032" layer="21"/>
|
||||
<wire x1="-75.438" y1="7.747" x2="-75.438" y2="0.508" width="0.2032" layer="21"/>
|
||||
<wire x1="-82.5246" y1="-0.127" x2="-87.5284" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="-0.127" x2="-86.8426" y2="1.4986" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="-0.127" x2="-88.4174" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-88.2142" y1="1.4986" x2="-87.5284" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="7.747" x2="-88.2396" y2="6.2484" width="0" layer="48"/>
|
||||
<wire x1="-88.2396" y1="6.2484" x2="-86.8172" y2="6.2484" width="0" layer="48"/>
|
||||
<wire x1="-86.8172" y1="6.2484" x2="-87.5284" y2="7.747" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="7.747" x2="-87.5284" y2="5.5372" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="-0.127" x2="-87.5284" y2="1.9558" width="0" layer="48"/>
|
||||
<wire x1="-86.8426" y1="1.4986" x2="-88.2142" y2="1.4986" width="0" layer="48"/>
|
||||
<wire x1="-75.438" y1="-1.143" x2="-75.438" y2="-8.382" width="0" layer="48"/>
|
||||
<wire x1="-9.652" y1="-0.2286" x2="-9.652" y2="-8.128" width="0" layer="48"/>
|
||||
<wire x1="-9.6774" y1="-6.985" x2="-75.4126" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-75.4126" y1="-6.985" x2="-73.025" y2="-5.715" width="0" layer="48"/>
|
||||
<wire x1="-73.025" y1="-5.715" x2="-73.025" y2="-8.255" width="0" layer="48"/>
|
||||
<wire x1="-73.025" y1="-8.255" x2="-75.4126" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-9.6774" y1="-6.985" x2="-12.065" y2="-5.715" width="0" layer="48"/>
|
||||
<wire x1="-12.065" y1="-5.715" x2="-12.065" y2="-8.255" width="0" layer="48"/>
|
||||
<wire x1="-12.065" y1="-8.255" x2="-9.6774" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-0.127" y1="77.597" x2="-196.977" y2="77.597" width="0.2032" layer="21"/>
|
||||
<wire x1="-75.438" y1="7.747" x2="-75.438" y2="5.715" width="0.1524" layer="21"/>
|
||||
<wire x1="-0.127" y1="77.597" x2="-0.127" y2="7.778" width="0.2032" layer="21"/>
|
||||
<smd name="26" x="-12.065" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="27" x="-14.605" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="28" x="-17.145" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="29" x="-19.685" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="30" x="-22.225" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="31" x="-24.765" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="32" x="-27.305" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="33" x="-29.845" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="34" x="-32.385" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="35" x="-34.925" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="36" x="-37.465" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="37" x="-40.005" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="38" x="-42.545" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="39" x="-45.085" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="40" x="-47.625" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="41" x="-50.165" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="42" x="-52.705" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="43" x="-55.245" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="44" x="-57.785" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="45" x="-60.325" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="46" x="-62.865" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="47" x="-65.405" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="48" x="-67.945" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="49" x="-70.485" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="50" x="-73.025" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="25" x="-12.065" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="24" x="-14.605" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="23" x="-17.145" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="22" x="-19.685" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="21" x="-22.225" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="20" x="-24.765" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="19" x="-27.305" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="18" x="-29.845" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="17" x="-32.385" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="16" x="-34.925" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="15" x="-37.465" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="14" x="-40.005" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="13" x="-42.545" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="12" x="-45.085" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="11" x="-47.625" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="10" x="-50.165" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="09" x="-52.705" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="08" x="-55.245" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="07" x="-57.785" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="06" x="-60.325" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="05" x="-62.865" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="04" x="-65.405" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="03" x="-67.945" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="02" x="-70.485" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="01" x="-73.025" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<text x="-5.715" y="3.175" size="1.778" layer="25">>NAME</text>
|
||||
<text x="-94.5134" y="2.9718" size="1.778" layer="48">7,87 mm</text>
|
||||
<text x="-40.8432" y="-9.2964" size="1.778" layer="48">74.93 mm
|
||||
2.950"</text>
|
||||
<text x="-5.715" y="-0.635" size="1.778" layer="27">>VALUE</text>
|
||||
<wire x1="-196.977" y1="77.597" x2="-254.127" y2="63.627" width="0.2032" layer="21"/>
|
||||
<wire x1="-254.127" y1="63.627" x2="-254.127" y2="7.747" width="0.2032" layer="21"/>
|
||||
</package>
|
||||
<package name="A2GS-44PIN-MEM">
|
||||
<description><B>Apple IIgs Memory Expansion Card</B>
|
||||
<br />
|
||||
The maximum PCB dimensions for an Apple IIgs Memory Expansion Card
|
||||
<br />
|
||||
Dimensions taken from Tech Note #28</description>
|
||||
<wire x1="-253.238" y1="0.508" x2="-252.603" y2="-0.127" width="0.2032" layer="22"/>
|
||||
<wire x1="-252.603" y1="-0.127" x2="-195.707" y2="-0.127" width="0.2032" layer="22"/>
|
||||
<wire x1="-195.707" y1="-0.127" x2="-195.072" y2="0.508" width="0.2032" layer="22"/>
|
||||
<wire x1="-253.238" y1="7.747" x2="-253.238" y2="0.508" width="0.2032" layer="22"/>
|
||||
<wire x1="-439.293" y1="7.747" x2="-347.472" y2="7.747" width="0.2032" layer="22"/>
|
||||
<wire x1="-347.472" y1="7.747" x2="-347.472" y2="-8.255" width="0.2032" layer="22"/>
|
||||
<wire x1="-347.472" y1="-8.255" x2="-337.312" y2="-8.255" width="0.2032" layer="22"/>
|
||||
<wire x1="-337.312" y1="-8.255" x2="-337.312" y2="7.747" width="0.2032" layer="22"/>
|
||||
<wire x1="-337.312" y1="7.747" x2="-253.238" y2="7.747" width="0.2032" layer="22"/>
|
||||
<wire x1="-195.072" y1="7.747" x2="-185.293" y2="7.747" width="0.2032" layer="22"/>
|
||||
<wire x1="-195.072" y1="7.747" x2="-195.072" y2="0.508" width="0.2032" layer="22"/>
|
||||
<wire x1="-191.7954" y1="-0.127" x2="-186.7916" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-186.7916" y1="-0.127" x2="-187.4774" y2="1.4986" width="0" layer="48"/>
|
||||
<wire x1="-186.7916" y1="-0.127" x2="-185.9026" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-186.1058" y1="1.4986" x2="-186.7916" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-186.7916" y1="7.747" x2="-186.0804" y2="6.2484" width="0" layer="48"/>
|
||||
<wire x1="-186.0804" y1="6.2484" x2="-187.5028" y2="6.2484" width="0" layer="48"/>
|
||||
<wire x1="-187.5028" y1="6.2484" x2="-186.7916" y2="7.747" width="0" layer="48"/>
|
||||
<wire x1="-186.7916" y1="7.747" x2="-186.7916" y2="5.5372" width="0" layer="48"/>
|
||||
<wire x1="-186.7916" y1="-0.127" x2="-186.7916" y2="1.9558" width="0" layer="48"/>
|
||||
<wire x1="-187.4774" y1="1.4986" x2="-186.1058" y2="1.4986" width="0" layer="48"/>
|
||||
<wire x1="-195.072" y1="-1.143" x2="-195.072" y2="-8.382" width="0" layer="48"/>
|
||||
<wire x1="-253.238" y1="-0.2286" x2="-253.238" y2="-8.128" width="0" layer="48"/>
|
||||
<wire x1="-253.2126" y1="-6.985" x2="-195.0974" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-195.0974" y1="-6.985" x2="-197.485" y2="-5.715" width="0" layer="48"/>
|
||||
<wire x1="-197.485" y1="-5.715" x2="-197.485" y2="-8.255" width="0" layer="48"/>
|
||||
<wire x1="-197.485" y1="-8.255" x2="-195.0974" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-253.2126" y1="-6.985" x2="-250.825" y2="-5.715" width="0" layer="48"/>
|
||||
<wire x1="-250.825" y1="-5.715" x2="-250.825" y2="-8.255" width="0" layer="48"/>
|
||||
<wire x1="-250.825" y1="-8.255" x2="-253.2126" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-439.293" y1="77.597" x2="-242.443" y2="77.597" width="0.2032" layer="22"/>
|
||||
<wire x1="-195.072" y1="7.747" x2="-195.072" y2="5.715" width="0.1524" layer="22"/>
|
||||
<wire x1="-439.293" y1="77.597" x2="-439.293" y2="7.778" width="0.2032" layer="22"/>
|
||||
<smd name="23" x="-250.825" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="24" x="-248.285" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="25" x="-245.745" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="26" x="-243.205" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="27" x="-240.665" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="28" x="-238.125" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="29" x="-235.585" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="30" x="-233.045" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="31" x="-230.505" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="32" x="-227.965" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="33" x="-225.425" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="34" x="-222.885" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="35" x="-220.345" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="36" x="-217.805" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="37" x="-215.265" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="38" x="-212.725" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="39" x="-210.185" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="40" x="-207.645" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="41" x="-205.105" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="42" x="-202.565" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="43" x="-200.025" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="44" x="-197.485" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="22" x="-250.825" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="21" x="-248.285" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="20" x="-245.745" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="19" x="-243.205" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="18" x="-240.665" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="17" x="-238.125" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="16" x="-235.585" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="15" x="-233.045" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="14" x="-230.505" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="13" x="-227.965" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="12" x="-225.425" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="11" x="-222.885" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="10" x="-220.345" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="09" x="-217.805" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="08" x="-215.265" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="07" x="-212.725" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="06" x="-210.185" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="05" x="-207.645" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="04" x="-205.105" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="03" x="-202.565" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="02" x="-200.025" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="01" x="-197.485" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<text x="-280.035" y="4.445" size="1.778" layer="25">>NAME</text>
|
||||
<text x="-182.3466" y="2.9718" size="1.778" layer="48">7,87 mm</text>
|
||||
<text x="-229.6668" y="-9.2964" size="1.778" layer="48">57,658 mm
|
||||
2.270"</text>
|
||||
<text x="-280.035" y="0.635" size="1.778" layer="27">>VALUE</text>
|
||||
<wire x1="-242.443" y1="77.597" x2="-185.293" y2="63.627" width="0.2032" layer="22"/>
|
||||
<wire x1="-185.293" y1="63.627" x2="-185.293" y2="7.747" width="0.2032" layer="22"/>
|
||||
</package>
|
||||
<package name="A2-50PIN-MINI">
|
||||
<wire x1="90.808" y1="-33.782" x2="90.173" y2="-34.417" width="0" layer="51"/>
|
||||
<wire x1="90.173" y1="-34.417" x2="25.657" y2="-34.417" width="0" layer="51"/>
|
||||
<wire x1="25.657" y1="-34.417" x2="25.022" y2="-33.782" width="0" layer="51"/>
|
||||
<wire x1="90.808" y1="-26.543" x2="90.808" y2="-33.782" width="0" layer="51"/>
|
||||
<wire x1="93" y1="-26.543" x2="90.808" y2="-26.543" width="0" layer="51"/>
|
||||
<wire x1="25.022" y1="-26.543" x2="-7" y2="-26.543" width="0" layer="51"/>
|
||||
<wire x1="25.022" y1="-26.543" x2="25.022" y2="-33.782" width="0" layer="51"/>
|
||||
<wire x1="17.9354" y1="-34.417" x2="12.9316" y2="-34.417" width="0" layer="48"/>
|
||||
<wire x1="12.9316" y1="-34.417" x2="13.6174" y2="-32.7914" width="0" layer="48"/>
|
||||
<wire x1="12.9316" y1="-34.417" x2="12.0426" y2="-34.417" width="0" layer="48"/>
|
||||
<wire x1="12.2458" y1="-32.7914" x2="12.9316" y2="-34.417" width="0" layer="48"/>
|
||||
<wire x1="12.9316" y1="-26.543" x2="12.2204" y2="-28.0416" width="0" layer="48"/>
|
||||
<wire x1="12.2204" y1="-28.0416" x2="13.6428" y2="-28.0416" width="0" layer="48"/>
|
||||
<wire x1="13.6428" y1="-28.0416" x2="12.9316" y2="-26.543" width="0" layer="48"/>
|
||||
<wire x1="12.9316" y1="-26.543" x2="12.9316" y2="-28.7528" width="0" layer="48"/>
|
||||
<wire x1="12.9316" y1="-34.417" x2="12.9316" y2="-32.3342" width="0" layer="48"/>
|
||||
<wire x1="13.6174" y1="-32.7914" x2="12.2458" y2="-32.7914" width="0" layer="48"/>
|
||||
<wire x1="25.022" y1="-35.433" x2="25.022" y2="-42.672" width="0" layer="48"/>
|
||||
<wire x1="90.808" y1="-34.5186" x2="90.808" y2="-42.418" width="0" layer="48"/>
|
||||
<wire x1="90.7826" y1="-41.275" x2="25.0474" y2="-41.275" width="0" layer="48"/>
|
||||
<wire x1="25.0474" y1="-41.275" x2="27.435" y2="-40.005" width="0" layer="48"/>
|
||||
<wire x1="27.435" y1="-40.005" x2="27.435" y2="-42.545" width="0" layer="48"/>
|
||||
<wire x1="27.435" y1="-42.545" x2="25.0474" y2="-41.275" width="0" layer="48"/>
|
||||
<wire x1="90.7826" y1="-41.275" x2="88.395" y2="-40.005" width="0" layer="48"/>
|
||||
<wire x1="88.395" y1="-40.005" x2="88.395" y2="-42.545" width="0" layer="48"/>
|
||||
<wire x1="88.395" y1="-42.545" x2="90.7826" y2="-41.275" width="0" layer="48"/>
|
||||
<wire x1="93" y1="43.307" x2="-7" y2="43.307" width="0" layer="51"/>
|
||||
<wire x1="25.022" y1="-26.543" x2="25.022" y2="-28.575" width="0" layer="51"/>
|
||||
<wire x1="93" y1="43.307" x2="93" y2="-26.512" width="0" layer="51"/>
|
||||
<smd name="26" x="88.395" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="27" x="85.855" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="28" x="83.315" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="29" x="80.775" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="30" x="78.235" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="31" x="75.695" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="32" x="73.155" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="33" x="70.615" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="34" x="68.075" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="35" x="65.535" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="36" x="62.995" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="37" x="60.455" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="38" x="57.915" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="39" x="55.375" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="40" x="52.835" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="41" x="50.295" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="42" x="47.755" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="43" x="45.215" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="44" x="42.675" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="45" x="40.135" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="46" x="37.595" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="47" x="35.055" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="48" x="32.515" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="49" x="29.975" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="50" x="27.435" y="-29.845" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="25" x="88.395" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="24" x="85.855" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="23" x="83.315" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="22" x="80.775" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="21" x="78.235" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="20" x="75.695" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="19" x="73.155" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="18" x="70.615" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="17" x="68.075" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="16" x="65.535" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="15" x="62.995" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="14" x="60.455" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="13" x="57.915" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="12" x="55.375" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="11" x="52.835" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="10" x="50.295" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="09" x="47.755" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="08" x="45.215" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="07" x="42.675" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="06" x="40.135" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="05" x="37.595" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="04" x="35.055" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="03" x="32.515" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="02" x="29.975" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="01" x="27.435" y="-29.845" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<text x="5.9466" y="-31.3182" size="1.778" layer="48">7,87 mm</text>
|
||||
<text x="59.6168" y="-43.5864" size="1.778" layer="48">74.93 mm
|
||||
2.950"</text>
|
||||
<wire x1="-7" y1="43.307" x2="-7" y2="-26.543" width="0" layer="51"/>
|
||||
</package>
|
||||
</packages>
|
||||
<symbols>
|
||||
<symbol name="ATPIN">
|
||||
<wire x1="0" y1="0.635" x2="3.175" y2="0.635" width="0.3048" layer="94"/>
|
||||
<wire x1="3.175" y1="0.635" x2="3.175" y2="-0.635" width="0.3048" layer="94"/>
|
||||
<wire x1="3.175" y1="-0.635" x2="0" y2="-0.635" width="0.3048" layer="94"/>
|
||||
<wire x1="0" y1="-0.635" x2="0" y2="0.635" width="0.3048" layer="94"/>
|
||||
<text x="4.445" y="-0.9652" size="1.778" layer="95">>NAME</text>
|
||||
<pin name="P" x="-2.54" y="0" visible="pad" length="short" swaplevel="1"/>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="A2-50PIN" prefix="ST" uservalue="yes">
|
||||
<description><B>Apple ][ Peripheral Card Connector</B>
|
||||
<br />
|
||||
This is the, default, 50-pin connector for slot #1 to #7
|
||||
<br />
|
||||
Pins are laid out as seen from the top of the slot</description>
|
||||
<gates>
|
||||
<gate name="_+12V" symbol="ATPIN" x="-5.08" y="-38.1" addlevel="always"/>
|
||||
<gate name="_D0" symbol="ATPIN" x="-5.08" y="-35.56" addlevel="always"/>
|
||||
<gate name="_D1" symbol="ATPIN" x="-5.08" y="-33.02" addlevel="always"/>
|
||||
<gate name="_D2" symbol="ATPIN" x="-5.08" y="-30.48" addlevel="always"/>
|
||||
<gate name="_D3" symbol="ATPIN" x="-5.08" y="-27.94" addlevel="always"/>
|
||||
<gate name="_D4" symbol="ATPIN" x="-5.08" y="-25.4" addlevel="always"/>
|
||||
<gate name="_D5" symbol="ATPIN" x="-5.08" y="-22.86" addlevel="always"/>
|
||||
<gate name="_D6" symbol="ATPIN" x="-5.08" y="-20.32" addlevel="always"/>
|
||||
<gate name="_D7" symbol="ATPIN" x="-5.08" y="-17.78" addlevel="always"/>
|
||||
<gate name="_DEVSELECT\" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
|
||||
<gate name="_00" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
|
||||
<gate name="_USER1" symbol="ATPIN" x="-5.08" y="-10.16" addlevel="always"/>
|
||||
<gate name="_01" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
|
||||
<gate name="_Q3" symbol="ATPIN" x="-5.08" y="-5.08" addlevel="always"/>
|
||||
<gate name="_7M" symbol="ATPIN" x="-5.08" y="-2.54" addlevel="always"/>
|
||||
<gate name="_NC@2" symbol="ATPIN" x="-5.08" y="0" addlevel="always"/>
|
||||
<gate name="_-5V" symbol="ATPIN" x="-5.08" y="2.54" addlevel="always"/>
|
||||
<gate name="_-12V" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
|
||||
<gate name="_INH\" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
|
||||
<gate name="_RES\" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
|
||||
<gate name="_IRQ\" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
|
||||
<gate name="_NMI\" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
|
||||
<gate name="_INT_IN" symbol="ATPIN" x="-5.08" y="17.78" addlevel="always"/>
|
||||
<gate name="_DMA_IN" symbol="ATPIN" x="-5.08" y="20.32" addlevel="always"/>
|
||||
<gate name="_GND" symbol="ATPIN" x="-5.08" y="22.86" addlevel="always"/>
|
||||
<gate name="_IOSELECT\" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
|
||||
<gate name="_A00" symbol="ATPIN" x="27.94" y="-35.56" addlevel="always"/>
|
||||
<gate name="_A01" symbol="ATPIN" x="27.94" y="-33.02" addlevel="always"/>
|
||||
<gate name="_A02" symbol="ATPIN" x="27.94" y="-30.48" addlevel="always"/>
|
||||
<gate name="_A03" symbol="ATPIN" x="27.94" y="-27.94" addlevel="always"/>
|
||||
<gate name="_A04" symbol="ATPIN" x="27.94" y="-25.4" addlevel="always"/>
|
||||
<gate name="_A05" symbol="ATPIN" x="27.94" y="-22.86" addlevel="always"/>
|
||||
<gate name="_A06" symbol="ATPIN" x="27.94" y="-20.32" addlevel="always"/>
|
||||
<gate name="_A07" symbol="ATPIN" x="27.94" y="-17.78" addlevel="always"/>
|
||||
<gate name="_A08" symbol="ATPIN" x="27.94" y="-15.24" addlevel="always"/>
|
||||
<gate name="_A09" symbol="ATPIN" x="27.94" y="-12.7" addlevel="always"/>
|
||||
<gate name="_A10" symbol="ATPIN" x="27.94" y="-10.16" addlevel="always"/>
|
||||
<gate name="_A11" symbol="ATPIN" x="27.94" y="-7.62" addlevel="always"/>
|
||||
<gate name="_A12" symbol="ATPIN" x="27.94" y="-5.08" addlevel="always"/>
|
||||
<gate name="_A13" symbol="ATPIN" x="27.94" y="-2.54" addlevel="always"/>
|
||||
<gate name="_A14" symbol="ATPIN" x="27.94" y="0" addlevel="always"/>
|
||||
<gate name="_A15" symbol="ATPIN" x="27.94" y="2.54" addlevel="always"/>
|
||||
<gate name="_RW" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
|
||||
<gate name="_NC@1" symbol="ATPIN" x="27.94" y="7.62" addlevel="always"/>
|
||||
<gate name="_IOSTR\" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
|
||||
<gate name="_RDY" symbol="ATPIN" x="27.94" y="12.7" addlevel="always"/>
|
||||
<gate name="_DMA\" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
|
||||
<gate name="_INT_OUT" symbol="ATPIN" x="27.94" y="17.78" addlevel="always"/>
|
||||
<gate name="_DMA_OUT" symbol="ATPIN" x="27.94" y="20.32" addlevel="always"/>
|
||||
<gate name="_+5V" symbol="ATPIN" x="27.94" y="22.86" addlevel="always"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="SLOT1-3" package="A2-50PIN-SL1-3">
|
||||
<connects>
|
||||
<connect gate="_+12V" pin="P" pad="50"/>
|
||||
<connect gate="_+5V" pin="P" pad="25"/>
|
||||
<connect gate="_-12V" pin="P" pad="33"/>
|
||||
<connect gate="_-5V" pin="P" pad="34"/>
|
||||
<connect gate="_00" pin="P" pad="40"/>
|
||||
<connect gate="_01" pin="P" pad="38"/>
|
||||
<connect gate="_7M" pin="P" pad="36"/>
|
||||
<connect gate="_A00" pin="P" pad="02"/>
|
||||
<connect gate="_A01" pin="P" pad="03"/>
|
||||
<connect gate="_A02" pin="P" pad="04"/>
|
||||
<connect gate="_A03" pin="P" pad="05"/>
|
||||
<connect gate="_A04" pin="P" pad="06"/>
|
||||
<connect gate="_A05" pin="P" pad="07"/>
|
||||
<connect gate="_A06" pin="P" pad="08"/>
|
||||
<connect gate="_A07" pin="P" pad="09"/>
|
||||
<connect gate="_A08" pin="P" pad="10"/>
|
||||
<connect gate="_A09" pin="P" pad="11"/>
|
||||
<connect gate="_A10" pin="P" pad="12"/>
|
||||
<connect gate="_A11" pin="P" pad="13"/>
|
||||
<connect gate="_A12" pin="P" pad="14"/>
|
||||
<connect gate="_A13" pin="P" pad="15"/>
|
||||
<connect gate="_A14" pin="P" pad="16"/>
|
||||
<connect gate="_A15" pin="P" pad="17"/>
|
||||
<connect gate="_D0" pin="P" pad="49"/>
|
||||
<connect gate="_D1" pin="P" pad="48"/>
|
||||
<connect gate="_D2" pin="P" pad="47"/>
|
||||
<connect gate="_D3" pin="P" pad="46"/>
|
||||
<connect gate="_D4" pin="P" pad="45"/>
|
||||
<connect gate="_D5" pin="P" pad="44"/>
|
||||
<connect gate="_D6" pin="P" pad="43"/>
|
||||
<connect gate="_D7" pin="P" pad="42"/>
|
||||
<connect gate="_DEVSELECT\" pin="P" pad="41"/>
|
||||
<connect gate="_DMA\" pin="P" pad="22"/>
|
||||
<connect gate="_DMA_IN" pin="P" pad="27"/>
|
||||
<connect gate="_DMA_OUT" pin="P" pad="24"/>
|
||||
<connect gate="_GND" pin="P" pad="26"/>
|
||||
<connect gate="_INH\" pin="P" pad="32"/>
|
||||
<connect gate="_INT_IN" pin="P" pad="28"/>
|
||||
<connect gate="_INT_OUT" pin="P" pad="23"/>
|
||||
<connect gate="_IOSELECT\" pin="P" pad="01"/>
|
||||
<connect gate="_IOSTR\" pin="P" pad="20"/>
|
||||
<connect gate="_IRQ\" pin="P" pad="30"/>
|
||||
<connect gate="_NC@1" pin="P" pad="19"/>
|
||||
<connect gate="_NC@2" pin="P" pad="35"/>
|
||||
<connect gate="_NMI\" pin="P" pad="29"/>
|
||||
<connect gate="_Q3" pin="P" pad="37"/>
|
||||
<connect gate="_RDY" pin="P" pad="21"/>
|
||||
<connect gate="_RES\" pin="P" pad="31"/>
|
||||
<connect gate="_RW" pin="P" pad="18"/>
|
||||
<connect gate="_USER1" pin="P" pad="39"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="SLOT4-7" package="A2-50PIN-SL4-7">
|
||||
<connects>
|
||||
<connect gate="_+12V" pin="P" pad="50"/>
|
||||
<connect gate="_+5V" pin="P" pad="25"/>
|
||||
<connect gate="_-12V" pin="P" pad="33"/>
|
||||
<connect gate="_-5V" pin="P" pad="34"/>
|
||||
<connect gate="_00" pin="P" pad="40"/>
|
||||
<connect gate="_01" pin="P" pad="38"/>
|
||||
<connect gate="_7M" pin="P" pad="36"/>
|
||||
<connect gate="_A00" pin="P" pad="02"/>
|
||||
<connect gate="_A01" pin="P" pad="03"/>
|
||||
<connect gate="_A02" pin="P" pad="04"/>
|
||||
<connect gate="_A03" pin="P" pad="05"/>
|
||||
<connect gate="_A04" pin="P" pad="06"/>
|
||||
<connect gate="_A05" pin="P" pad="07"/>
|
||||
<connect gate="_A06" pin="P" pad="08"/>
|
||||
<connect gate="_A07" pin="P" pad="09"/>
|
||||
<connect gate="_A08" pin="P" pad="10"/>
|
||||
<connect gate="_A09" pin="P" pad="11"/>
|
||||
<connect gate="_A10" pin="P" pad="12"/>
|
||||
<connect gate="_A11" pin="P" pad="13"/>
|
||||
<connect gate="_A12" pin="P" pad="14"/>
|
||||
<connect gate="_A13" pin="P" pad="15"/>
|
||||
<connect gate="_A14" pin="P" pad="16"/>
|
||||
<connect gate="_A15" pin="P" pad="17"/>
|
||||
<connect gate="_D0" pin="P" pad="49"/>
|
||||
<connect gate="_D1" pin="P" pad="48"/>
|
||||
<connect gate="_D2" pin="P" pad="47"/>
|
||||
<connect gate="_D3" pin="P" pad="46"/>
|
||||
<connect gate="_D4" pin="P" pad="45"/>
|
||||
<connect gate="_D5" pin="P" pad="44"/>
|
||||
<connect gate="_D6" pin="P" pad="43"/>
|
||||
<connect gate="_D7" pin="P" pad="42"/>
|
||||
<connect gate="_DEVSELECT\" pin="P" pad="41"/>
|
||||
<connect gate="_DMA\" pin="P" pad="22"/>
|
||||
<connect gate="_DMA_IN" pin="P" pad="27"/>
|
||||
<connect gate="_DMA_OUT" pin="P" pad="24"/>
|
||||
<connect gate="_GND" pin="P" pad="26"/>
|
||||
<connect gate="_INH\" pin="P" pad="32"/>
|
||||
<connect gate="_INT_IN" pin="P" pad="28"/>
|
||||
<connect gate="_INT_OUT" pin="P" pad="23"/>
|
||||
<connect gate="_IOSELECT\" pin="P" pad="01"/>
|
||||
<connect gate="_IOSTR\" pin="P" pad="20"/>
|
||||
<connect gate="_IRQ\" pin="P" pad="30"/>
|
||||
<connect gate="_NC@1" pin="P" pad="19"/>
|
||||
<connect gate="_NC@2" pin="P" pad="35"/>
|
||||
<connect gate="_NMI\" pin="P" pad="29"/>
|
||||
<connect gate="_Q3" pin="P" pad="37"/>
|
||||
<connect gate="_RDY" pin="P" pad="21"/>
|
||||
<connect gate="_RES\" pin="P" pad="31"/>
|
||||
<connect gate="_RW" pin="P" pad="18"/>
|
||||
<connect gate="_USER1" pin="P" pad="39"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="MINI" package="A2-50PIN-MINI">
|
||||
<connects>
|
||||
<connect gate="_+12V" pin="P" pad="50"/>
|
||||
<connect gate="_+5V" pin="P" pad="25"/>
|
||||
<connect gate="_-12V" pin="P" pad="33"/>
|
||||
<connect gate="_-5V" pin="P" pad="34"/>
|
||||
<connect gate="_00" pin="P" pad="40"/>
|
||||
<connect gate="_01" pin="P" pad="38"/>
|
||||
<connect gate="_7M" pin="P" pad="36"/>
|
||||
<connect gate="_A00" pin="P" pad="02"/>
|
||||
<connect gate="_A01" pin="P" pad="03"/>
|
||||
<connect gate="_A02" pin="P" pad="04"/>
|
||||
<connect gate="_A03" pin="P" pad="05"/>
|
||||
<connect gate="_A04" pin="P" pad="06"/>
|
||||
<connect gate="_A05" pin="P" pad="07"/>
|
||||
<connect gate="_A06" pin="P" pad="08"/>
|
||||
<connect gate="_A07" pin="P" pad="09"/>
|
||||
<connect gate="_A08" pin="P" pad="10"/>
|
||||
<connect gate="_A09" pin="P" pad="11"/>
|
||||
<connect gate="_A10" pin="P" pad="12"/>
|
||||
<connect gate="_A11" pin="P" pad="13"/>
|
||||
<connect gate="_A12" pin="P" pad="14"/>
|
||||
<connect gate="_A13" pin="P" pad="15"/>
|
||||
<connect gate="_A14" pin="P" pad="16"/>
|
||||
<connect gate="_A15" pin="P" pad="17"/>
|
||||
<connect gate="_D0" pin="P" pad="49"/>
|
||||
<connect gate="_D1" pin="P" pad="48"/>
|
||||
<connect gate="_D2" pin="P" pad="47"/>
|
||||
<connect gate="_D3" pin="P" pad="46"/>
|
||||
<connect gate="_D4" pin="P" pad="45"/>
|
||||
<connect gate="_D5" pin="P" pad="44"/>
|
||||
<connect gate="_D6" pin="P" pad="43"/>
|
||||
<connect gate="_D7" pin="P" pad="42"/>
|
||||
<connect gate="_DEVSELECT\" pin="P" pad="41"/>
|
||||
<connect gate="_DMA\" pin="P" pad="22"/>
|
||||
<connect gate="_DMA_IN" pin="P" pad="27"/>
|
||||
<connect gate="_DMA_OUT" pin="P" pad="24"/>
|
||||
<connect gate="_GND" pin="P" pad="26"/>
|
||||
<connect gate="_INH\" pin="P" pad="32"/>
|
||||
<connect gate="_INT_IN" pin="P" pad="28"/>
|
||||
<connect gate="_INT_OUT" pin="P" pad="23"/>
|
||||
<connect gate="_IOSELECT\" pin="P" pad="01"/>
|
||||
<connect gate="_IOSTR\" pin="P" pad="20"/>
|
||||
<connect gate="_IRQ\" pin="P" pad="30"/>
|
||||
<connect gate="_NC@1" pin="P" pad="19"/>
|
||||
<connect gate="_NC@2" pin="P" pad="35"/>
|
||||
<connect gate="_NMI\" pin="P" pad="29"/>
|
||||
<connect gate="_Q3" pin="P" pad="37"/>
|
||||
<connect gate="_RDY" pin="P" pad="21"/>
|
||||
<connect gate="_RES\" pin="P" pad="31"/>
|
||||
<connect gate="_RW" pin="P" pad="18"/>
|
||||
<connect gate="_USER1" pin="P" pad="39"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="A2GSRAM-44PIN" prefix="ST" uservalue="yes">
|
||||
<description><B>Apple IIgs Memory Expansion Slot 44-pin</B>
|
||||
<br />
|
||||
This is the 44-pin board dimensions for an Apple IIgs Memory Expansion Card
|
||||
<br />
|
||||
Pins are laid out as seen from the top of the slot. Pin 1 is towards the front of the case/keyboard</description>
|
||||
<gates>
|
||||
<gate name="_GND@5" symbol="ATPIN" x="-5.08" y="-38.1" addlevel="always"/>
|
||||
<gate name="_+5V@5" symbol="ATPIN" x="-5.08" y="-35.56" addlevel="always"/>
|
||||
<gate name="_A15" symbol="ATPIN" x="-5.08" y="-33.02" addlevel="always"/>
|
||||
<gate name="_A14" symbol="ATPIN" x="-5.08" y="-30.48" addlevel="always"/>
|
||||
<gate name="_A13" symbol="ATPIN" x="-5.08" y="-27.94" addlevel="always"/>
|
||||
<gate name="_A12" symbol="ATPIN" x="-5.08" y="-25.4" addlevel="always"/>
|
||||
<gate name="_A11" symbol="ATPIN" x="-5.08" y="-22.86" addlevel="always"/>
|
||||
<gate name="_A10" symbol="ATPIN" x="-5.08" y="-20.32" addlevel="always"/>
|
||||
<gate name="_D1" symbol="ATPIN" x="-5.08" y="-17.78" addlevel="always"/>
|
||||
<gate name="_CRAS\" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
|
||||
<gate name="_GND@4" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
|
||||
<gate name="_D3" symbol="ATPIN" x="-5.08" y="-10.16" addlevel="always"/>
|
||||
<gate name="_ABORT" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
|
||||
<gate name="_02" symbol="ATPIN" x="-5.08" y="-5.08" addlevel="always"/>
|
||||
<gate name="_D5" symbol="ATPIN" x="-5.08" y="-2.54" addlevel="always"/>
|
||||
<gate name="_D4" symbol="ATPIN" x="-5.08" y="0" addlevel="always"/>
|
||||
<gate name="_D6" symbol="ATPIN" x="-5.08" y="2.54" addlevel="always"/>
|
||||
<gate name="_MSIZE" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
|
||||
<gate name="_CSEL\" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
|
||||
<gate name="_GND@3" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
|
||||
<gate name="_+5V@4" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
|
||||
<gate name="_D0" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
|
||||
<gate name="_GND@1" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
|
||||
<gate name="_+5V@1" symbol="ATPIN" x="27.94" y="-35.56" addlevel="always"/>
|
||||
<gate name="_FRA9" symbol="ATPIN" x="27.94" y="-33.02" addlevel="always"/>
|
||||
<gate name="_FRA8" symbol="ATPIN" x="27.94" y="-30.48" addlevel="always"/>
|
||||
<gate name="_D2" symbol="ATPIN" x="27.94" y="-27.94" addlevel="always"/>
|
||||
<gate name="_FRA6" symbol="ATPIN" x="27.94" y="-25.4" addlevel="always"/>
|
||||
<gate name="_FRA3" symbol="ATPIN" x="27.94" y="-22.86" addlevel="always"/>
|
||||
<gate name="_FRA4" symbol="ATPIN" x="27.94" y="-20.32" addlevel="always"/>
|
||||
<gate name="_FRA5" symbol="ATPIN" x="27.94" y="-17.78" addlevel="always"/>
|
||||
<gate name="_FRA7" symbol="ATPIN" x="27.94" y="-15.24" addlevel="always"/>
|
||||
<gate name="_+5V@2" symbol="ATPIN" x="27.94" y="-12.7" addlevel="always"/>
|
||||
<gate name="_FR/W" symbol="ATPIN" x="27.94" y="-10.16" addlevel="always"/>
|
||||
<gate name="_FRA0" symbol="ATPIN" x="27.94" y="-7.62" addlevel="always"/>
|
||||
<gate name="_FRA2" symbol="ATPIN" x="27.94" y="-5.08" addlevel="always"/>
|
||||
<gate name="_FRA1" symbol="ATPIN" x="27.94" y="-2.54" addlevel="always"/>
|
||||
<gate name="_D7" symbol="ATPIN" x="27.94" y="0" addlevel="always"/>
|
||||
<gate name="_CCAS\" symbol="ATPIN" x="27.94" y="2.54" addlevel="always"/>
|
||||
<gate name="_CROW0" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
|
||||
<gate name="_CROW1" symbol="ATPIN" x="27.94" y="7.62" addlevel="always"/>
|
||||
<gate name="_CROMSEL\" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
|
||||
<gate name="_+5V@3" symbol="ATPIN" x="27.94" y="12.7" addlevel="always"/>
|
||||
<gate name="_GND@2" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="IIGS-RAM" package="A2GS-44PIN-MEM">
|
||||
<connects>
|
||||
<connect gate="_+5V@1" pin="P" pad="02"/>
|
||||
<connect gate="_+5V@2" pin="P" pad="11"/>
|
||||
<connect gate="_+5V@3" pin="P" pad="21"/>
|
||||
<connect gate="_+5V@4" pin="P" pad="24"/>
|
||||
<connect gate="_+5V@5" pin="P" pad="43"/>
|
||||
<connect gate="_02" pin="P" pad="31"/>
|
||||
<connect gate="_A10" pin="P" pad="37"/>
|
||||
<connect gate="_A11" pin="P" pad="38"/>
|
||||
<connect gate="_A12" pin="P" pad="39"/>
|
||||
<connect gate="_A13" pin="P" pad="40"/>
|
||||
<connect gate="_A14" pin="P" pad="41"/>
|
||||
<connect gate="_A15" pin="P" pad="42"/>
|
||||
<connect gate="_ABORT" pin="P" pad="32"/>
|
||||
<connect gate="_CCAS\" pin="P" pad="17"/>
|
||||
<connect gate="_CRAS\" pin="P" pad="35"/>
|
||||
<connect gate="_CROMSEL\" pin="P" pad="20"/>
|
||||
<connect gate="_CROW0" pin="P" pad="18"/>
|
||||
<connect gate="_CROW1" pin="P" pad="19"/>
|
||||
<connect gate="_CSEL\" pin="P" pad="26"/>
|
||||
<connect gate="_D0" pin="P" pad="25"/>
|
||||
<connect gate="_D1" pin="P" pad="36"/>
|
||||
<connect gate="_D2" pin="P" pad="05"/>
|
||||
<connect gate="_D3" pin="P" pad="33"/>
|
||||
<connect gate="_D4" pin="P" pad="29"/>
|
||||
<connect gate="_D5" pin="P" pad="30"/>
|
||||
<connect gate="_D6" pin="P" pad="28"/>
|
||||
<connect gate="_D7" pin="P" pad="16"/>
|
||||
<connect gate="_FR/W" pin="P" pad="12"/>
|
||||
<connect gate="_FRA0" pin="P" pad="13"/>
|
||||
<connect gate="_FRA1" pin="P" pad="15"/>
|
||||
<connect gate="_FRA2" pin="P" pad="14"/>
|
||||
<connect gate="_FRA3" pin="P" pad="07"/>
|
||||
<connect gate="_FRA4" pin="P" pad="08"/>
|
||||
<connect gate="_FRA5" pin="P" pad="09"/>
|
||||
<connect gate="_FRA6" pin="P" pad="06"/>
|
||||
<connect gate="_FRA7" pin="P" pad="10"/>
|
||||
<connect gate="_FRA8" pin="P" pad="04"/>
|
||||
<connect gate="_FRA9" pin="P" pad="03"/>
|
||||
<connect gate="_GND@1" pin="P" pad="01"/>
|
||||
<connect gate="_GND@2" pin="P" pad="22"/>
|
||||
<connect gate="_GND@3" pin="P" pad="23"/>
|
||||
<connect gate="_GND@4" pin="P" pad="34"/>
|
||||
<connect gate="_GND@5" pin="P" pad="44"/>
|
||||
<connect gate="_MSIZE" pin="P" pad="27"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
<compatibility>
|
||||
<note version="6.3" minversion="6.2.2" severity="warning">
|
||||
Since Version 6.2.2 text objects can contain more than one line,
|
||||
which will not be processed correctly with this version.
|
||||
</note>
|
||||
</compatibility>
|
||||
</eagle>
|
||||
469
eagle/FPGA disk controller/eagle.epf
Normal file
469
eagle/FPGA disk controller/eagle.epf
Normal file
@ -0,0 +1,469 @@
|
||||
[Eagle]
|
||||
Version="06 06 00"
|
||||
Platform="Windows"
|
||||
Serial="62191E841E-LSR-WLM-1EL"
|
||||
Globals="Globals"
|
||||
Desktop="Desktop"
|
||||
|
||||
[Globals]
|
||||
AutoSaveProject=1
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/19inch.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/40xx.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/41xx.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/45xx.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/74ac-logic.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/74ttl-din.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/74xx-eu.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/74xx-little-de.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/74xx-little-us.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/74xx-us.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/751xx.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/advanced-test-technologies.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/agilent-technologies.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/allegro.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/altera-cyclone-II.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/altera-cyclone-III.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/altera-stratix-iv.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/altera.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/am29-memory.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/amd-mach.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/amd.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/amis.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/analog-devices.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/aplus.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/ase.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/atmel.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/austriamicrosystems.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/avago.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/axis.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/battery.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/belton-engineering.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/burr-brown.lbr"
|
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UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/omnivision.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/on-semiconductor.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/opto-honeywell-3000.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/opto-honeywell-4000.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/opto-honeywell.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/opto-micro-linear.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/opto-trans-siemens.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/opto-transmittter-hp.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/opto-vishay.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/optocoupler.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/pal.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/philips-semiconductors.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/photo-elements.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/piher.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/pinhead.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/plcc-socket.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/pld-intel.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/plxtech.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/pot-vitrohm.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/pot-xicor.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/pot.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/ptc-ntc.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/quantum-research-group.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/rcl.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/recom-international.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/rectifier.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/ref-packages-longpad.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/ref-packages.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/relay.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/renesas.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/resistor-bourns.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/resistor-dil.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/resistor-net.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/resistor-power.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/resistor-ruf.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/resistor-shunt.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/resistor-sil.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/resistor.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/rf-micro-devices.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/rf-solutions.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/rohm.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/roundsolutions.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/semicon-smd-ipc.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/sensor-comus-group.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/sensor-heraeus.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/sensor-infratec.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/sharp.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/silabs.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/sim-technology.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/sipex.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/smd-ipc.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/smd-special.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/solomon-systech.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/solpad.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/speaker.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/special-drill.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/special.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/st-microelectronics.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/supertex.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/supply1.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/supply2.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/switch-alps.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/switch-coto.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/switch-dil.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/switch-misc.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/switch-omron.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/switch-raychem.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/switch-reed.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/switch.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/telcom.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/telecontrolli.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/telefunken.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/testpad.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/texas-sn55-sn75.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/texas.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/toshiba.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/traco-electronic.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/trafo-bei.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/trafo-hammondmfg.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/trafo-siemens.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/trafo-xicon.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/trafo.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/transformer-pulse.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/transistor-fet.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/transistor-neu-to92.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/transistor-npn.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/transistor-pnp.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/transistor-power.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/transistor-small-signal.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/transistor.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/triac.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/trimble.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/tripas.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/u-blox.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/uln-udn.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/v-reg-micrel.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/v-reg.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/varistor.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/wafer-scale-psd.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/wirepad.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/xicor.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/xilinx-virtex-v5.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/xilinx-xc18v.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/xilinx-xc9.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/xilinx-xcv.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/zetex.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/zilog.lbr"
|
||||
UsedLibrary="bmowdisk.lbr"
|
||||
UsedLibrary="bmowdisk1.lbr"
|
||||
UsedLibrary="con-apple2.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/floppyemu model C/floppyemu-c.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/Model D/model-d.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/Model D/borkedlabs-connectors.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/Model D/borkedlabs-micros.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/Model D/borkedlabs-powerics.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/Model D/borkedlabs-transceivers.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/Model D/SparkFun-IC-Microcontroller.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/Model D/SparkFun-IC-Power.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/Model D/controller-micro_atmel_jd.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/Model D/SparkFun-Aesthetics.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/Model D/SparkFun-PowerSymbols.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/Model D/borkedlabs-passives.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/apple IIc adapter/apple-iic-adapter.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/floppyemu/eagle/Model D/Sparkfun SAMD21_Dev_Breakout/Hardware/sparkfun-samd21-pro-breakout.lbr"
|
||||
UsedLibrary="C:/Users/chamberlin/Documents/Wearable/wearable.lbr"
|
||||
|
||||
[Win_1]
|
||||
Type="Control Panel"
|
||||
Loc="116 397 715 796"
|
||||
State=0
|
||||
Number=0
|
||||
|
||||
[Win_2]
|
||||
Type="Board Editor"
|
||||
Loc="652 321 1251 720"
|
||||
State=2
|
||||
Number=2
|
||||
File="C:/Users/chamberlin/Documents/floppyemu/eagle/floppyemu 1.5/floppyemu-1.5.brd"
|
||||
View="6.54114 18.6889 40.0355 39.7414"
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||||
WireWidths=" 0 0.254 0.3048 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0.4064"
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||||
PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
|
||||
PadDrills=" 0.5 0.6 0.7 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.8"
|
||||
ViaDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
|
||||
ViaDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6"
|
||||
HoleDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6"
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||||
TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778"
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PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
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||||
MiterRadiuss=" 0.254 0.3175 0.635 1.27 2.54 1 2 2.5 5 7.5 10 0"
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||||
DimensionWidths=" 0 0.127 0.254 0.1 0.26 0.13"
|
||||
DimensionExtWidths=" 0.127 0.254 0.1 0.13 0.26 0"
|
||||
DimensionExtLengths=" 1.27 2.54 1 2 3 0"
|
||||
DimensionExtOffsets=" 1.27 2.54 1 2 3 0"
|
||||
SmdSizes=" 0.3048 0.1524 0.4064 0.2032 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635"
|
||||
WireBend=0
|
||||
WireBendSet=0
|
||||
WireCap=1
|
||||
MiterStyle=0
|
||||
PadShape=0
|
||||
ViaShape=0
|
||||
PolygonPour=0
|
||||
PolygonRank=1
|
||||
PolygonThermals=1
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||||
PolygonOrphans=0
|
||||
TextRatio=8
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||||
DimensionUnit=1
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||||
DimensionPrecision=2
|
||||
DimensionShowUnit=0
|
||||
PinDirection=3
|
||||
PinFunction=0
|
||||
PinLength=2
|
||||
PinVisible=3
|
||||
SwapLevel=0
|
||||
ArcDirection=0
|
||||
AddLevel=2
|
||||
PadsSameType=0
|
||||
Layer=16
|
||||
|
||||
[Win_3]
|
||||
Type="Schematic Editor"
|
||||
Loc="652 321 1251 720"
|
||||
State=1
|
||||
Number=1
|
||||
File="C:/Users/chamberlin/Documents/floppyemu/eagle/floppyemu 1.5/floppyemu-1.5.sch"
|
||||
View="-107.888 -36.8209 227.882 130.005"
|
||||
WireWidths=" 0 0.3048 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0.4064 0.1524"
|
||||
PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
|
||||
PadDrills=" 0.5 0.6 0.7 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.8"
|
||||
ViaDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
|
||||
ViaDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6"
|
||||
HoleDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6"
|
||||
TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778"
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||||
PolygonSpacings=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.27"
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PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
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||||
MiterRadiuss=" 0.254 0.3175 0.635 1.27 2.54 1 2 2.5 5 7.5 10 0"
|
||||
DimensionWidths=" 0 0.127 0.254 0.1 0.26 0.13"
|
||||
DimensionExtWidths=" 0.127 0.254 0.1 0.13 0.26 0"
|
||||
DimensionExtLengths=" 1.27 2.54 1 2 3 0"
|
||||
DimensionExtOffsets=" 1.27 2.54 1 2 3 0"
|
||||
SmdSizes=" 0.3048 0.1524 0.4064 0.2032 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635"
|
||||
WireBend=0
|
||||
WireBendSet=31
|
||||
WireCap=1
|
||||
MiterStyle=0
|
||||
PadShape=0
|
||||
ViaShape=0
|
||||
PolygonPour=0
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||||
PolygonRank=0
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||||
PolygonThermals=1
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||||
PolygonOrphans=0
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||||
TextRatio=8
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||||
DimensionUnit=1
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||||
DimensionPrecision=2
|
||||
DimensionShowUnit=0
|
||||
PinDirection=3
|
||||
PinFunction=0
|
||||
PinLength=2
|
||||
PinVisible=3
|
||||
SwapLevel=0
|
||||
ArcDirection=0
|
||||
AddLevel=2
|
||||
PadsSameType=0
|
||||
Layer=91
|
||||
Views=" 1: -107.888 -36.8209 227.882 130.005"
|
||||
Sheet=1
|
||||
|
||||
[Desktop]
|
||||
Screen="1920 1080"
|
||||
Window="Win_1"
|
||||
Window="Win_2"
|
||||
Window="Win_3"
|
||||
812
eagle/Liron - original/74xx-us.lbr
Normal file
812
eagle/Liron - original/74xx-us.lbr
Normal file
@ -0,0 +1,812 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.6.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="1" unitdist="mic" unit="mic" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
|
||||
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="93" name="Pins" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
|
||||
</layers>
|
||||
<library>
|
||||
<packages>
|
||||
<package name="DIL14">
|
||||
<description><b>Dual In Line Package</b></description>
|
||||
<wire x1="8.89" y1="2.921" x2="-8.89" y2="2.921" width="0.1524" layer="21"/>
|
||||
<wire x1="-8.89" y1="-2.921" x2="8.89" y2="-2.921" width="0.1524" layer="21"/>
|
||||
<wire x1="8.89" y1="2.921" x2="8.89" y2="-2.921" width="0.1524" layer="21"/>
|
||||
<wire x1="-8.89" y1="2.921" x2="-8.89" y2="1.016" width="0.1524" layer="21"/>
|
||||
<wire x1="-8.89" y1="-2.921" x2="-8.89" y2="-1.016" width="0.1524" layer="21"/>
|
||||
<wire x1="-8.89" y1="1.016" x2="-8.89" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
|
||||
<pad name="1" x="-7.62" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="2" x="-5.08" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="3" x="-2.54" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="4" x="0" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="5" x="2.54" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="6" x="5.08" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="7" x="7.62" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="8" x="7.62" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="9" x="5.08" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="10" x="2.54" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="11" x="0" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="12" x="-2.54" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="13" x="-5.08" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="14" x="-7.62" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<text x="-9.271" y="-3.048" size="1.27" layer="25" ratio="10" rot="R90">>NAME</text>
|
||||
<text x="-6.731" y="-0.635" size="1.27" layer="27" ratio="10">>VALUE</text>
|
||||
</package>
|
||||
<package name="DIL20">
|
||||
<description><b>Dual In Line Package</b></description>
|
||||
<wire x1="12.7" y1="2.921" x2="-12.7" y2="2.921" width="0.1524" layer="21"/>
|
||||
<wire x1="-12.7" y1="-2.921" x2="12.7" y2="-2.921" width="0.1524" layer="21"/>
|
||||
<wire x1="12.7" y1="2.921" x2="12.7" y2="-2.921" width="0.1524" layer="21"/>
|
||||
<wire x1="-12.7" y1="2.921" x2="-12.7" y2="1.016" width="0.1524" layer="21"/>
|
||||
<wire x1="-12.7" y1="-2.921" x2="-12.7" y2="-1.016" width="0.1524" layer="21"/>
|
||||
<wire x1="-12.7" y1="1.016" x2="-12.7" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
|
||||
<pad name="1" x="-11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="2" x="-8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="3" x="-6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="4" x="-3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="5" x="-1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="6" x="1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="7" x="3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="8" x="6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="9" x="8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="10" x="11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="11" x="11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="12" x="8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="13" x="6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="14" x="3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="15" x="1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="16" x="-1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="17" x="-3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="18" x="-6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="19" x="-8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="20" x="-11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
|
||||
<text x="-13.081" y="-3.048" size="1.27" layer="25" rot="R90">>NAME</text>
|
||||
<text x="-9.779" y="-0.381" size="1.27" layer="27">>VALUE</text>
|
||||
</package>
|
||||
<package name="LCC20">
|
||||
<description><b>Leadless Chip Carrier</b><p> Ceramic Package</description>
|
||||
<wire x1="-0.4001" y1="4.4" x2="-0.87" y2="4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="-3.3" y1="4.4" x2="-4.4" y2="3.3" width="0.2032" layer="51"/>
|
||||
<wire x1="-0.4001" y1="4.3985" x2="0.4001" y2="4.3985" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="-1.6701" y1="4.3985" x2="-0.8699" y2="4.3985" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="-4.3985" y1="2.14" x2="-4.3985" y2="2.94" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="-2.9401" y1="4.4" x2="-3.3" y2="4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="0.87" y1="4.4" x2="0.4001" y2="4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="0.87" y1="4.3985" x2="1.67" y2="4.3985" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="-4.4" y1="3.3" x2="-4.4" y2="2.9401" width="0.2032" layer="51"/>
|
||||
<wire x1="-4.4" y1="2.14" x2="-4.4" y2="1.6701" width="0.2032" layer="51"/>
|
||||
<wire x1="-4.3985" y1="0.87" x2="-4.3985" y2="1.67" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="-4.3985" y1="-0.4001" x2="-4.3985" y2="0.4001" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="-4.3985" y1="-1.6701" x2="-4.3985" y2="-0.8699" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="-4.4" y1="0.87" x2="-4.4" y2="0.4001" width="0.2032" layer="51"/>
|
||||
<wire x1="-4.4" y1="-0.4001" x2="-4.4" y2="-0.87" width="0.2032" layer="51"/>
|
||||
<wire x1="-4.4" y1="-2.9401" x2="-4.4" y2="-4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="-4.4" y1="-4.4" x2="-4.4" y2="-4.4099" width="0.2032" layer="51"/>
|
||||
<wire x1="2.14" y1="4.3985" x2="2.94" y2="4.3985" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="2.14" y1="4.4" x2="1.6701" y2="4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="4.4" y1="4.4" x2="2.9401" y2="4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="0.4001" y1="-4.4" x2="0.87" y2="-4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="-0.4001" y1="-4.3985" x2="0.4001" y2="-4.3985" width="0.2032" layer="51" curve="-180"/>
|
||||
<wire x1="0.87" y1="-4.3985" x2="1.67" y2="-4.3985" width="0.2032" layer="51" curve="-180"/>
|
||||
<wire x1="2.9401" y1="-4.4" x2="4.4" y2="-4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="-0.87" y1="-4.4" x2="-0.4001" y2="-4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="-1.6701" y1="-4.3985" x2="-0.8699" y2="-4.3985" width="0.2032" layer="51" curve="-180"/>
|
||||
<wire x1="-2.9401" y1="-4.3985" x2="-2.1399" y2="-4.3985" width="0.2032" layer="51" curve="-180"/>
|
||||
<wire x1="-2.14" y1="-4.4" x2="-1.6701" y2="-4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="-4.4" y1="-4.4" x2="-2.9401" y2="-4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="4.4" y1="0.4001" x2="4.4" y2="0.87" width="0.2032" layer="51"/>
|
||||
<wire x1="4.3985" y1="0.4001" x2="4.3985" y2="-0.4001" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="4.3985" y1="1.6701" x2="4.3985" y2="0.8699" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="4.4" y1="2.9401" x2="4.4" y2="4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="4.4" y1="-0.87" x2="4.4" y2="-0.4001" width="0.2032" layer="51"/>
|
||||
<wire x1="4.3985" y1="-0.87" x2="4.3985" y2="-1.67" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="4.3985" y1="-2.14" x2="4.3985" y2="-2.94" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="4.4" y1="-2.14" x2="4.4" y2="-1.6701" width="0.2032" layer="51"/>
|
||||
<wire x1="4.4" y1="-4.4" x2="4.4" y2="-2.9401" width="0.2032" layer="51"/>
|
||||
<wire x1="-2.9401" y1="4.3985" x2="-2.1399" y2="4.3985" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="-1.6701" y1="4.4" x2="-2.14" y2="4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="-4.3985" y1="-2.9401" x2="-4.3985" y2="-2.1399" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="-4.4" y1="-1.6701" x2="-4.4" y2="-2.14" width="0.2032" layer="51"/>
|
||||
<wire x1="1.6701" y1="-4.4" x2="2.14" y2="-4.4" width="0.2032" layer="51"/>
|
||||
<wire x1="2.14" y1="-4.3985" x2="2.94" y2="-4.3985" width="0.2032" layer="51" curve="-180"/>
|
||||
<wire x1="4.3985" y1="2.9401" x2="4.3985" y2="2.1399" width="0.2032" layer="51" curve="180"/>
|
||||
<wire x1="4.4" y1="1.6701" x2="4.4" y2="2.14" width="0.2032" layer="51"/>
|
||||
<smd name="1" x="0" y="3.8001" dx="0.8" dy="3.4" layer="1"/>
|
||||
<smd name="2" x="-1.27" y="4.5001" dx="0.8" dy="2" layer="1"/>
|
||||
<smd name="3" x="-2.54" y="4.5001" dx="0.8" dy="2" layer="1"/>
|
||||
<smd name="4" x="-4.5001" y="2.54" dx="2" dy="0.8" layer="1"/>
|
||||
<smd name="5" x="-4.5001" y="1.27" dx="2" dy="0.8" layer="1"/>
|
||||
<smd name="6" x="-4.5001" y="0" dx="2" dy="0.8" layer="1"/>
|
||||
<smd name="7" x="-4.5001" y="-1.27" dx="2" dy="0.8" layer="1"/>
|
||||
<smd name="8" x="-4.5001" y="-2.54" dx="2" dy="0.8" layer="1"/>
|
||||
<smd name="9" x="-2.54" y="-4.5001" dx="0.8" dy="2" layer="1"/>
|
||||
<smd name="10" x="-1.27" y="-4.5001" dx="0.8" dy="2" layer="1"/>
|
||||
<smd name="11" x="0" y="-4.5001" dx="0.8" dy="2" layer="1"/>
|
||||
<smd name="12" x="1.27" y="-4.5001" dx="0.8" dy="2" layer="1"/>
|
||||
<smd name="13" x="2.54" y="-4.5001" dx="0.8" dy="2" layer="1"/>
|
||||
<smd name="14" x="4.5001" y="-2.54" dx="2" dy="0.8" layer="1"/>
|
||||
<smd name="15" x="4.5001" y="-1.27" dx="2" dy="0.8" layer="1"/>
|
||||
<smd name="16" x="4.5001" y="0" dx="2" dy="0.8" layer="1"/>
|
||||
<smd name="17" x="4.5001" y="1.27" dx="2" dy="0.8" layer="1"/>
|
||||
<smd name="18" x="4.5001" y="2.54" dx="2" dy="0.8" layer="1"/>
|
||||
<smd name="19" x="2.54" y="4.5001" dx="0.8" dy="2" layer="1"/>
|
||||
<smd name="20" x="1.27" y="4.5001" dx="0.8" dy="2" layer="1"/>
|
||||
<text x="-3.4971" y="5.811" size="1.778" layer="25">>NAME</text>
|
||||
<text x="-3.9751" y="-7.6871" size="1.778" layer="27">>VALUE</text>
|
||||
</package>
|
||||
<package name="SO14">
|
||||
<description><b>Small Outline package</b> 150 mil</description>
|
||||
<wire x1="4.064" y1="1.9558" x2="-4.064" y2="1.9558" width="0.1524" layer="21"/>
|
||||
<wire x1="4.064" y1="-1.9558" x2="4.445" y2="-1.5748" width="0.1524" layer="21" curve="90"/>
|
||||
<wire x1="-4.445" y1="1.5748" x2="-4.064" y2="1.9558" width="0.1524" layer="21" curve="-90"/>
|
||||
<wire x1="4.064" y1="1.9558" x2="4.445" y2="1.5748" width="0.1524" layer="21" curve="-90"/>
|
||||
<wire x1="-4.445" y1="-1.5748" x2="-4.064" y2="-1.9558" width="0.1524" layer="21" curve="90"/>
|
||||
<wire x1="-4.064" y1="-1.9558" x2="4.064" y2="-1.9558" width="0.1524" layer="21"/>
|
||||
<wire x1="4.445" y1="-1.5748" x2="4.445" y2="1.5748" width="0.1524" layer="21"/>
|
||||
<wire x1="-4.445" y1="1.5748" x2="-4.445" y2="0.508" width="0.1524" layer="21"/>
|
||||
<wire x1="-4.445" y1="0.508" x2="-4.445" y2="-0.508" width="0.1524" layer="21"/>
|
||||
<wire x1="-4.445" y1="-0.508" x2="-4.445" y2="-1.5748" width="0.1524" layer="21"/>
|
||||
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|
||||
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||||
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|
||||
<text x="-7.62" y="-17.78" size="1.778" layer="96">>VALUE</text>
|
||||
</symbol>
|
||||
<symbol name="PWRN">
|
||||
<pin name="GND" x="0" y="-10.16" visible="pad" direction="pwr" rot="R90"/>
|
||||
<pin name="VCC" x="0" y="10.16" visible="pad" direction="pwr" rot="R270"/>
|
||||
<text x="-0.635" y="-0.635" size="1.778" layer="95">>NAME</text>
|
||||
<text x="1.905" y="-7.62" size="1.27" layer="95" rot="R90">GND</text>
|
||||
<text x="1.905" y="5.08" size="1.27" layer="95" rot="R90">VCC</text>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="74*00" prefix="IC">
|
||||
<description>Quad 2-input <b>NAND</b> gate</description>
|
||||
<gates>
|
||||
<gate name="A" symbol="7400" x="20.32" y="0" swaplevel="1"/>
|
||||
<gate name="B" symbol="7400" x="20.32" y="-12.7" swaplevel="1"/>
|
||||
<gate name="C" symbol="7400" x="48.26" y="0" swaplevel="1"/>
|
||||
<gate name="D" symbol="7400" x="48.26" y="-12.7" swaplevel="1"/>
|
||||
<gate name="P" symbol="PWRN" x="2.54" y="-5.08" addlevel="request"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="D" package="SO14">
|
||||
<connects>
|
||||
<connect gate="A" pin="I0" pad="1"/>
|
||||
<connect gate="A" pin="I1" pad="2"/>
|
||||
<connect gate="A" pin="O" pad="3"/>
|
||||
<connect gate="B" pin="I0" pad="4"/>
|
||||
<connect gate="B" pin="I1" pad="5"/>
|
||||
<connect gate="B" pin="O" pad="6"/>
|
||||
<connect gate="C" pin="I0" pad="9"/>
|
||||
<connect gate="C" pin="I1" pad="10"/>
|
||||
<connect gate="C" pin="O" pad="8"/>
|
||||
<connect gate="D" pin="I0" pad="12"/>
|
||||
<connect gate="D" pin="I1" pad="13"/>
|
||||
<connect gate="D" pin="O" pad="11"/>
|
||||
<connect gate="P" pin="GND" pad="7"/>
|
||||
<connect gate="P" pin="VCC" pad="14"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="ALS"/>
|
||||
<technology name="AS"/>
|
||||
<technology name="LS"/>
|
||||
<technology name="S"/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="FK" package="LCC20">
|
||||
<connects>
|
||||
<connect gate="A" pin="I0" pad="2"/>
|
||||
<connect gate="A" pin="I1" pad="3"/>
|
||||
<connect gate="A" pin="O" pad="4"/>
|
||||
<connect gate="B" pin="I0" pad="6"/>
|
||||
<connect gate="B" pin="I1" pad="8"/>
|
||||
<connect gate="B" pin="O" pad="9"/>
|
||||
<connect gate="C" pin="I0" pad="13"/>
|
||||
<connect gate="C" pin="I1" pad="14"/>
|
||||
<connect gate="C" pin="O" pad="12"/>
|
||||
<connect gate="D" pin="I0" pad="18"/>
|
||||
<connect gate="D" pin="I1" pad="19"/>
|
||||
<connect gate="D" pin="O" pad="16"/>
|
||||
<connect gate="P" pin="GND" pad="10"/>
|
||||
<connect gate="P" pin="VCC" pad="20"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="ALS"/>
|
||||
<technology name="AS"/>
|
||||
<technology name="LS"/>
|
||||
<technology name="S"/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="N" package="DIL14">
|
||||
<connects>
|
||||
<connect gate="A" pin="I0" pad="1"/>
|
||||
<connect gate="A" pin="I1" pad="2"/>
|
||||
<connect gate="A" pin="O" pad="3"/>
|
||||
<connect gate="B" pin="I0" pad="4"/>
|
||||
<connect gate="B" pin="I1" pad="5"/>
|
||||
<connect gate="B" pin="O" pad="6"/>
|
||||
<connect gate="C" pin="I0" pad="9"/>
|
||||
<connect gate="C" pin="I1" pad="10"/>
|
||||
<connect gate="C" pin="O" pad="8"/>
|
||||
<connect gate="D" pin="I0" pad="12"/>
|
||||
<connect gate="D" pin="I1" pad="13"/>
|
||||
<connect gate="D" pin="O" pad="11"/>
|
||||
<connect gate="P" pin="GND" pad="7"/>
|
||||
<connect gate="P" pin="VCC" pad="14"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="ALS"/>
|
||||
<technology name="AS"/>
|
||||
<technology name="LS"/>
|
||||
<technology name="S"/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="74*20" prefix="IC">
|
||||
<description>Dual 4-input <b>NAND</b> gate</description>
|
||||
<gates>
|
||||
<gate name="A" symbol="7420" x="15.24" y="0" swaplevel="1"/>
|
||||
<gate name="B" symbol="7420" x="48.26" y="0" swaplevel="1"/>
|
||||
<gate name="P" symbol="PWRN" x="-7.62" y="0" addlevel="request"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="D" package="SO14">
|
||||
<connects>
|
||||
<connect gate="A" pin="I0" pad="1"/>
|
||||
<connect gate="A" pin="I1" pad="2"/>
|
||||
<connect gate="A" pin="I2" pad="4"/>
|
||||
<connect gate="A" pin="I3" pad="5"/>
|
||||
<connect gate="A" pin="O" pad="6"/>
|
||||
<connect gate="B" pin="I0" pad="9"/>
|
||||
<connect gate="B" pin="I1" pad="10"/>
|
||||
<connect gate="B" pin="I2" pad="12"/>
|
||||
<connect gate="B" pin="I3" pad="13"/>
|
||||
<connect gate="B" pin="O" pad="8"/>
|
||||
<connect gate="P" pin="GND" pad="7"/>
|
||||
<connect gate="P" pin="VCC" pad="14"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="ALS"/>
|
||||
<technology name="AS"/>
|
||||
<technology name="LS"/>
|
||||
<technology name="S"/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="FK" package="LCC20">
|
||||
<connects>
|
||||
<connect gate="A" pin="I0" pad="2"/>
|
||||
<connect gate="A" pin="I1" pad="3"/>
|
||||
<connect gate="A" pin="I2" pad="6"/>
|
||||
<connect gate="A" pin="I3" pad="8"/>
|
||||
<connect gate="A" pin="O" pad="9"/>
|
||||
<connect gate="B" pin="I0" pad="13"/>
|
||||
<connect gate="B" pin="I1" pad="14"/>
|
||||
<connect gate="B" pin="I2" pad="18"/>
|
||||
<connect gate="B" pin="I3" pad="19"/>
|
||||
<connect gate="B" pin="O" pad="12"/>
|
||||
<connect gate="P" pin="GND" pad="10"/>
|
||||
<connect gate="P" pin="VCC" pad="20"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="ALS"/>
|
||||
<technology name="AS"/>
|
||||
<technology name="LS"/>
|
||||
<technology name="S"/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="N" package="DIL14">
|
||||
<connects>
|
||||
<connect gate="A" pin="I0" pad="1"/>
|
||||
<connect gate="A" pin="I1" pad="2"/>
|
||||
<connect gate="A" pin="I2" pad="4"/>
|
||||
<connect gate="A" pin="I3" pad="5"/>
|
||||
<connect gate="A" pin="O" pad="6"/>
|
||||
<connect gate="B" pin="I0" pad="9"/>
|
||||
<connect gate="B" pin="I1" pad="10"/>
|
||||
<connect gate="B" pin="I2" pad="12"/>
|
||||
<connect gate="B" pin="I3" pad="13"/>
|
||||
<connect gate="B" pin="O" pad="8"/>
|
||||
<connect gate="P" pin="GND" pad="7"/>
|
||||
<connect gate="P" pin="VCC" pad="14"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="ALS"/>
|
||||
<technology name="AS"/>
|
||||
<technology name="LS"/>
|
||||
<technology name="S"/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="74*21" prefix="IC">
|
||||
<description>Dual 4-input <b>AND</b> gate</description>
|
||||
<gates>
|
||||
<gate name="A" symbol="7421" x="20.32" y="0" swaplevel="1"/>
|
||||
<gate name="B" symbol="7421" x="20.32" y="-17.78" swaplevel="1"/>
|
||||
<gate name="P" symbol="PWRN" x="2.54" y="-10.16" addlevel="request"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="D" package="SO14">
|
||||
<connects>
|
||||
<connect gate="A" pin="I0" pad="1"/>
|
||||
<connect gate="A" pin="I1" pad="2"/>
|
||||
<connect gate="A" pin="I2" pad="4"/>
|
||||
<connect gate="A" pin="I3" pad="5"/>
|
||||
<connect gate="A" pin="O" pad="6"/>
|
||||
<connect gate="B" pin="I0" pad="9"/>
|
||||
<connect gate="B" pin="I1" pad="10"/>
|
||||
<connect gate="B" pin="I2" pad="12"/>
|
||||
<connect gate="B" pin="I3" pad="13"/>
|
||||
<connect gate="B" pin="O" pad="8"/>
|
||||
<connect gate="P" pin="GND" pad="7"/>
|
||||
<connect gate="P" pin="VCC" pad="14"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="ALS"/>
|
||||
<technology name="AS"/>
|
||||
<technology name="LS"/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="FK" package="LCC20">
|
||||
<connects>
|
||||
<connect gate="A" pin="I0" pad="2"/>
|
||||
<connect gate="A" pin="I1" pad="3"/>
|
||||
<connect gate="A" pin="I2" pad="6"/>
|
||||
<connect gate="A" pin="I3" pad="8"/>
|
||||
<connect gate="A" pin="O" pad="9"/>
|
||||
<connect gate="B" pin="I0" pad="13"/>
|
||||
<connect gate="B" pin="I1" pad="14"/>
|
||||
<connect gate="B" pin="I2" pad="18"/>
|
||||
<connect gate="B" pin="I3" pad="19"/>
|
||||
<connect gate="B" pin="O" pad="12"/>
|
||||
<connect gate="P" pin="GND" pad="10"/>
|
||||
<connect gate="P" pin="VCC" pad="20"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="ALS"/>
|
||||
<technology name="AS"/>
|
||||
<technology name="LS"/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="N" package="DIL14">
|
||||
<connects>
|
||||
<connect gate="A" pin="I0" pad="1"/>
|
||||
<connect gate="A" pin="I1" pad="2"/>
|
||||
<connect gate="A" pin="I2" pad="4"/>
|
||||
<connect gate="A" pin="I3" pad="5"/>
|
||||
<connect gate="A" pin="O" pad="6"/>
|
||||
<connect gate="B" pin="I0" pad="9"/>
|
||||
<connect gate="B" pin="I1" pad="10"/>
|
||||
<connect gate="B" pin="I2" pad="12"/>
|
||||
<connect gate="B" pin="I3" pad="13"/>
|
||||
<connect gate="B" pin="O" pad="8"/>
|
||||
<connect gate="P" pin="GND" pad="7"/>
|
||||
<connect gate="P" pin="VCC" pad="14"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="ALS"/>
|
||||
<technology name="AS"/>
|
||||
<technology name="LS"/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="74*30" prefix="IC">
|
||||
<description>8-input <b>NAND</b> gate</description>
|
||||
<gates>
|
||||
<gate name="A" symbol="7430" x="12.7" y="0"/>
|
||||
<gate name="P" symbol="PWRN" x="-5.08" y="0" addlevel="request"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="D" package="SO14">
|
||||
<connects>
|
||||
<connect gate="A" pin="I0" pad="1"/>
|
||||
<connect gate="A" pin="I1" pad="2"/>
|
||||
<connect gate="A" pin="I2" pad="3"/>
|
||||
<connect gate="A" pin="I3" pad="4"/>
|
||||
<connect gate="A" pin="I4" pad="5"/>
|
||||
<connect gate="A" pin="I5" pad="6"/>
|
||||
<connect gate="A" pin="I6" pad="11"/>
|
||||
<connect gate="A" pin="I7" pad="12"/>
|
||||
<connect gate="A" pin="O" pad="8"/>
|
||||
<connect gate="P" pin="GND" pad="7"/>
|
||||
<connect gate="P" pin="VCC" pad="14"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="ALS"/>
|
||||
<technology name="AS"/>
|
||||
<technology name="LS"/>
|
||||
<technology name="S"/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="FK" package="LCC20">
|
||||
<connects>
|
||||
<connect gate="A" pin="I0" pad="2"/>
|
||||
<connect gate="A" pin="I1" pad="3"/>
|
||||
<connect gate="A" pin="I2" pad="4"/>
|
||||
<connect gate="A" pin="I3" pad="6"/>
|
||||
<connect gate="A" pin="I4" pad="8"/>
|
||||
<connect gate="A" pin="I5" pad="9"/>
|
||||
<connect gate="A" pin="I6" pad="16"/>
|
||||
<connect gate="A" pin="I7" pad="18"/>
|
||||
<connect gate="A" pin="O" pad="12"/>
|
||||
<connect gate="P" pin="GND" pad="10"/>
|
||||
<connect gate="P" pin="VCC" pad="20"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="ALS"/>
|
||||
<technology name="AS"/>
|
||||
<technology name="LS"/>
|
||||
<technology name="S"/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="N" package="DIL14">
|
||||
<connects>
|
||||
<connect gate="A" pin="I0" pad="1"/>
|
||||
<connect gate="A" pin="I1" pad="2"/>
|
||||
<connect gate="A" pin="I2" pad="3"/>
|
||||
<connect gate="A" pin="I3" pad="4"/>
|
||||
<connect gate="A" pin="I4" pad="5"/>
|
||||
<connect gate="A" pin="I5" pad="6"/>
|
||||
<connect gate="A" pin="I6" pad="11"/>
|
||||
<connect gate="A" pin="I7" pad="12"/>
|
||||
<connect gate="A" pin="O" pad="8"/>
|
||||
<connect gate="P" pin="GND" pad="7"/>
|
||||
<connect gate="P" pin="VCC" pad="14"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="ALS"/>
|
||||
<technology name="AS"/>
|
||||
<technology name="LS"/>
|
||||
<technology name="S"/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="74*245" prefix="IC">
|
||||
<description>Octal <b>BUS TRANSCEIVER</b>, 3-state</description>
|
||||
<gates>
|
||||
<gate name="A" symbol="74245" x="20.32" y="0"/>
|
||||
<gate name="P" symbol="PWRN" x="-5.08" y="0" addlevel="request"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="DW" package="SO20W">
|
||||
<connects>
|
||||
<connect gate="A" pin="A1" pad="2"/>
|
||||
<connect gate="A" pin="A2" pad="3"/>
|
||||
<connect gate="A" pin="A3" pad="4"/>
|
||||
<connect gate="A" pin="A4" pad="5"/>
|
||||
<connect gate="A" pin="A5" pad="6"/>
|
||||
<connect gate="A" pin="A6" pad="7"/>
|
||||
<connect gate="A" pin="A7" pad="8"/>
|
||||
<connect gate="A" pin="A8" pad="9"/>
|
||||
<connect gate="A" pin="B1" pad="18"/>
|
||||
<connect gate="A" pin="B2" pad="17"/>
|
||||
<connect gate="A" pin="B3" pad="16"/>
|
||||
<connect gate="A" pin="B4" pad="15"/>
|
||||
<connect gate="A" pin="B5" pad="14"/>
|
||||
<connect gate="A" pin="B6" pad="13"/>
|
||||
<connect gate="A" pin="B7" pad="12"/>
|
||||
<connect gate="A" pin="B8" pad="11"/>
|
||||
<connect gate="A" pin="DIR" pad="1"/>
|
||||
<connect gate="A" pin="G" pad="19"/>
|
||||
<connect gate="P" pin="GND" pad="10"/>
|
||||
<connect gate="P" pin="VCC" pad="20"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="LS"/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="FK" package="LCC20">
|
||||
<connects>
|
||||
<connect gate="A" pin="A1" pad="2"/>
|
||||
<connect gate="A" pin="A2" pad="3"/>
|
||||
<connect gate="A" pin="A3" pad="4"/>
|
||||
<connect gate="A" pin="A4" pad="5"/>
|
||||
<connect gate="A" pin="A5" pad="6"/>
|
||||
<connect gate="A" pin="A6" pad="7"/>
|
||||
<connect gate="A" pin="A7" pad="8"/>
|
||||
<connect gate="A" pin="A8" pad="9"/>
|
||||
<connect gate="A" pin="B1" pad="18"/>
|
||||
<connect gate="A" pin="B2" pad="17"/>
|
||||
<connect gate="A" pin="B3" pad="16"/>
|
||||
<connect gate="A" pin="B4" pad="15"/>
|
||||
<connect gate="A" pin="B5" pad="14"/>
|
||||
<connect gate="A" pin="B6" pad="13"/>
|
||||
<connect gate="A" pin="B7" pad="12"/>
|
||||
<connect gate="A" pin="B8" pad="11"/>
|
||||
<connect gate="A" pin="DIR" pad="1"/>
|
||||
<connect gate="A" pin="G" pad="19"/>
|
||||
<connect gate="P" pin="GND" pad="10"/>
|
||||
<connect gate="P" pin="VCC" pad="20"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="LS"/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="N" package="DIL20">
|
||||
<connects>
|
||||
<connect gate="A" pin="A1" pad="2"/>
|
||||
<connect gate="A" pin="A2" pad="3"/>
|
||||
<connect gate="A" pin="A3" pad="4"/>
|
||||
<connect gate="A" pin="A4" pad="5"/>
|
||||
<connect gate="A" pin="A5" pad="6"/>
|
||||
<connect gate="A" pin="A6" pad="7"/>
|
||||
<connect gate="A" pin="A7" pad="8"/>
|
||||
<connect gate="A" pin="A8" pad="9"/>
|
||||
<connect gate="A" pin="B1" pad="18"/>
|
||||
<connect gate="A" pin="B2" pad="17"/>
|
||||
<connect gate="A" pin="B3" pad="16"/>
|
||||
<connect gate="A" pin="B4" pad="15"/>
|
||||
<connect gate="A" pin="B5" pad="14"/>
|
||||
<connect gate="A" pin="B6" pad="13"/>
|
||||
<connect gate="A" pin="B7" pad="12"/>
|
||||
<connect gate="A" pin="B8" pad="11"/>
|
||||
<connect gate="A" pin="DIR" pad="1"/>
|
||||
<connect gate="A" pin="G" pad="19"/>
|
||||
<connect gate="P" pin="GND" pad="10"/>
|
||||
<connect gate="P" pin="VCC" pad="20"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
<technology name="LS"/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
</eagle>
|
||||
452
eagle/Liron - original/eagle.epf
Normal file
452
eagle/Liron - original/eagle.epf
Normal file
@ -0,0 +1,452 @@
|
||||
[Eagle]
|
||||
Version="06 06 00"
|
||||
Platform="Windows"
|
||||
Serial="62191E841E-LSR-WLM-1EL"
|
||||
Globals="Globals"
|
||||
Desktop="Desktop"
|
||||
|
||||
[Globals]
|
||||
AutoSaveProject=1
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/19inch.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/40xx.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/41xx.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/45xx.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/74ac-logic.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/74ttl-din.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/74xx-eu.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/74xx-little-de.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/74xx-little-us.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/74xx-us.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/751xx.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/advanced-test-technologies.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/agilent-technologies.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/allegro.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/altera-cyclone-II.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/altera-cyclone-III.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/altera-stratix-iv.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/altera.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/am29-memory.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/amd-mach.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/amd.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/amis.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/analog-devices.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/aplus.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/ase.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/atmel.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/austriamicrosystems.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/avago.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/axis.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/battery.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/belton-engineering.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/burr-brown.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/busbar.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/buzzer.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/c-trimm.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/california-micro-devices.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/capacitor-wima.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/chipcard-siemens.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/cirrus-logic.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-3m.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-4ucon.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-amp-champ.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-amp-micromatch.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-amp-mt.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-amp-mt6.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-amp-quick.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-amp-te.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-amp.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-amphenol.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-avx.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-berg.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-bosch.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-chipcard-iso7816.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-coax.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-commcon.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-conrad.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-cpci.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-cui.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-cypressindustries.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-deutsch.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-dil.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-ebyelectro.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-elco.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-erni.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-faston.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-fci.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-friwo.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-garry.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-harting-h.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-harting-ml.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-harting-v.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-harting.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-hirose.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-hirschmann.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-jack.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-jae.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-jst.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-kycon.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-kyocera-elco.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-lemo.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-leotronics.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-lsta.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-lstb.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-lumberg.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-ml.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-molex.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-neutrik_ag.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-omron.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-panasonic.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-panduit.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-pc.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-pc104.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-phoenix-254.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-phoenix-3.81.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-phoenix-350.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-phoenix-500.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-phoenix-508.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-phoenix-762.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-phoenix-me_max.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-phoenix-mkds_5.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-phoenix-smkdsp.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-ptr500.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-pulse.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-rib.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-samtec.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-shallin.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-shiua-chyuan.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-stewart.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-stocko.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-subd.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-sullinselectronics.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-thomas-betts.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-tyco.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-tycoelectronics.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-vg.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-wago-500.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-wago-508.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-wago.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-wago255.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-weidmueller-sl35.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-wenzhou-yihua.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-xmultiple.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/con-yamaichi.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/crystal.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/csr.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/cypress.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/davicom.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/dc-dc-converter.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/dimensions.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/diode.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/discrete.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/display-hp.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/display-kingbright.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/display-lcd.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/docu-dummy.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/eagle-ltspice.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/ecl.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/em-microelectronic.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/etx-board.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/exar.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/fairchild-semic.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/farnell.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/fiber-optic-hp.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/fiber-optic-siemens.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/fifo.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/flexipanel.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/fox-electronics.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/frames.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/freescale.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/ftdichip.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/fujitsu.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/fuse.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/gennum.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/halo-electronics.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/heatsink.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/holes.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/holtek.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/ic-package.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/inductor-coilcraft.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/inductor-neosid.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/inductor-nkl.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/inductors.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/infineon-tricore.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/infineon.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/intersil-techwell.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/intersil.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/ir.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/isd.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/johanson-technology.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/jump-0r-smd.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/jumper.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/lantronix.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/lattice.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/lc-filter.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/led-7-segment.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/led-citizen-electronics.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/led-lumiled.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/led.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/lem.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/linear-technology.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/linear.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/linx.lbr"
|
||||
UsedLibrary="C:/Program Files (x86)/EAGLE-6.6.0/lbr/logo.lbr"
|
||||
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|
||||
HoleDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6"
|
||||
TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778"
|
||||
PolygonSpacings=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.27"
|
||||
PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
|
||||
MiterRadiuss=" 0.254 0.3175 0.635 1.27 2.54 1 2 2.5 5 7.5 10 0"
|
||||
DimensionWidths=" 0 0.127 0.254 0.1 0.26 0.13"
|
||||
DimensionExtWidths=" 0.127 0.254 0.1 0.13 0.26 0"
|
||||
DimensionExtLengths=" 1.27 2.54 1 2 3 0"
|
||||
DimensionExtOffsets=" 1.27 2.54 1 2 3 0"
|
||||
SmdSizes=" 0.3048 0.1524 0.4064 0.2032 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635"
|
||||
WireBend=0
|
||||
WireBendSet=31
|
||||
WireCap=1
|
||||
MiterStyle=0
|
||||
PadShape=0
|
||||
ViaShape=0
|
||||
PolygonPour=0
|
||||
PolygonRank=0
|
||||
PolygonThermals=1
|
||||
PolygonOrphans=0
|
||||
TextRatio=8
|
||||
DimensionUnit=1
|
||||
DimensionPrecision=2
|
||||
DimensionShowUnit=0
|
||||
PinDirection=3
|
||||
PinFunction=0
|
||||
PinLength=2
|
||||
PinVisible=3
|
||||
SwapLevel=0
|
||||
ArcDirection=0
|
||||
AddLevel=2
|
||||
PadsSameType=0
|
||||
Layer=91
|
||||
Views=" 1: -51.7895 -103.761 267.738 101.65"
|
||||
Sheet=1
|
||||
|
||||
[Desktop]
|
||||
Screen="1920 1080"
|
||||
Window="Win_1"
|
||||
Window="Win_2"
|
||||
Window="Win_3"
|
||||
1139
eagle/Liron - original/liron.brd
Normal file
1139
eagle/Liron - original/liron.brd
Normal file
File diff suppressed because it is too large
Load Diff
1485
eagle/Liron - original/liron.lbr
Normal file
1485
eagle/Liron - original/liron.lbr
Normal file
File diff suppressed because it is too large
Load Diff
3461
eagle/Liron - original/liron.sch
Normal file
3461
eagle/Liron - original/liron.sch
Normal file
File diff suppressed because it is too large
Load Diff
1869
eagle/Liron - original/liron3.lbr
Normal file
1869
eagle/Liron - original/liron3.lbr
Normal file
File diff suppressed because it is too large
Load Diff
178
eagle/Liron - original/memory.lbr
Normal file
178
eagle/Liron - original/memory.lbr
Normal file
@ -0,0 +1,178 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.6.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="1" unitdist="mic" unit="mic" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
|
||||
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="93" name="Pins" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
|
||||
</layers>
|
||||
<library>
|
||||
<packages>
|
||||
<package name="DIL24">
|
||||
<description><b>Dual In Line Package</b></description>
|
||||
<wire x1="-15.24" y1="6.731" x2="-15.24" y2="1.016" width="0.1524" layer="21"/>
|
||||
<wire x1="-15.24" y1="-6.731" x2="-15.24" y2="-1.016" width="0.1524" layer="21"/>
|
||||
<wire x1="-15.24" y1="1.016" x2="-15.24" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
|
||||
<wire x1="-15.24" y1="-6.731" x2="15.24" y2="-6.731" width="0.1524" layer="21"/>
|
||||
<wire x1="15.24" y1="6.731" x2="15.24" y2="-6.731" width="0.1524" layer="21"/>
|
||||
<wire x1="15.24" y1="6.731" x2="-15.24" y2="6.731" width="0.1524" layer="21"/>
|
||||
<pad name="1" x="-13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="2" x="-11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="3" x="-8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="4" x="-6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="5" x="-3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="6" x="-1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="7" x="1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="8" x="3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="9" x="6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="10" x="8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="11" x="11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="12" x="13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="13" x="13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="14" x="11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="15" x="8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="16" x="6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="17" x="3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="18" x="1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="19" x="-1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="20" x="-3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="21" x="-6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="22" x="-8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="23" x="-11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<pad name="24" x="-13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
|
||||
<text x="-15.494" y="-6.731" size="1.778" layer="25" ratio="10" rot="R90">>NAME</text>
|
||||
<text x="-11.303" y="-0.889" size="1.778" layer="27" ratio="10">>VALUE</text>
|
||||
</package>
|
||||
</packages>
|
||||
<symbols>
|
||||
<symbol name="2716">
|
||||
<wire x1="-10.16" y1="-20.32" x2="5.08" y2="-20.32" width="0.4064" layer="94"/>
|
||||
<wire x1="5.08" y1="-20.32" x2="5.08" y2="20.32" width="0.4064" layer="94"/>
|
||||
<wire x1="5.08" y1="20.32" x2="-10.16" y2="20.32" width="0.4064" layer="94"/>
|
||||
<wire x1="-10.16" y1="20.32" x2="-10.16" y2="-20.32" width="0.4064" layer="94"/>
|
||||
<pin name="!CE" x="-15.24" y="-12.7" length="middle" direction="in"/>
|
||||
<pin name="!OE" x="-15.24" y="-15.24" length="middle" direction="in"/>
|
||||
<pin name="A0" x="-15.24" y="17.78" length="middle" direction="in"/>
|
||||
<pin name="A1" x="-15.24" y="15.24" length="middle" direction="in"/>
|
||||
<pin name="A2" x="-15.24" y="12.7" length="middle" direction="in"/>
|
||||
<pin name="A3" x="-15.24" y="10.16" length="middle" direction="in"/>
|
||||
<pin name="A4" x="-15.24" y="7.62" length="middle" direction="in"/>
|
||||
<pin name="A5" x="-15.24" y="5.08" length="middle" direction="in"/>
|
||||
<pin name="A6" x="-15.24" y="2.54" length="middle" direction="in"/>
|
||||
<pin name="A7" x="-15.24" y="0" length="middle" direction="in"/>
|
||||
<pin name="A8" x="-15.24" y="-2.54" length="middle" direction="in"/>
|
||||
<pin name="A9" x="-15.24" y="-5.08" length="middle" direction="in"/>
|
||||
<pin name="A10" x="-15.24" y="-7.62" length="middle" direction="in"/>
|
||||
<pin name="O0" x="10.16" y="17.78" length="middle" direction="hiz" rot="R180"/>
|
||||
<pin name="O1" x="10.16" y="15.24" length="middle" direction="hiz" rot="R180"/>
|
||||
<pin name="O2" x="10.16" y="12.7" length="middle" direction="hiz" rot="R180"/>
|
||||
<pin name="O3" x="10.16" y="10.16" length="middle" direction="hiz" rot="R180"/>
|
||||
<pin name="O4" x="10.16" y="7.62" length="middle" direction="hiz" rot="R180"/>
|
||||
<pin name="O5" x="10.16" y="5.08" length="middle" direction="hiz" rot="R180"/>
|
||||
<pin name="O6" x="10.16" y="2.54" length="middle" direction="hiz" rot="R180"/>
|
||||
<pin name="O7" x="10.16" y="0" length="middle" direction="hiz" rot="R180"/>
|
||||
<pin name="VPP" x="-15.24" y="-17.78" length="middle" direction="in"/>
|
||||
<text x="-10.16" y="20.955" size="1.778" layer="95">>NAME</text>
|
||||
<text x="-10.16" y="-22.86" size="1.778" layer="96">>VALUE</text>
|
||||
</symbol>
|
||||
<symbol name="PWRN">
|
||||
<pin name="GND" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
|
||||
<pin name="VCC" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
|
||||
<text x="-0.635" y="-0.635" size="1.778" layer="95">>NAME</text>
|
||||
<text x="1.905" y="-5.588" size="1.27" layer="95" rot="R90">GND</text>
|
||||
<text x="1.905" y="2.413" size="1.27" layer="95" rot="R90">VCC</text>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="2716" prefix="IC" uservalue="yes">
|
||||
<description><b>MEMORY</b></description>
|
||||
<gates>
|
||||
<gate name="A" symbol="2716" x="22.86" y="0"/>
|
||||
<gate name="P" symbol="PWRN" x="-7.62" y="0" addlevel="request"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="DIL24">
|
||||
<connects>
|
||||
<connect gate="A" pin="!CE" pad="18"/>
|
||||
<connect gate="A" pin="!OE" pad="20"/>
|
||||
<connect gate="A" pin="A0" pad="8"/>
|
||||
<connect gate="A" pin="A1" pad="7"/>
|
||||
<connect gate="A" pin="A10" pad="19"/>
|
||||
<connect gate="A" pin="A2" pad="6"/>
|
||||
<connect gate="A" pin="A3" pad="5"/>
|
||||
<connect gate="A" pin="A4" pad="4"/>
|
||||
<connect gate="A" pin="A5" pad="3"/>
|
||||
<connect gate="A" pin="A6" pad="2"/>
|
||||
<connect gate="A" pin="A7" pad="1"/>
|
||||
<connect gate="A" pin="A8" pad="23"/>
|
||||
<connect gate="A" pin="A9" pad="22"/>
|
||||
<connect gate="A" pin="O0" pad="9"/>
|
||||
<connect gate="A" pin="O1" pad="10"/>
|
||||
<connect gate="A" pin="O2" pad="11"/>
|
||||
<connect gate="A" pin="O3" pad="13"/>
|
||||
<connect gate="A" pin="O4" pad="14"/>
|
||||
<connect gate="A" pin="O5" pad="15"/>
|
||||
<connect gate="A" pin="O6" pad="16"/>
|
||||
<connect gate="A" pin="O7" pad="17"/>
|
||||
<connect gate="A" pin="VPP" pad="21"/>
|
||||
<connect gate="P" pin="GND" pad="12"/>
|
||||
<connect gate="P" pin="VCC" pad="24"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
</eagle>
|
||||
900
eagle/Liron - original/pinhead.lbr
Normal file
900
eagle/Liron - original/pinhead.lbr
Normal file
@ -0,0 +1,900 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.6.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="1" unitdist="mic" unit="mic" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
|
||||
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|
||||
<pad name="23" x="-1.27" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="24" x="-1.27" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="25" x="1.27" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="26" x="1.27" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="27" x="3.81" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="28" x="3.81" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="29" x="6.35" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="30" x="6.35" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="31" x="8.89" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="32" x="8.89" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="33" x="11.43" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="34" x="11.43" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="35" x="13.97" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="36" x="13.97" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="37" x="16.51" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="38" x="16.51" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="39" x="19.05" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="40" x="19.05" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="41" x="21.59" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="42" x="21.59" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="43" x="24.13" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="44" x="24.13" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="45" x="26.67" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="46" x="26.67" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="47" x="29.21" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="48" x="29.21" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<pad name="49" x="31.75" y="-3.81" drill="1.016" shape="octagon"/>
|
||||
<pad name="50" x="31.75" y="-6.35" drill="1.016" shape="octagon"/>
|
||||
<text x="-31.115" y="-3.81" size="1.27" layer="25" ratio="10" rot="R90">>NAME</text>
|
||||
<text x="34.925" y="-4.445" size="1.27" layer="27" rot="R90">>VALUE</text>
|
||||
</package>
|
||||
<package name="57102-F08-25">
|
||||
<description><b>UNSH HEADER</b> 2.0mm VERTICAL TMT<p>
|
||||
Source: https://portal.fciconnect.com/res/en/pdffiles/doc_search/57102.pdf</description>
|
||||
<wire x1="-10" y1="2" x2="40" y2="2" width="0.2032" layer="21"/>
|
||||
<wire x1="40" y1="2" x2="40" y2="-2" width="0.2032" layer="21"/>
|
||||
<wire x1="40" y1="-2" x2="-10" y2="-2" width="0.2032" layer="21"/>
|
||||
<wire x1="-10" y1="-2" x2="-10" y2="2" width="0.2032" layer="21"/>
|
||||
<pad name="1" x="-9" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="2" x="-9" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="3" x="-7" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="4" x="-7" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="5" x="-5" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="6" x="-5" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="7" x="-3" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="8" x="-3" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="9" x="-1" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="10" x="-1" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="11" x="1" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="12" x="1" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="13" x="3" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="14" x="3" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="15" x="5" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="16" x="5" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="17" x="7" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="18" x="7" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="19" x="9" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="20" x="9" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="21" x="11" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="22" x="11" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="23" x="13" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="24" x="13" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="25" x="15" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="26" x="15" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="27" x="17" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="28" x="17" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="29" x="19" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="30" x="19" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="31" x="21" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="32" x="21" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="33" x="23" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="34" x="23" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="35" x="25" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="36" x="25" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="37" x="27" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="38" x="27" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="39" x="29" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="40" x="29" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="41" x="31" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="42" x="31" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="43" x="33" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="44" x="33" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="45" x="35" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="46" x="35" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="47" x="37" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="48" x="37" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="49" x="39" y="-1" drill="0.8" diameter="1.4224"/>
|
||||
<pad name="50" x="39" y="1" drill="0.8" diameter="1.4224"/>
|
||||
<text x="-8.89" y="2.54" size="1.27" layer="25">>NAME</text>
|
||||
<text x="-8.89" y="-4.445" size="1.27" layer="27">>VALUE</text>
|
||||
</package>
|
||||
</packages>
|
||||
<symbols>
|
||||
<symbol name="PINH2X25">
|
||||
<wire x1="-6.35" y1="-33.02" x2="8.89" y2="-33.02" width="0.4064" layer="94"/>
|
||||
<wire x1="8.89" y1="-33.02" x2="8.89" y2="33.02" width="0.4064" layer="94"/>
|
||||
<wire x1="8.89" y1="33.02" x2="-6.35" y2="33.02" width="0.4064" layer="94"/>
|
||||
<wire x1="-6.35" y1="33.02" x2="-6.35" y2="-33.02" width="0.4064" layer="94"/>
|
||||
<pin name="1" x="-2.54" y="30.48" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="2" x="5.08" y="30.48" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="3" x="-2.54" y="27.94" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="4" x="5.08" y="27.94" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="5" x="-2.54" y="25.4" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="6" x="5.08" y="25.4" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="7" x="-2.54" y="22.86" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="8" x="5.08" y="22.86" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="9" x="-2.54" y="20.32" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="10" x="5.08" y="20.32" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="11" x="-2.54" y="17.78" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="12" x="5.08" y="17.78" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="13" x="-2.54" y="15.24" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="14" x="5.08" y="15.24" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="15" x="-2.54" y="12.7" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="16" x="5.08" y="12.7" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="17" x="-2.54" y="10.16" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="18" x="5.08" y="10.16" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="19" x="-2.54" y="7.62" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="20" x="5.08" y="7.62" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="21" x="-2.54" y="5.08" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="22" x="5.08" y="5.08" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="23" x="-2.54" y="2.54" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="24" x="5.08" y="2.54" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="25" x="-2.54" y="0" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="26" x="5.08" y="0" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="27" x="-2.54" y="-2.54" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="28" x="5.08" y="-2.54" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="29" x="-2.54" y="-5.08" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="30" x="5.08" y="-5.08" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="31" x="-2.54" y="-7.62" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="32" x="5.08" y="-7.62" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="33" x="-2.54" y="-10.16" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="34" x="5.08" y="-10.16" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="35" x="-2.54" y="-12.7" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="36" x="5.08" y="-12.7" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="37" x="-2.54" y="-15.24" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="38" x="5.08" y="-15.24" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="39" x="-2.54" y="-17.78" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="40" x="5.08" y="-17.78" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="41" x="-2.54" y="-20.32" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="42" x="5.08" y="-20.32" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="43" x="-2.54" y="-22.86" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="44" x="5.08" y="-22.86" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="45" x="-2.54" y="-25.4" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="46" x="5.08" y="-25.4" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="47" x="-2.54" y="-27.94" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="48" x="5.08" y="-27.94" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<pin name="49" x="-2.54" y="-30.48" visible="pad" length="short" direction="pas" function="dot"/>
|
||||
<pin name="50" x="5.08" y="-30.48" visible="pad" length="short" direction="pas" function="dot" rot="R180"/>
|
||||
<text x="-6.35" y="33.655" size="1.778" layer="95">>NAME</text>
|
||||
<text x="-6.35" y="-35.56" size="1.778" layer="96">>VALUE</text>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="PINHD-2X25" prefix="JP" uservalue="yes">
|
||||
<description><b>PIN HEADER</b></description>
|
||||
<gates>
|
||||
<gate name="A" symbol="PINH2X25" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="2X25">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="10" pad="10"/>
|
||||
<connect gate="A" pin="11" pad="11"/>
|
||||
<connect gate="A" pin="12" pad="12"/>
|
||||
<connect gate="A" pin="13" pad="13"/>
|
||||
<connect gate="A" pin="14" pad="14"/>
|
||||
<connect gate="A" pin="15" pad="15"/>
|
||||
<connect gate="A" pin="16" pad="16"/>
|
||||
<connect gate="A" pin="17" pad="17"/>
|
||||
<connect gate="A" pin="18" pad="18"/>
|
||||
<connect gate="A" pin="19" pad="19"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="20" pad="20"/>
|
||||
<connect gate="A" pin="21" pad="21"/>
|
||||
<connect gate="A" pin="22" pad="22"/>
|
||||
<connect gate="A" pin="23" pad="23"/>
|
||||
<connect gate="A" pin="24" pad="24"/>
|
||||
<connect gate="A" pin="25" pad="25"/>
|
||||
<connect gate="A" pin="26" pad="26"/>
|
||||
<connect gate="A" pin="27" pad="27"/>
|
||||
<connect gate="A" pin="28" pad="28"/>
|
||||
<connect gate="A" pin="29" pad="29"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="30" pad="30"/>
|
||||
<connect gate="A" pin="31" pad="31"/>
|
||||
<connect gate="A" pin="32" pad="32"/>
|
||||
<connect gate="A" pin="33" pad="33"/>
|
||||
<connect gate="A" pin="34" pad="34"/>
|
||||
<connect gate="A" pin="35" pad="35"/>
|
||||
<connect gate="A" pin="36" pad="36"/>
|
||||
<connect gate="A" pin="37" pad="37"/>
|
||||
<connect gate="A" pin="38" pad="38"/>
|
||||
<connect gate="A" pin="39" pad="39"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="40" pad="40"/>
|
||||
<connect gate="A" pin="41" pad="41"/>
|
||||
<connect gate="A" pin="42" pad="42"/>
|
||||
<connect gate="A" pin="43" pad="43"/>
|
||||
<connect gate="A" pin="44" pad="44"/>
|
||||
<connect gate="A" pin="45" pad="45"/>
|
||||
<connect gate="A" pin="46" pad="46"/>
|
||||
<connect gate="A" pin="47" pad="47"/>
|
||||
<connect gate="A" pin="48" pad="48"/>
|
||||
<connect gate="A" pin="49" pad="49"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="50" pad="50"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
<connect gate="A" pin="7" pad="7"/>
|
||||
<connect gate="A" pin="8" pad="8"/>
|
||||
<connect gate="A" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="/90" package="2X25/90">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="10" pad="10"/>
|
||||
<connect gate="A" pin="11" pad="11"/>
|
||||
<connect gate="A" pin="12" pad="12"/>
|
||||
<connect gate="A" pin="13" pad="13"/>
|
||||
<connect gate="A" pin="14" pad="14"/>
|
||||
<connect gate="A" pin="15" pad="15"/>
|
||||
<connect gate="A" pin="16" pad="16"/>
|
||||
<connect gate="A" pin="17" pad="17"/>
|
||||
<connect gate="A" pin="18" pad="18"/>
|
||||
<connect gate="A" pin="19" pad="19"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="20" pad="20"/>
|
||||
<connect gate="A" pin="21" pad="21"/>
|
||||
<connect gate="A" pin="22" pad="22"/>
|
||||
<connect gate="A" pin="23" pad="23"/>
|
||||
<connect gate="A" pin="24" pad="24"/>
|
||||
<connect gate="A" pin="25" pad="25"/>
|
||||
<connect gate="A" pin="26" pad="26"/>
|
||||
<connect gate="A" pin="27" pad="27"/>
|
||||
<connect gate="A" pin="28" pad="28"/>
|
||||
<connect gate="A" pin="29" pad="29"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="30" pad="30"/>
|
||||
<connect gate="A" pin="31" pad="31"/>
|
||||
<connect gate="A" pin="32" pad="32"/>
|
||||
<connect gate="A" pin="33" pad="33"/>
|
||||
<connect gate="A" pin="34" pad="34"/>
|
||||
<connect gate="A" pin="35" pad="35"/>
|
||||
<connect gate="A" pin="36" pad="36"/>
|
||||
<connect gate="A" pin="37" pad="37"/>
|
||||
<connect gate="A" pin="38" pad="38"/>
|
||||
<connect gate="A" pin="39" pad="39"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="40" pad="40"/>
|
||||
<connect gate="A" pin="41" pad="41"/>
|
||||
<connect gate="A" pin="42" pad="42"/>
|
||||
<connect gate="A" pin="43" pad="43"/>
|
||||
<connect gate="A" pin="44" pad="44"/>
|
||||
<connect gate="A" pin="45" pad="45"/>
|
||||
<connect gate="A" pin="46" pad="46"/>
|
||||
<connect gate="A" pin="47" pad="47"/>
|
||||
<connect gate="A" pin="48" pad="48"/>
|
||||
<connect gate="A" pin="49" pad="49"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="50" pad="50"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
<connect gate="A" pin="7" pad="7"/>
|
||||
<connect gate="A" pin="8" pad="8"/>
|
||||
<connect gate="A" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="_57102-F08-25" package="57102-F08-25">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="10" pad="10"/>
|
||||
<connect gate="A" pin="11" pad="11"/>
|
||||
<connect gate="A" pin="12" pad="12"/>
|
||||
<connect gate="A" pin="13" pad="13"/>
|
||||
<connect gate="A" pin="14" pad="14"/>
|
||||
<connect gate="A" pin="15" pad="15"/>
|
||||
<connect gate="A" pin="16" pad="16"/>
|
||||
<connect gate="A" pin="17" pad="17"/>
|
||||
<connect gate="A" pin="18" pad="18"/>
|
||||
<connect gate="A" pin="19" pad="19"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="20" pad="20"/>
|
||||
<connect gate="A" pin="21" pad="21"/>
|
||||
<connect gate="A" pin="22" pad="22"/>
|
||||
<connect gate="A" pin="23" pad="23"/>
|
||||
<connect gate="A" pin="24" pad="24"/>
|
||||
<connect gate="A" pin="25" pad="25"/>
|
||||
<connect gate="A" pin="26" pad="26"/>
|
||||
<connect gate="A" pin="27" pad="27"/>
|
||||
<connect gate="A" pin="28" pad="28"/>
|
||||
<connect gate="A" pin="29" pad="29"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="30" pad="30"/>
|
||||
<connect gate="A" pin="31" pad="31"/>
|
||||
<connect gate="A" pin="32" pad="32"/>
|
||||
<connect gate="A" pin="33" pad="33"/>
|
||||
<connect gate="A" pin="34" pad="34"/>
|
||||
<connect gate="A" pin="35" pad="35"/>
|
||||
<connect gate="A" pin="36" pad="36"/>
|
||||
<connect gate="A" pin="37" pad="37"/>
|
||||
<connect gate="A" pin="38" pad="38"/>
|
||||
<connect gate="A" pin="39" pad="39"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="40" pad="40"/>
|
||||
<connect gate="A" pin="41" pad="41"/>
|
||||
<connect gate="A" pin="42" pad="42"/>
|
||||
<connect gate="A" pin="43" pad="43"/>
|
||||
<connect gate="A" pin="44" pad="44"/>
|
||||
<connect gate="A" pin="45" pad="45"/>
|
||||
<connect gate="A" pin="46" pad="46"/>
|
||||
<connect gate="A" pin="47" pad="47"/>
|
||||
<connect gate="A" pin="48" pad="48"/>
|
||||
<connect gate="A" pin="49" pad="49"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="50" pad="50"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
<connect gate="A" pin="7" pad="7"/>
|
||||
<connect gate="A" pin="8" pad="8"/>
|
||||
<connect gate="A" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
</eagle>
|
||||
2574
lattice/._Real_._Math_.vhd
Normal file
2574
lattice/._Real_._Math_.vhd
Normal file
File diff suppressed because it is too large
Load Diff
14
lattice/.floorplanner.ini
Normal file
14
lattice/.floorplanner.ini
Normal file
@ -0,0 +1,14 @@
|
||||
[General]
|
||||
showNCD=true
|
||||
showPgroups=true
|
||||
showCongestion=false
|
||||
showConnsSelect=false
|
||||
showConnsBetween=true
|
||||
showConnsOutside=true
|
||||
showLPF=true
|
||||
showREGIONs=true
|
||||
showUGROUPs=true
|
||||
showPARITIONs=true
|
||||
showLogicalConnections=false
|
||||
dontShowBBoxOverlapWarning=false
|
||||
sceneInViewRect=@Variant(\0\0\0\x14@\x99\0\0\0\0\0\0@\xd0\x63\0\0\0\0\0@\xd4\xc3\0\0\0\0\0@\xc2\x8e\0\0\0\0\0)
|
||||
9
lattice/.run_manager.ini
Normal file
9
lattice/.run_manager.ini
Normal file
@ -0,0 +1,9 @@
|
||||
[Runmanager]
|
||||
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
|
||||
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
|
||||
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
|
||||
|
||||
[fpgatop%3CStrategy1%3E]
|
||||
isChecked=false
|
||||
isHidden=false
|
||||
isExpanded=false
|
||||
4
lattice/.setting.ini
Normal file
4
lattice/.setting.ini
Normal file
@ -0,0 +1,4 @@
|
||||
[General]
|
||||
PAR.auto_tasks=PARTrace
|
||||
AutoAssign=false
|
||||
Export.auto_tasks=Jedecgen
|
||||
3
lattice/.spread_sheet.ini
Normal file
3
lattice/.spread_sheet.ini
Normal file
@ -0,0 +1,3 @@
|
||||
[General]
|
||||
COLUMN_POS_INFO_NAME_-1_0=Prioritize
|
||||
COLUMN_POS_INFO_NAME_-1_1=PIO Register
|
||||
76
lattice/.spreadsheet_view.ini
Normal file
76
lattice/.spreadsheet_view.ini
Normal file
@ -0,0 +1,76 @@
|
||||
[General]
|
||||
pin_sort_type=0
|
||||
pin_sort_ascending=true
|
||||
sig_sort_type=0
|
||||
sig_sort_ascending=true
|
||||
active_Sheet=Port Assignments
|
||||
|
||||
[Port%20Assignments]
|
||||
Name="183,0"
|
||||
Group%20By="84,1"
|
||||
Pin="50,2"
|
||||
BANK="62,3"
|
||||
IO_TYPE="80,4"
|
||||
PULLMODE="92,5"
|
||||
DRIVE="67,9"
|
||||
SLEWRATE="92,6"
|
||||
OPENDRAIN="97,10"
|
||||
Outload%20%28pF%29="103,11"
|
||||
MaxSkew="87,14"
|
||||
Clock%20Load%20Only="121,13"
|
||||
sort_columns="BANK,Ascending"
|
||||
BANK_VCC="90,7"
|
||||
VREF="60,8"
|
||||
CLAMP="71,12"
|
||||
DIFFRESISTOR="114,15"
|
||||
DIFFDRIVE="92,16"
|
||||
HYSTERESIS="101,17"
|
||||
SwitchingID="100,18"
|
||||
Ground%20plane%20PCB%20noise%20%28mV%29="196,19"
|
||||
Power%20plane%20PCB%20noise%20%28mV%29="190,20"
|
||||
SSO%20Allowance%28%25%29="138,21"
|
||||
|
||||
[Pin%20Assignments]
|
||||
Pin="90,0"
|
||||
Pad%20Name="89,1"
|
||||
Dual%20Function="158,2"
|
||||
Polarity="77,3"
|
||||
BANK="0,4"
|
||||
IO_TYPE="80,5"
|
||||
Signal%20Name="102,6"
|
||||
Signal%20Type="98,7"
|
||||
sort_columns="Pin,Ascending"
|
||||
BANK_VCC="90,8"
|
||||
|
||||
[Clock%20Resource]
|
||||
Clock%20Type="100,ELLIPSIS"
|
||||
Clock%20Name="100,ELLIPSIS"
|
||||
Selection="100,ELLIPSIS"
|
||||
|
||||
[Global%20Preferences]
|
||||
Preference%20Name="230,ELLIPSIS"
|
||||
Preference%20Value="236,ELLIPSIS"
|
||||
|
||||
[Cell%20Mapping]
|
||||
Type="100,ELLIPSIS"
|
||||
Name="100,ELLIPSIS"
|
||||
Din\Dout="100,ELLIPSIS"
|
||||
PIO%20Register="100,ELLIPSIS"
|
||||
|
||||
[Route%20Priority]
|
||||
Type="100,ELLIPSIS"
|
||||
Name="100,ELLIPSIS"
|
||||
Prioritize="100,ELLIPSIS"
|
||||
|
||||
[Timing%20Preferences]
|
||||
Preference%20Name="129,ELLIPSIS"
|
||||
Preference%20Value="104,ELLIPSIS"
|
||||
Preference%20Unit="98,ELLIPSIS"
|
||||
|
||||
[Group]
|
||||
Group%20Type\Name="134,ELLIPSIS"
|
||||
Value="38,ELLIPSIS"
|
||||
|
||||
[Misc%20Preferences]
|
||||
Preference%20Name="162,ELLIPSIS"
|
||||
Preference%20Value="104,ELLIPSIS"
|
||||
4
lattice/Untitled.tpf
Normal file
4
lattice/Untitled.tpf
Normal file
@ -0,0 +1,4 @@
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
AUTOMOTIVE ;
|
||||
FREQUENCY NET "fclk_c" 318.066000 MHz ;
|
||||
37
lattice/addrDecoder.v
Normal file
37
lattice/addrDecoder.v
Normal file
@ -0,0 +1,37 @@
|
||||
`timescale 1 ns / 1 ps
|
||||
module addrDecoder(
|
||||
input [11:0] addr,
|
||||
//input _devsel, // 16 bytes (for IWM)
|
||||
input fclk,
|
||||
input _iostrobe, // shared 2K space
|
||||
input _iosel, // card-specific 256 bytes
|
||||
input _reset,
|
||||
output _romoe, // 0 if the card's ROM should drive its output right now
|
||||
output reg romExpansionActive // 1 if the Yellowstone card's ROM is the currently selected slot ROM
|
||||
);
|
||||
|
||||
wire histrobe = ~_iostrobe & (addr == 12'hFFF);
|
||||
|
||||
/*reg [1:0] histrobeHistory;
|
||||
reg [1:0] ioselHistory;
|
||||
|
||||
always @(posedge fclk) begin
|
||||
histrobeHistory <= { histrobeHistory[0], histrobe };
|
||||
ioselHistory <= { ioselHistory[0], _iosel };
|
||||
end*/
|
||||
|
||||
//wire clearActive = histrobe || ~_reset;
|
||||
//always @(posedge fclk or posedge clearActive) begin
|
||||
always @(posedge fclk) begin
|
||||
//if (clearActive)
|
||||
//if (histrobeHistory == 2'b11)
|
||||
if (histrobe)
|
||||
romExpansionActive <= 0;
|
||||
//else if (ioselHistory == 2'b00)
|
||||
else if (~_iosel)
|
||||
romExpansionActive <= 1;
|
||||
end
|
||||
|
||||
assign _romoe = ~(~_iosel || (romExpansionActive && ~_iostrobe));
|
||||
|
||||
endmodule
|
||||
918
lattice/codeROM.edn
Normal file
918
lattice/codeROM.edn
Normal file
@ -0,0 +1,918 @@
|
||||
(edif codeROM
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2018 1 30 17 35 12)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.9.0.99.2"))))
|
||||
(comment "C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n codeROM -lang verilog -synth lse -bus_exp 7 -bb -arch xo2c00 -type bram -wp 00 -rp 1100 -addr_width 12 -data_width 8 -num_rows 4096 -outdata REGISTERED -cascade 11 -resetmode SYNC -sync_reset -memfile c:/users/chamberlin/documents/liron/rom-full-4k.mem -memformat hex ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell DP8KC
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DIA8
|
||||
(direction INPUT))
|
||||
(port DIA7
|
||||
(direction INPUT))
|
||||
(port DIA6
|
||||
(direction INPUT))
|
||||
(port DIA5
|
||||
(direction INPUT))
|
||||
(port DIA4
|
||||
(direction INPUT))
|
||||
(port DIA3
|
||||
(direction INPUT))
|
||||
(port DIA2
|
||||
(direction INPUT))
|
||||
(port DIA1
|
||||
(direction INPUT))
|
||||
(port DIA0
|
||||
(direction INPUT))
|
||||
(port ADA12
|
||||
(direction INPUT))
|
||||
(port ADA11
|
||||
(direction INPUT))
|
||||
(port ADA10
|
||||
(direction INPUT))
|
||||
(port ADA9
|
||||
(direction INPUT))
|
||||
(port ADA8
|
||||
(direction INPUT))
|
||||
(port ADA7
|
||||
(direction INPUT))
|
||||
(port ADA6
|
||||
(direction INPUT))
|
||||
(port ADA5
|
||||
(direction INPUT))
|
||||
(port ADA4
|
||||
(direction INPUT))
|
||||
(port ADA3
|
||||
(direction INPUT))
|
||||
(port ADA2
|
||||
(direction INPUT))
|
||||
(port ADA1
|
||||
(direction INPUT))
|
||||
(port ADA0
|
||||
(direction INPUT))
|
||||
(port CEA
|
||||
(direction INPUT))
|
||||
(port OCEA
|
||||
(direction INPUT))
|
||||
(port CLKA
|
||||
(direction INPUT))
|
||||
(port WEA
|
||||
(direction INPUT))
|
||||
(port CSA2
|
||||
(direction INPUT))
|
||||
(port CSA1
|
||||
(direction INPUT))
|
||||
(port CSA0
|
||||
(direction INPUT))
|
||||
(port RSTA
|
||||
(direction INPUT))
|
||||
(port DIB8
|
||||
(direction INPUT))
|
||||
(port DIB7
|
||||
(direction INPUT))
|
||||
(port DIB6
|
||||
(direction INPUT))
|
||||
(port DIB5
|
||||
(direction INPUT))
|
||||
(port DIB4
|
||||
(direction INPUT))
|
||||
(port DIB3
|
||||
(direction INPUT))
|
||||
(port DIB2
|
||||
(direction INPUT))
|
||||
(port DIB1
|
||||
(direction INPUT))
|
||||
(port DIB0
|
||||
(direction INPUT))
|
||||
(port ADB12
|
||||
(direction INPUT))
|
||||
(port ADB11
|
||||
(direction INPUT))
|
||||
(port ADB10
|
||||
(direction INPUT))
|
||||
(port ADB9
|
||||
(direction INPUT))
|
||||
(port ADB8
|
||||
(direction INPUT))
|
||||
(port ADB7
|
||||
(direction INPUT))
|
||||
(port ADB6
|
||||
(direction INPUT))
|
||||
(port ADB5
|
||||
(direction INPUT))
|
||||
(port ADB4
|
||||
(direction INPUT))
|
||||
(port ADB3
|
||||
(direction INPUT))
|
||||
(port ADB2
|
||||
(direction INPUT))
|
||||
(port ADB1
|
||||
(direction INPUT))
|
||||
(port ADB0
|
||||
(direction INPUT))
|
||||
(port CEB
|
||||
(direction INPUT))
|
||||
(port OCEB
|
||||
(direction INPUT))
|
||||
(port CLKB
|
||||
(direction INPUT))
|
||||
(port WEB
|
||||
(direction INPUT))
|
||||
(port CSB2
|
||||
(direction INPUT))
|
||||
(port CSB1
|
||||
(direction INPUT))
|
||||
(port CSB0
|
||||
(direction INPUT))
|
||||
(port RSTB
|
||||
(direction INPUT))
|
||||
(port DOA8
|
||||
(direction OUTPUT))
|
||||
(port DOA7
|
||||
(direction OUTPUT))
|
||||
(port DOA6
|
||||
(direction OUTPUT))
|
||||
(port DOA5
|
||||
(direction OUTPUT))
|
||||
(port DOA4
|
||||
(direction OUTPUT))
|
||||
(port DOA3
|
||||
(direction OUTPUT))
|
||||
(port DOA2
|
||||
(direction OUTPUT))
|
||||
(port DOA1
|
||||
(direction OUTPUT))
|
||||
(port DOA0
|
||||
(direction OUTPUT))
|
||||
(port DOB8
|
||||
(direction OUTPUT))
|
||||
(port DOB7
|
||||
(direction OUTPUT))
|
||||
(port DOB6
|
||||
(direction OUTPUT))
|
||||
(port DOB5
|
||||
(direction OUTPUT))
|
||||
(port DOB4
|
||||
(direction OUTPUT))
|
||||
(port DOB3
|
||||
(direction OUTPUT))
|
||||
(port DOB2
|
||||
(direction OUTPUT))
|
||||
(port DOB1
|
||||
(direction OUTPUT))
|
||||
(port DOB0
|
||||
(direction OUTPUT)))))
|
||||
(cell codeROM
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename Address "Address(11:0)") 12)
|
||||
(direction INPUT))
|
||||
(port OutClock
|
||||
(direction INPUT))
|
||||
(port OutClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(7:0)") 8)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance codeROM_0_0_0_3
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "SYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "codeROM.lpc"))
|
||||
(property MEM_INIT_FILE
|
||||
(string "rom-full-4k.mem"))
|
||||
(property INITVAL_1F
|
||||
(string "0x1E07417209022F10021108E3F1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF"))
|
||||
(property INITVAL_1E
|
||||
(string "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE00020F8186D01C04D"))
|
||||
(property INITVAL_1D
|
||||
(string "0x15E1D120E31A04907C101C4E907A0100A220348D1501A10040108480DCA3060680522C024AA0301B"))
|
||||
(property INITVAL_1C
|
||||
(string "0x0409311AAA038091CA2100C48108441187602A9309231012450840A080240AA6A19A150229D13219"))
|
||||
(property INITVAL_1B
|
||||
(string "0x0B4241A461086D51BEC10008408C44000040484209A4109AE8024401440402C3400A611A8640022C"))
|
||||
(property INITVAL_1A
|
||||
(string "0x1363C0121809242080101920B06C5614E8210C2118CC008C40090500061D14A51030A219A1D15C99"))
|
||||
(property INITVAL_19
|
||||
(string "0x1121113A76160120325902A5C198800864108242194C1024C00884118E011848212E2500A41108C8"))
|
||||
(property INITVAL_18
|
||||
(string "0x0265D148D0012101220706429092441089108A840A233002E2130091B0A21AA05062DC0B04204078"))
|
||||
(property INITVAL_17
|
||||
(string "0x0101809644088041123019C81006A0090BA1DC23080D20864E00A041D09D04A88030410C88D02A91"))
|
||||
(property INITVAL_16
|
||||
(string "0x00A800341502014022C008A111341208A09036221085F0108B0ECD11B0D104A4606A5510C1D12C44"))
|
||||
(property INITVAL_15
|
||||
(string "0x03C0403A5C15E241244902040000890881302005080C410022012C50C203032850A2010581918A61"))
|
||||
(property INITVAL_14
|
||||
(string "0x0A06210241094010800000000000000000000000000000000000000014A8084410481B0064D16048"))
|
||||
(property INITVAL_13
|
||||
(string "0x1101C11610002451601102E0002420002180D8050D80406856088C10804409ADC00C030C0C00C05C"))
|
||||
(property INITVAL_12
|
||||
(string "0x048590684112AD5122110A0A919ECF00204004601624010250082400A09808AC00484419C1A1B214"))
|
||||
(property INITVAL_11
|
||||
(string "0x0E86A0C851122A512245080CE082A11224408CB608A1D03499028650AC4019C4114A9402E0008251"))
|
||||
(property INITVAL_10
|
||||
(string "0x0A82706670008410E0251881400E500226110835108060C017004441BA410A800184600A67419228"))
|
||||
(property INITVAL_0F
|
||||
(string "0x160300301000E0902A28102000400C000560601D02E011E6380229B0E01008C6D18041032B70026E"))
|
||||
(property INITVAL_0E
|
||||
(string "0x100460DAC00821916E01008661B807140111367002AD516CA5180701864309E7B05C021C20803C22"))
|
||||
(property INITVAL_0D
|
||||
(string "0x160300301000E0902A28102000400C000560601D02E01166380229B0E01008C6D18041032B70026E"))
|
||||
(property INITVAL_0C
|
||||
(string "0x100460DAC00821916E01008661B807140111367002AD516CA5180601864309E6B054021420803C22"))
|
||||
(property INITVAL_0B
|
||||
(string "0x160300301000E0902A28102000400C000560601D02E010E6380229B0E01008C6D18041032B70026E"))
|
||||
(property INITVAL_0A
|
||||
(string "0x100460DAC00821916E01008661B807140111367002AD516CA5180501864309E5B04C020C20803C22"))
|
||||
(property INITVAL_09
|
||||
(string "0x160300301000E0902A28102000400C000560601D02E01066380229B0E01008C6D18041032B70026E"))
|
||||
(property INITVAL_08
|
||||
(string "0x100460DAC00821916E01008661B807140111367002AD516CA5180401864309E4B044020420803C22"))
|
||||
(property INITVAL_07
|
||||
(string "0x160300301000E0902A28102000400C000560601D02E011E6380229B0E01008C6D18041032B70026E"))
|
||||
(property INITVAL_06
|
||||
(string "0x100460DAC00821916E01008661B807140111367002AD516CA5180701864309E7B05C021C20803C22"))
|
||||
(property INITVAL_05
|
||||
(string "0x160300301000E0902A28102000400C000560601D02E01166380229B0E01008C6D18041032B70026E"))
|
||||
(property INITVAL_04
|
||||
(string "0x100460DAC00821916E01008661B807140111367002AD516CA5180601864309E6B054021420803C22"))
|
||||
(property INITVAL_03
|
||||
(string "0x160300301000E0902A28102000400C000560601D02E010E6380229B0E01008C6D18041032B70026E"))
|
||||
(property INITVAL_02
|
||||
(string "0x100460DAC00821916E01008661B807140111367002AD516CA5180501864309E5B04C020C20803C22"))
|
||||
(property INITVAL_01
|
||||
(string "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF"))
|
||||
(property INITVAL_00
|
||||
(string "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FECE0FA0506A181206C0CE66"))
|
||||
(property CSDECODE_B
|
||||
(string "0b111"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "SYNC"))
|
||||
(property REGMODE_B
|
||||
(string "NOREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "2"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "2")))
|
||||
(instance codeROM_0_0_1_2
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "SYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "codeROM.lpc"))
|
||||
(property MEM_INIT_FILE
|
||||
(string "rom-full-4k.mem"))
|
||||
(property INITVAL_1F
|
||||
(string "0x1E00C19C310A6C11801A010BF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF"))
|
||||
(property INITVAL_1E
|
||||
(string "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE08002F01A4241E251"))
|
||||
(property INITVAL_1D
|
||||
(string "0x1F8120A8F2048700F8011E0C107C0D05E130E00E180A800CA4028B00A8AC0361803C3011CAA1308F"))
|
||||
(property INITVAL_1C
|
||||
(string "0x050D2082AA128821B21B0DCA40DC6E08CB914C180CA9A1324D106790903416CA61922504A2105221"))
|
||||
(property INITVAL_1B
|
||||
(string "0x0CA960306A09000000080546A0D46A1188600CA601C4A1144C040461C46A0E8390125B0ACD503698"))
|
||||
(property INITVAL_1A
|
||||
(string "0x03E2C09615082A00E2A918C49048B70AA50012031EA090A8A9052020243302A550A8921922112295"))
|
||||
(property INITVAL_19
|
||||
(string "0x0029213CCC082B90A45D05AA802CE610690140A210A861FECA120A40DC24092910902C196C210889"))
|
||||
(property INITVAL_18
|
||||
(string "0x0D6B303018104481280F1840412A521241400A690B4FC0341A04042054AA03E09034E40CCA605062"))
|
||||
(property INITVAL_17
|
||||
(string "0x15426150A61406A15CC01320D16C430D0A60120A088E31C6E919E2C0A0561286010C031244504A55"))
|
||||
(property INITVAL_16
|
||||
(string "0x16C6814C490565602889024350A80102424094D30945B1C04A0CCFD0C06D14E491347506CF915A56"))
|
||||
(property INITVAL_15
|
||||
(string "0x04A4004A501BE01000900089018CE6194030406914886182B919A6F0B68117A6F0B69B130AD0DE5B"))
|
||||
(property INITVAL_14
|
||||
(string "0x1E0A2106C2094011000000000000000000000000000000000000000014AA082C70183B002C3160CA"))
|
||||
(property INITVAL_13
|
||||
(string "0x010AC11628002C31601107C0F040F30C8200303C0D03C028950AC4D19044114E807A10164831E038"))
|
||||
(property INITVAL_12
|
||||
(string "0x078F9008A9024550AA12178AA11E3C01E0E006D2160A2106E011EA2150A809E831D06F012860283C"))
|
||||
(property INITVAL_11
|
||||
(string "0x10C180A0F203061086C80D4F509061086C80C2B501E2D10CD4078B4088AA06A480DA4907C0F124D3"))
|
||||
(property INITVAL_10
|
||||
(string "0x1882818473092231C0F9188DA0146805A92094260940A0843E01E881FC401D6A2086C0164E80922C"))
|
||||
(property INITVAL_0F
|
||||
(string "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95"))
|
||||
(property INITVAL_0E
|
||||
(string "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000"))
|
||||
(property INITVAL_0D
|
||||
(string "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95"))
|
||||
(property INITVAL_0C
|
||||
(string "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000"))
|
||||
(property INITVAL_0B
|
||||
(string "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95"))
|
||||
(property INITVAL_0A
|
||||
(string "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000"))
|
||||
(property INITVAL_09
|
||||
(string "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95"))
|
||||
(property INITVAL_08
|
||||
(string "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000"))
|
||||
(property INITVAL_07
|
||||
(string "0x160320402201C0F07828148081B88807866140F914C0F05826022491C0F808A27106E10289E01E95"))
|
||||
(property INITVAL_06
|
||||
(string "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106CB0144207EC11609B0102804000"))
|
||||
(property INITVAL_05
|
||||
(string "0x160320402201C0F07828148081B88807866140F914C0F05826022491C0F808A27106E10289E01E95"))
|
||||
(property INITVAL_04
|
||||
(string "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106CB0144207EC11609B0102804000"))
|
||||
(property INITVAL_03
|
||||
(string "0x160320402201C0F07828148081B88807866140F914C0F05826022491C0F808A27106E10289E01E95"))
|
||||
(property INITVAL_02
|
||||
(string "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106CB0144207EC11609B0102804000"))
|
||||
(property INITVAL_01
|
||||
(string "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF"))
|
||||
(property INITVAL_00
|
||||
(string "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEC314034116201AA84082C9"))
|
||||
(property CSDECODE_B
|
||||
(string "0b111"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "SYNC"))
|
||||
(property REGMODE_B
|
||||
(string "NOREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "2"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "2")))
|
||||
(instance codeROM_0_0_2_1
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "SYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "codeROM.lpc"))
|
||||
(property MEM_INIT_FILE
|
||||
(string "rom-full-4k.mem"))
|
||||
(property INITVAL_1F
|
||||
(string "0x1E812150AE1FC8A178BF1D0BF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF"))
|
||||
(property INITVAL_1E
|
||||
(string "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE00082020304200010"))
|
||||
(property INITVAL_1D
|
||||
(string "0x0008008400084000808900214110830DC8C0FC180C282026D8140BA10CF009C21058B6004000C608"))
|
||||
(property INITVAL_1C
|
||||
(string "0x0809C140000DA010388D06C9206A35146701B4080408D0CCB2050C40208010098048240482004820"))
|
||||
(property INITVAL_1B
|
||||
(string "0x04008040A8140000002C1CC3C07C3E1AC860465807038070A3004531BC35110680B08D0464909E65"))
|
||||
(property INITVAL_1A
|
||||
(string "0x0408E1669101084108F61A41212080010841104800C5903091192C90964B04824046380482008460"))
|
||||
(property INITVAL_19
|
||||
(string "0x0240209C2C128F60844004029046DA12A9512C8C06410000201088107E4104C0415440010A202454"))
|
||||
(property INITVAL_18
|
||||
(string "0x0568B04A2D0027208E21008881221C138070483D01E0009E0A00600054A20448819AC1106D3080DB"))
|
||||
(property INITVAL_17
|
||||
(string "0x000230D0930CE3E02206040321808413A080402815A600A0530060E0C2420B0BD012300BE2404C46"))
|
||||
(property INITVAL_16
|
||||
(string "0x092BD030740409200AD10A8C9130C90AE450A4DC1106103230010700420209654112081007003A19"))
|
||||
(property INITVAL_15
|
||||
(string "0x04C320486705E000020000022126581C68809434134530C8D60203801C081843011A4D0C4E00700E"))
|
||||
(property INITVAL_14
|
||||
(string "0x050B4050A202088100000000000000000000000000000000000000005001140C301831140C3034D0"))
|
||||
(property INITVAL_13
|
||||
(string "0x15A0E0408E0C0C30140000E43042A400A0301A0C01A0C12099032B212000002ED018B4018D01B03D"))
|
||||
(property INITVAL_12
|
||||
(string "0x01830120960944608C02064A80D8FC1060D1E0CF03084040741061810C80102D01C08C0600808E04"))
|
||||
(property INITVAL_11
|
||||
(string "0x03021038100C0840E04114046020840E04110401182020100700808000A010C101007600E4308020"))
|
||||
(property INITVAL_10
|
||||
(string "0x090A1008A4002C00E8161CE2110086004180C2980C281168070821C03C20180F4060F8060CA0408A"))
|
||||
(property INITVAL_0F
|
||||
(string "0x0603B0C2A9076CE0726D00A2304A0D0701A1E8E01264E040C0000510E8E0002411A68000A3709C66"))
|
||||
(property INITVAL_0E
|
||||
(string "0x0200108AD31000500E4E000141BA39108000A4741C826110041A68C02088106881844F048F30042A"))
|
||||
(property INITVAL_0D
|
||||
(string "0x0603B0C2A9056CA0526D00A2304A0D0501A1E8A01264A040C0000510E8A0002411A48000A3709466"))
|
||||
(property INITVAL_0C
|
||||
(string "0x0200108AD21000500E4A000141BA29108000A47414826110041A48C02088106881844F048F30042A"))
|
||||
(property INITVAL_0B
|
||||
(string "0x0603B0C2A9036C60326D00A2304A0D0301A1E86012646040C0000510E860002411A28000A3708C66"))
|
||||
(property INITVAL_0A
|
||||
(string "0x0200108AD11000500E46000141BA19108000A4740C826110041A28C02088106881844F048F30042A"))
|
||||
(property INITVAL_09
|
||||
(string "0x0603B0C2A9016C20126D00A2304A0D0101A1E82012642040C0000510E820002411A08000A3708466"))
|
||||
(property INITVAL_08
|
||||
(string "0x0200108AD01000500E42000141BA09108000A47404826110041A08C02088106881844F048F30042A"))
|
||||
(property INITVAL_07
|
||||
(string "0x0603B0C2A9076CE0726D00A2304A0D0701A1E8E01264E040C0000510E8E0002411A68000A3709C66"))
|
||||
(property INITVAL_06
|
||||
(string "0x0200108AD31000500E4E000141BA39108000A4741C826110041A68C02088106881844F048F30042A"))
|
||||
(property INITVAL_05
|
||||
(string "0x0603B0C2A9056CA0526D00A2304A0D0501A1E8A01264A040C0000510E8A0002411A48000A3709466"))
|
||||
(property INITVAL_04
|
||||
(string "0x0200108AD21000500E4A000141BA29108000A47414826110041A48C02088106881844F048F30042A"))
|
||||
(property INITVAL_03
|
||||
(string "0x0603B0C2A9036C60326D00A2304A0D0301A1E86012646040C0000510E860002411A28000A3708C66"))
|
||||
(property INITVAL_02
|
||||
(string "0x0200108AD11000500E46000141BA19108000A4740C826110041A28C02088106881844F048F30042A"))
|
||||
(property INITVAL_01
|
||||
(string "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF"))
|
||||
(property INITVAL_00
|
||||
(string "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FECE158AA150BA15EBE176B8"))
|
||||
(property CSDECODE_B
|
||||
(string "0b111"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "SYNC"))
|
||||
(property REGMODE_B
|
||||
(string "NOREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "2"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "2")))
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance codeROM_0_0_3_0
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "SYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "codeROM.lpc"))
|
||||
(property MEM_INIT_FILE
|
||||
(string "rom-full-4k.mem"))
|
||||
(property INITVAL_1F
|
||||
(string "0x1E0FE17EAF1FEFB1FEAA156BF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF"))
|
||||
(property INITVAL_1E
|
||||
(string "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE00086FE1F6FE1E6FF"))
|
||||
(property INITVAL_1D
|
||||
(string "0x1FEBF1FCF31FCFF1FEBB1E6FF176C71FE0F1C4330463206698110B0044E419E2305C3800C000C608"))
|
||||
(property INITVAL_1C
|
||||
(string "0x1E08B18C000D8861908E0349903439122B41D46512C4E0CCF61A617058181309F00CA604C6604C26"))
|
||||
(property INITVAL_1B
|
||||
(string "0x04C590CAA718C00110101A419034381C6D90429A06633066220E40111C39130C8182860C69800C63"))
|
||||
(property INITVAL_1A
|
||||
(string "0x0DA381DC191128D100660642D034991328C110CF0AE2512885152881983E0CC660CCD300CA60CC66"))
|
||||
(property INITVAL_19
|
||||
(string "0x06C620C8F9100660CC6604C2E0E698158AC1588F06C331CE48130B6076E604CBD110EF096C2066F7"))
|
||||
(property INITVAL_18
|
||||
(string "0x0523E0CE6F10C620CC2E090D81329B1366604C1911CF400C6E02431000000DE0818AD31669B06A89"))
|
||||
(property INITVAL_17
|
||||
(string "0x03211130431201A17A490CE27032C909ED004C2913E0E0DCAE0F4E90E4610324C128011302602C65"))
|
||||
(property INITVAL_16
|
||||
(string "0x0324C12866052990CAF90A8D91B8CD0AEE50BE8D1126C0DE0D12EE60643507C2410298136E61F294"))
|
||||
(property INITVAL_15
|
||||
(string "0x04E3314C630DA0000000000411E6DB01E0816838132C11F8F604C1911CC00CC3910C8E0C4A60328E"))
|
||||
(property INITVAL_14
|
||||
(string "0x1E4BB10ECA05C08110881108810482104821002A1002A10000054AA1300113CBA1D6AC03CBA182FF"))
|
||||
(property INITVAL_13
|
||||
(string "0x13EBC0583C0DCBA182651D63A142791EC92098E9118E813059128361929608C4C1D0BF1E4CE116AC"))
|
||||
(property INITVAL_12
|
||||
(string "0x1D6AC036460C4660CC6218AFF086FF0F4E819C881808E05CBD074F317885174CE142B506ED00CCEA"))
|
||||
(property INITVAL_11
|
||||
(string "0x03641136A80DA060DCA112ED707A060DCA116819174861A0661D4191209712E3D00C661D63A0D06E"))
|
||||
(property INITVAL_10
|
||||
(string "0x130BC09AB91C2BE176861C66F042BC10CF319E1B19E21164EB170DB15C2E16A3E01C8B15CB80583C"))
|
||||
(property INITVAL_0F
|
||||
(string "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67"))
|
||||
(property INITVAL_0E
|
||||
(string "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422"))
|
||||
(property INITVAL_0D
|
||||
(string "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67"))
|
||||
(property INITVAL_0C
|
||||
(string "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422"))
|
||||
(property INITVAL_0B
|
||||
(string "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67"))
|
||||
(property INITVAL_0A
|
||||
(string "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422"))
|
||||
(property INITVAL_09
|
||||
(string "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67"))
|
||||
(property INITVAL_08
|
||||
(string "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422"))
|
||||
(property INITVAL_07
|
||||
(string "0x04034046241D63A1D0EF1EA230C6FC1D250066A60B63A188DF0CA6D0E6AD12AB519CB60ACC707467"))
|
||||
(property INITVAL_06
|
||||
(string "0x07A9516ACE16C561AE3A1B25B038E919E650D87314C061025619CB906A8B1BE881DC050408206422"))
|
||||
(property INITVAL_05
|
||||
(string "0x04034046241D63A1D0EF1EA230C6FC1D250066A60B63A188DF0CA6D0E6AD12AB519CB60ACC707467"))
|
||||
(property INITVAL_04
|
||||
(string "0x07A9516ACE16C561AE3A1B25B038E919E650D87314C061025619CB906A8B1BE881DC050408206422"))
|
||||
(property INITVAL_03
|
||||
(string "0x04034046241D63A1D0EF1EA230C6FC1D250066A60B63A188DF0CA6D0E6AD12AB519CB60ACC707467"))
|
||||
(property INITVAL_02
|
||||
(string "0x07A9516ACE16C561AE3A1B25B038E919E650D87314C061025619CB906A8B1BE881DC050408206422"))
|
||||
(property INITVAL_01
|
||||
(string "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF"))
|
||||
(property INITVAL_00
|
||||
(string "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FECF1FEBF1FEBE1FEFE1FEFF"))
|
||||
(property CSDECODE_B
|
||||
(string "0b111"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "SYNC"))
|
||||
(property REGMODE_B
|
||||
(string "NOREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "2"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "2")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef OCEB (instanceRef codeROM_0_0_0_3))
|
||||
(portRef CEB (instanceRef codeROM_0_0_0_3))
|
||||
(portRef OCEB (instanceRef codeROM_0_0_1_2))
|
||||
(portRef CEB (instanceRef codeROM_0_0_1_2))
|
||||
(portRef OCEB (instanceRef codeROM_0_0_2_1))
|
||||
(portRef CEB (instanceRef codeROM_0_0_2_1))
|
||||
(portRef OCEB (instanceRef codeROM_0_0_3_0))
|
||||
(portRef CEB (instanceRef codeROM_0_0_3_0))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef CSB2 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef CSA2 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef CSB1 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef CSA1 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef CSB0 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef CSA0 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef RSTB (instanceRef codeROM_0_0_0_3))
|
||||
(portRef WEB (instanceRef codeROM_0_0_0_3))
|
||||
(portRef WEA (instanceRef codeROM_0_0_0_3))
|
||||
(portRef CLKB (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB12 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB11 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB10 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB9 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB8 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB7 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB6 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB5 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB4 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB3 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB2 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB1 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADB0 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA0 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIB8 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIA8 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIB7 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIA7 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIB6 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIA6 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIB5 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIA5 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIB4 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIA4 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIB3 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIA3 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIB2 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIA2 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIB1 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIA1 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIB0 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef DIA0 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef CSB2 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef CSA2 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef CSB1 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef CSA1 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef CSB0 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef CSA0 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef RSTB (instanceRef codeROM_0_0_1_2))
|
||||
(portRef WEB (instanceRef codeROM_0_0_1_2))
|
||||
(portRef WEA (instanceRef codeROM_0_0_1_2))
|
||||
(portRef CLKB (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB12 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB11 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB10 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB9 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB8 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB7 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB6 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB5 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB4 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB3 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB2 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB1 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADB0 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA0 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIB8 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIA8 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIB7 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIA7 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIB6 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIA6 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIB5 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIA5 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIB4 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIA4 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIB3 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIA3 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIB2 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIA2 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIB1 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIA1 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIB0 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef DIA0 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef CSB2 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef CSA2 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef CSB1 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef CSA1 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef CSB0 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef CSA0 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef RSTB (instanceRef codeROM_0_0_2_1))
|
||||
(portRef WEB (instanceRef codeROM_0_0_2_1))
|
||||
(portRef WEA (instanceRef codeROM_0_0_2_1))
|
||||
(portRef CLKB (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB12 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB11 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB10 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB9 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB8 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB7 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB6 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB5 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB4 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB3 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB2 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB1 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADB0 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA0 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIB8 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIA8 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIB7 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIA7 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIB6 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIA6 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIB5 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIA5 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIB4 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIA4 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIB3 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIA3 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIB2 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIA2 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIB1 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIA1 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIB0 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef DIA0 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef CSB2 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef CSA2 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef CSB1 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef CSA1 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef CSB0 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef CSA0 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef RSTB (instanceRef codeROM_0_0_3_0))
|
||||
(portRef WEB (instanceRef codeROM_0_0_3_0))
|
||||
(portRef WEA (instanceRef codeROM_0_0_3_0))
|
||||
(portRef CLKB (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB12 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB11 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB10 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB9 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB8 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB7 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB6 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB5 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB4 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB3 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB2 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB1 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADB0 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef ADA0 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIB8 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIA8 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIB7 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIA7 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIB6 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIA6 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIB5 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIA5 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIB4 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIA4 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIB3 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIA3 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIB2 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIA2 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIB1 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIA1 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIB0 (instanceRef codeROM_0_0_3_0))
|
||||
(portRef DIA0 (instanceRef codeROM_0_0_3_0))))
|
||||
(net dataout7
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef DOA1 (instanceRef codeROM_0_0_3_0))))
|
||||
(net dataout6
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef DOA0 (instanceRef codeROM_0_0_3_0))))
|
||||
(net dataout5
|
||||
(joined
|
||||
(portRef (member Q 2))
|
||||
(portRef DOA1 (instanceRef codeROM_0_0_2_1))))
|
||||
(net dataout4
|
||||
(joined
|
||||
(portRef (member Q 3))
|
||||
(portRef DOA0 (instanceRef codeROM_0_0_2_1))))
|
||||
(net dataout3
|
||||
(joined
|
||||
(portRef (member Q 4))
|
||||
(portRef DOA1 (instanceRef codeROM_0_0_1_2))))
|
||||
(net dataout2
|
||||
(joined
|
||||
(portRef (member Q 5))
|
||||
(portRef DOA0 (instanceRef codeROM_0_0_1_2))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 6))
|
||||
(portRef DOA1 (instanceRef codeROM_0_0_0_3))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 7))
|
||||
(portRef DOA0 (instanceRef codeROM_0_0_0_3))))
|
||||
(net Reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef RSTA (instanceRef codeROM_0_0_0_3))
|
||||
(portRef RSTA (instanceRef codeROM_0_0_1_2))
|
||||
(portRef RSTA (instanceRef codeROM_0_0_2_1))
|
||||
(portRef RSTA (instanceRef codeROM_0_0_3_0))))
|
||||
(net RdClockEn
|
||||
(joined
|
||||
(portRef OutClockEn)
|
||||
(portRef OCEA (instanceRef codeROM_0_0_0_3))
|
||||
(portRef CEA (instanceRef codeROM_0_0_0_3))
|
||||
(portRef OCEA (instanceRef codeROM_0_0_1_2))
|
||||
(portRef CEA (instanceRef codeROM_0_0_1_2))
|
||||
(portRef OCEA (instanceRef codeROM_0_0_2_1))
|
||||
(portRef CEA (instanceRef codeROM_0_0_2_1))
|
||||
(portRef OCEA (instanceRef codeROM_0_0_3_0))
|
||||
(portRef CEA (instanceRef codeROM_0_0_3_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef OutClock)
|
||||
(portRef CLKA (instanceRef codeROM_0_0_0_3))
|
||||
(portRef CLKA (instanceRef codeROM_0_0_1_2))
|
||||
(portRef CLKA (instanceRef codeROM_0_0_2_1))
|
||||
(portRef CLKA (instanceRef codeROM_0_0_3_0))))
|
||||
(net raddr11
|
||||
(joined
|
||||
(portRef (member Address 0))
|
||||
(portRef ADA12 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA12 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA12 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA12 (instanceRef codeROM_0_0_3_0))))
|
||||
(net raddr10
|
||||
(joined
|
||||
(portRef (member Address 1))
|
||||
(portRef ADA11 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA11 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA11 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA11 (instanceRef codeROM_0_0_3_0))))
|
||||
(net raddr9
|
||||
(joined
|
||||
(portRef (member Address 2))
|
||||
(portRef ADA10 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA10 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA10 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA10 (instanceRef codeROM_0_0_3_0))))
|
||||
(net raddr8
|
||||
(joined
|
||||
(portRef (member Address 3))
|
||||
(portRef ADA9 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA9 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA9 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA9 (instanceRef codeROM_0_0_3_0))))
|
||||
(net raddr7
|
||||
(joined
|
||||
(portRef (member Address 4))
|
||||
(portRef ADA8 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA8 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA8 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA8 (instanceRef codeROM_0_0_3_0))))
|
||||
(net raddr6
|
||||
(joined
|
||||
(portRef (member Address 5))
|
||||
(portRef ADA7 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA7 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA7 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA7 (instanceRef codeROM_0_0_3_0))))
|
||||
(net raddr5
|
||||
(joined
|
||||
(portRef (member Address 6))
|
||||
(portRef ADA6 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA6 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA6 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA6 (instanceRef codeROM_0_0_3_0))))
|
||||
(net raddr4
|
||||
(joined
|
||||
(portRef (member Address 7))
|
||||
(portRef ADA5 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA5 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA5 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA5 (instanceRef codeROM_0_0_3_0))))
|
||||
(net raddr3
|
||||
(joined
|
||||
(portRef (member Address 8))
|
||||
(portRef ADA4 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA4 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA4 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA4 (instanceRef codeROM_0_0_3_0))))
|
||||
(net raddr2
|
||||
(joined
|
||||
(portRef (member Address 9))
|
||||
(portRef ADA3 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA3 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA3 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA3 (instanceRef codeROM_0_0_3_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member Address 10))
|
||||
(portRef ADA2 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA2 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA2 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA2 (instanceRef codeROM_0_0_3_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member Address 11))
|
||||
(portRef ADA1 (instanceRef codeROM_0_0_0_3))
|
||||
(portRef ADA1 (instanceRef codeROM_0_0_1_2))
|
||||
(portRef ADA1 (instanceRef codeROM_0_0_2_1))
|
||||
(portRef ADA1 (instanceRef codeROM_0_0_3_0))))))))
|
||||
(design codeROM
|
||||
(cellRef codeROM
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
11
lattice/codeROM.ipx
Normal file
11
lattice/codeROM.ipx
Normal file
@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="codeROM" module="codeROM" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 01 30 17:35:17.438" version="5.4" type="Module" synthesis="lse" source_format="Verilog HDL">
|
||||
<Package>
|
||||
<File name="" type="" modified="2018 01 30 17:35:17.297"/>
|
||||
<File name="c:/users/chamberlin/documents/liron/rom-full-4k.mem" type="mem" modified="2018 01 30 17:34:47.640"/>
|
||||
<File name="codeROM.lpc" type="lpc" modified="2018 01 30 17:35:12.008"/>
|
||||
<File name="codeROM.v" type="top_level_verilog" modified="2018 01 30 17:35:12.086"/>
|
||||
<File name="codeROM_tmpl.v" type="template_verilog" modified="2018 01 30 17:35:12.086"/>
|
||||
<File name="tb_codeROM_tmpl.v" type="testbench_verilog" modified="2018 01 30 17:35:12.102"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
||||
51
lattice/codeROM.lpc
Normal file
51
lattice/codeROM.lpc
Normal file
@ -0,0 +1,51 @@
|
||||
[Device]
|
||||
Family=machxo2
|
||||
PartType=LCMXO2-1200HC
|
||||
PartName=LCMXO2-1200HC-4TG100C
|
||||
SpeedGrade=4
|
||||
Package=TQFP100
|
||||
OperatingCondition=COM
|
||||
Status=S
|
||||
|
||||
[IP]
|
||||
VendorName=Lattice Semiconductor Corporation
|
||||
CoreType=LPM
|
||||
CoreStatus=Demo
|
||||
CoreName=ROM
|
||||
CoreRevision=5.4
|
||||
ModuleName=codeROM
|
||||
SourceFormat=Verilog HDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=01/30/2018
|
||||
Time=17:35:12
|
||||
|
||||
[Parameters]
|
||||
Verilog=1
|
||||
VHDL=0
|
||||
EDIF=1
|
||||
Destination=Synplicity
|
||||
Expression=BusA(0 to 7)
|
||||
Order=Big Endian [MSB:LSB]
|
||||
IO=0
|
||||
Address=4096
|
||||
Data=8
|
||||
enByte=0
|
||||
ByteSize=9
|
||||
OutputEn=1
|
||||
ClockEn=0
|
||||
Optimization=Area
|
||||
Reset=Sync
|
||||
Reset1=Sync
|
||||
Init=0
|
||||
MemFile=c:/users/chamberlin/documents/liron/rom-full-4k.mem
|
||||
MemFormat=hex
|
||||
EnECC=0
|
||||
Pipeline=0
|
||||
Write=Normal
|
||||
init_data=0
|
||||
|
||||
[FilesGenerated]
|
||||
c:/users/chamberlin/documents/liron/rom-full-4k.mem=mem
|
||||
|
||||
[Command]
|
||||
cmd_line= -w -n codeROM -lang verilog -synth lse -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-1200HC -addr_width 12 -data_width 8 -num_words 4096 -outdata REGISTERED -cascade 11 -resetmode SYNC -sync_reset -memfile "c:/users/chamberlin/documents/liron/rom-full-4k.mem" -memformat hex
|
||||
23
lattice/codeROM.naf
Normal file
23
lattice/codeROM.naf
Normal file
@ -0,0 +1,23 @@
|
||||
Address[11] i
|
||||
Address[10] i
|
||||
Address[9] i
|
||||
Address[8] i
|
||||
Address[7] i
|
||||
Address[6] i
|
||||
Address[5] i
|
||||
Address[4] i
|
||||
Address[3] i
|
||||
Address[2] i
|
||||
Address[1] i
|
||||
Address[0] i
|
||||
OutClock i
|
||||
OutClockEn i
|
||||
Reset i
|
||||
Q[7] o
|
||||
Q[6] o
|
||||
Q[5] o
|
||||
Q[4] o
|
||||
Q[3] o
|
||||
Q[2] o
|
||||
Q[1] o
|
||||
Q[0] o
|
||||
1
lattice/codeROM.sort
Normal file
1
lattice/codeROM.sort
Normal file
@ -0,0 +1 @@
|
||||
codeROM.v
|
||||
29
lattice/codeROM.srp
Normal file
29
lattice/codeROM.srp
Normal file
@ -0,0 +1,29 @@
|
||||
SCUBA, Version Diamond (64-bit) 3.9.0.99.2
|
||||
Tue Jan 30 17:35:12 2018
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Issued command : C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n codeROM -lang verilog -synth lse -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-1200HC -addr_width 12 -data_width 8 -num_words 4096 -outdata REGISTERED -cascade 11 -resetmode SYNC -sync_reset -memfile c:/users/chamberlin/documents/liron/rom-full-4k.mem -memformat hex
|
||||
Circuit name : codeROM
|
||||
Module type : EBR_ROM
|
||||
Module Version : 5.4
|
||||
Ports :
|
||||
Inputs : Address[11:0], OutClock, OutClockEn, Reset
|
||||
Outputs : Q[7:0]
|
||||
I/O buffer : not inserted
|
||||
Memory file : c:/users/chamberlin/documents/liron/rom-full-4k.mem
|
||||
EDIF output : codeROM.edn
|
||||
Verilog output : codeROM.v
|
||||
Verilog template : codeROM_tmpl.v
|
||||
Verilog testbench: tb_codeROM_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : codeROM.srp
|
||||
Element Usage :
|
||||
DP8KC : 4
|
||||
Estimated Resource Usage:
|
||||
EBR : 4
|
||||
BIN
lattice/codeROM.sym
Normal file
BIN
lattice/codeROM.sym
Normal file
Binary file not shown.
295
lattice/codeROM.v
Normal file
295
lattice/codeROM.v
Normal file
@ -0,0 +1,295 @@
|
||||
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.9.0.99.2 */
|
||||
/* Module Version: 5.4 */
|
||||
/* C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n codeROM -lang verilog -synth lse -bus_exp 7 -bb -arch xo2c00 -type bram -wp 00 -rp 1100 -addr_width 12 -data_width 8 -num_rows 4096 -outdata REGISTERED -cascade 11 -resetmode SYNC -sync_reset -memfile c:/users/chamberlin/documents/liron/rom-full-4k.mem -memformat hex */
|
||||
/* Tue Jan 30 17:35:12 2018 */
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
module codeROM (Address, OutClock, OutClockEn, Reset, Q)/* synthesis NGD_DRC_MASK=1 */;
|
||||
input wire [11:0] Address;
|
||||
input wire OutClock;
|
||||
input wire OutClockEn;
|
||||
input wire Reset;
|
||||
output wire [7:0] Q;
|
||||
|
||||
wire scuba_vhi;
|
||||
wire scuba_vlo;
|
||||
|
||||
defparam codeROM_0_0_0_3.INIT_DATA = "STATIC" ;
|
||||
defparam codeROM_0_0_0_3.ASYNC_RESET_RELEASE = "SYNC" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_1F = "0x1E07417209022F10021108E3F1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE00020F8186D01C04D" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_1D = "0x15E1D120E31A04907C101C4E907A0100A220348D1501A10040108480DCA3060680522C024AA0301B" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_1C = "0x0409311AAA038091CA2100C48108441187602A9309231012450840A080240AA6A19A150229D13219" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_1B = "0x0B4241A461086D51BEC10008408C44000040484209A4109AE8024401440402C3400A611A8640022C" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_1A = "0x1363C0121809242080101920B06C5614E8210C2118CC008C40090500061D14A51030A219A1D15C99" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_19 = "0x1121113A76160120325902A5C198800864108242194C1024C00884118E011848212E2500A41108C8" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_18 = "0x0265D148D0012101220706429092441089108A840A233002E2130091B0A21AA05062DC0B04204078" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_17 = "0x0101809644088041123019C81006A0090BA1DC23080D20864E00A041D09D04A88030410C88D02A91" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_16 = "0x00A800341502014022C008A111341208A09036221085F0108B0ECD11B0D104A4606A5510C1D12C44" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_15 = "0x03C0403A5C15E241244902040000890881302005080C410022012C50C203032850A2010581918A61" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_14 = "0x0A06210241094010800000000000000000000000000000000000000014A8084410481B0064D16048" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_13 = "0x1101C11610002451601102E0002420002180D8050D80406856088C10804409ADC00C030C0C00C05C" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_12 = "0x048590684112AD5122110A0A919ECF00204004601624010250082400A09808AC00484419C1A1B214" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_11 = "0x0E86A0C851122A512245080CE082A11224408CB608A1D03499028650AC4019C4114A9402E0008251" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_10 = "0x0A82706670008410E0251881400E500226110835108060C017004441BA410A800184600A67419228" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_0F = "0x160300301000E0902A28102000400C000560601D02E011E6380229B0E01008C6D18041032B70026E" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_0E = "0x100460DAC00821916E01008661B807140111367002AD516CA5180701864309E7B05C021C20803C22" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_0D = "0x160300301000E0902A28102000400C000560601D02E01166380229B0E01008C6D18041032B70026E" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_0C = "0x100460DAC00821916E01008661B807140111367002AD516CA5180601864309E6B054021420803C22" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_0B = "0x160300301000E0902A28102000400C000560601D02E010E6380229B0E01008C6D18041032B70026E" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_0A = "0x100460DAC00821916E01008661B807140111367002AD516CA5180501864309E5B04C020C20803C22" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_09 = "0x160300301000E0902A28102000400C000560601D02E01066380229B0E01008C6D18041032B70026E" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_08 = "0x100460DAC00821916E01008661B807140111367002AD516CA5180401864309E4B044020420803C22" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_07 = "0x160300301000E0902A28102000400C000560601D02E011E6380229B0E01008C6D18041032B70026E" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_06 = "0x100460DAC00821916E01008661B807140111367002AD516CA5180701864309E7B05C021C20803C22" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_05 = "0x160300301000E0902A28102000400C000560601D02E01166380229B0E01008C6D18041032B70026E" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_04 = "0x100460DAC00821916E01008661B807140111367002AD516CA5180601864309E6B054021420803C22" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_03 = "0x160300301000E0902A28102000400C000560601D02E010E6380229B0E01008C6D18041032B70026E" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_02 = "0x100460DAC00821916E01008661B807140111367002AD516CA5180501864309E5B04C020C20803C22" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_01 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ;
|
||||
defparam codeROM_0_0_0_3.INITVAL_00 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FECE0FA0506A181206C0CE66" ;
|
||||
defparam codeROM_0_0_0_3.CSDECODE_B = "0b111" ;
|
||||
defparam codeROM_0_0_0_3.CSDECODE_A = "0b000" ;
|
||||
defparam codeROM_0_0_0_3.WRITEMODE_B = "NORMAL" ;
|
||||
defparam codeROM_0_0_0_3.WRITEMODE_A = "NORMAL" ;
|
||||
defparam codeROM_0_0_0_3.GSR = "ENABLED" ;
|
||||
defparam codeROM_0_0_0_3.RESETMODE = "SYNC" ;
|
||||
defparam codeROM_0_0_0_3.REGMODE_B = "NOREG" ;
|
||||
defparam codeROM_0_0_0_3.REGMODE_A = "OUTREG" ;
|
||||
defparam codeROM_0_0_0_3.DATA_WIDTH_B = 2 ;
|
||||
defparam codeROM_0_0_0_3.DATA_WIDTH_A = 2 ;
|
||||
DP8KC codeROM_0_0_0_3 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
|
||||
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
|
||||
.DIA1(scuba_vlo), .DIA0(scuba_vlo), .ADA12(Address[11]), .ADA11(Address[10]),
|
||||
.ADA10(Address[9]), .ADA9(Address[8]), .ADA8(Address[7]), .ADA7(Address[6]),
|
||||
.ADA6(Address[5]), .ADA5(Address[4]), .ADA4(Address[3]), .ADA3(Address[2]),
|
||||
.ADA2(Address[1]), .ADA1(Address[0]), .ADA0(scuba_vlo), .CEA(OutClockEn),
|
||||
.OCEA(OutClockEn), .CLKA(OutClock), .WEA(scuba_vlo), .CSA2(scuba_vlo),
|
||||
.CSA1(scuba_vlo), .CSA0(scuba_vlo), .RSTA(Reset), .DIB8(scuba_vlo),
|
||||
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
|
||||
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
|
||||
.ADB12(scuba_vlo), .ADB11(scuba_vlo), .ADB10(scuba_vlo), .ADB9(scuba_vlo),
|
||||
.ADB8(scuba_vlo), .ADB7(scuba_vlo), .ADB6(scuba_vlo), .ADB5(scuba_vlo),
|
||||
.ADB4(scuba_vlo), .ADB3(scuba_vlo), .ADB2(scuba_vlo), .ADB1(scuba_vlo),
|
||||
.ADB0(scuba_vlo), .CEB(scuba_vhi), .OCEB(scuba_vhi), .CLKB(scuba_vlo),
|
||||
.WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo),
|
||||
.RSTB(scuba_vlo), .DOA8(), .DOA7(), .DOA6(), .DOA5(), .DOA4(), .DOA3(),
|
||||
.DOA2(), .DOA1(Q[1]), .DOA0(Q[0]), .DOB8(), .DOB7(), .DOB6(), .DOB5(),
|
||||
.DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0())
|
||||
/* synthesis MEM_LPC_FILE="codeROM.lpc" */
|
||||
/* synthesis MEM_INIT_FILE="rom-full-4k.mem" */;
|
||||
|
||||
defparam codeROM_0_0_1_2.INIT_DATA = "STATIC" ;
|
||||
defparam codeROM_0_0_1_2.ASYNC_RESET_RELEASE = "SYNC" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_1F = "0x1E00C19C310A6C11801A010BF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE08002F01A4241E251" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_1D = "0x1F8120A8F2048700F8011E0C107C0D05E130E00E180A800CA4028B00A8AC0361803C3011CAA1308F" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_1C = "0x050D2082AA128821B21B0DCA40DC6E08CB914C180CA9A1324D106790903416CA61922504A2105221" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_1B = "0x0CA960306A09000000080546A0D46A1188600CA601C4A1144C040461C46A0E8390125B0ACD503698" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_1A = "0x03E2C09615082A00E2A918C49048B70AA50012031EA090A8A9052020243302A550A8921922112295" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_19 = "0x0029213CCC082B90A45D05AA802CE610690140A210A861FECA120A40DC24092910902C196C210889" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_18 = "0x0D6B303018104481280F1840412A521241400A690B4FC0341A04042054AA03E09034E40CCA605062" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_17 = "0x15426150A61406A15CC01320D16C430D0A60120A088E31C6E919E2C0A0561286010C031244504A55" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_16 = "0x16C6814C490565602889024350A80102424094D30945B1C04A0CCFD0C06D14E491347506CF915A56" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_15 = "0x04A4004A501BE01000900089018CE6194030406914886182B919A6F0B68117A6F0B69B130AD0DE5B" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_14 = "0x1E0A2106C2094011000000000000000000000000000000000000000014AA082C70183B002C3160CA" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_13 = "0x010AC11628002C31601107C0F040F30C8200303C0D03C028950AC4D19044114E807A10164831E038" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_12 = "0x078F9008A9024550AA12178AA11E3C01E0E006D2160A2106E011EA2150A809E831D06F012860283C" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_11 = "0x10C180A0F203061086C80D4F509061086C80C2B501E2D10CD4078B4088AA06A480DA4907C0F124D3" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_10 = "0x1882818473092231C0F9188DA0146805A92094260940A0843E01E881FC401D6A2086C0164E80922C" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_0F = "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_0E = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_0D = "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_0C = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_0B = "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_0A = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_09 = "0x160320402201C0F07828148081B88807866140F914C0F0D826022491C0F808A27106E10289E01E95" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_08 = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106DB0144207ED11689B0902804000" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_07 = "0x160320402201C0F07828148081B88807866140F914C0F05826022491C0F808A27106E10289E01E95" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_06 = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106CB0144207EC11609B0102804000" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_05 = "0x160320402201C0F07828148081B88807866140F914C0F05826022491C0F808A27106E10289E01E95" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_04 = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106CB0144207EC11609B0102804000" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_03 = "0x160320402201C0F07828148081B88807866140F914C0F05826022491C0F808A27106E10289E01E95" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_02 = "0x0104504E831C21413C0F108520F03D08411092E01F269174A9106CB0144207EC11609B0102804000" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_01 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ;
|
||||
defparam codeROM_0_0_1_2.INITVAL_00 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEC314034116201AA84082C9" ;
|
||||
defparam codeROM_0_0_1_2.CSDECODE_B = "0b111" ;
|
||||
defparam codeROM_0_0_1_2.CSDECODE_A = "0b000" ;
|
||||
defparam codeROM_0_0_1_2.WRITEMODE_B = "NORMAL" ;
|
||||
defparam codeROM_0_0_1_2.WRITEMODE_A = "NORMAL" ;
|
||||
defparam codeROM_0_0_1_2.GSR = "ENABLED" ;
|
||||
defparam codeROM_0_0_1_2.RESETMODE = "SYNC" ;
|
||||
defparam codeROM_0_0_1_2.REGMODE_B = "NOREG" ;
|
||||
defparam codeROM_0_0_1_2.REGMODE_A = "OUTREG" ;
|
||||
defparam codeROM_0_0_1_2.DATA_WIDTH_B = 2 ;
|
||||
defparam codeROM_0_0_1_2.DATA_WIDTH_A = 2 ;
|
||||
DP8KC codeROM_0_0_1_2 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
|
||||
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
|
||||
.DIA1(scuba_vlo), .DIA0(scuba_vlo), .ADA12(Address[11]), .ADA11(Address[10]),
|
||||
.ADA10(Address[9]), .ADA9(Address[8]), .ADA8(Address[7]), .ADA7(Address[6]),
|
||||
.ADA6(Address[5]), .ADA5(Address[4]), .ADA4(Address[3]), .ADA3(Address[2]),
|
||||
.ADA2(Address[1]), .ADA1(Address[0]), .ADA0(scuba_vlo), .CEA(OutClockEn),
|
||||
.OCEA(OutClockEn), .CLKA(OutClock), .WEA(scuba_vlo), .CSA2(scuba_vlo),
|
||||
.CSA1(scuba_vlo), .CSA0(scuba_vlo), .RSTA(Reset), .DIB8(scuba_vlo),
|
||||
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
|
||||
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
|
||||
.ADB12(scuba_vlo), .ADB11(scuba_vlo), .ADB10(scuba_vlo), .ADB9(scuba_vlo),
|
||||
.ADB8(scuba_vlo), .ADB7(scuba_vlo), .ADB6(scuba_vlo), .ADB5(scuba_vlo),
|
||||
.ADB4(scuba_vlo), .ADB3(scuba_vlo), .ADB2(scuba_vlo), .ADB1(scuba_vlo),
|
||||
.ADB0(scuba_vlo), .CEB(scuba_vhi), .OCEB(scuba_vhi), .CLKB(scuba_vlo),
|
||||
.WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo),
|
||||
.RSTB(scuba_vlo), .DOA8(), .DOA7(), .DOA6(), .DOA5(), .DOA4(), .DOA3(),
|
||||
.DOA2(), .DOA1(Q[3]), .DOA0(Q[2]), .DOB8(), .DOB7(), .DOB6(), .DOB5(),
|
||||
.DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0())
|
||||
/* synthesis MEM_LPC_FILE="codeROM.lpc" */
|
||||
/* synthesis MEM_INIT_FILE="rom-full-4k.mem" */;
|
||||
|
||||
defparam codeROM_0_0_2_1.INIT_DATA = "STATIC" ;
|
||||
defparam codeROM_0_0_2_1.ASYNC_RESET_RELEASE = "SYNC" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_1F = "0x1E812150AE1FC8A178BF1D0BF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE00082020304200010" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_1D = "0x0008008400084000808900214110830DC8C0FC180C282026D8140BA10CF009C21058B6004000C608" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_1C = "0x0809C140000DA010388D06C9206A35146701B4080408D0CCB2050C40208010098048240482004820" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_1B = "0x04008040A8140000002C1CC3C07C3E1AC860465807038070A3004531BC35110680B08D0464909E65" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_1A = "0x0408E1669101084108F61A41212080010841104800C5903091192C90964B04824046380482008460" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_19 = "0x0240209C2C128F60844004029046DA12A9512C8C06410000201088107E4104C0415440010A202454" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_18 = "0x0568B04A2D0027208E21008881221C138070483D01E0009E0A00600054A20448819AC1106D3080DB" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_17 = "0x000230D0930CE3E02206040321808413A080402815A600A0530060E0C2420B0BD012300BE2404C46" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_16 = "0x092BD030740409200AD10A8C9130C90AE450A4DC1106103230010700420209654112081007003A19" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_15 = "0x04C320486705E000020000022126581C68809434134530C8D60203801C081843011A4D0C4E00700E" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_14 = "0x050B4050A202088100000000000000000000000000000000000000005001140C301831140C3034D0" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_13 = "0x15A0E0408E0C0C30140000E43042A400A0301A0C01A0C12099032B212000002ED018B4018D01B03D" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_12 = "0x01830120960944608C02064A80D8FC1060D1E0CF03084040741061810C80102D01C08C0600808E04" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_11 = "0x03021038100C0840E04114046020840E04110401182020100700808000A010C101007600E4308020" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_10 = "0x090A1008A4002C00E8161CE2110086004180C2980C281168070821C03C20180F4060F8060CA0408A" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_0F = "0x0603B0C2A9076CE0726D00A2304A0D0701A1E8E01264E040C0000510E8E0002411A68000A3709C66" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_0E = "0x0200108AD31000500E4E000141BA39108000A4741C826110041A68C02088106881844F048F30042A" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_0D = "0x0603B0C2A9056CA0526D00A2304A0D0501A1E8A01264A040C0000510E8A0002411A48000A3709466" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_0C = "0x0200108AD21000500E4A000141BA29108000A47414826110041A48C02088106881844F048F30042A" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_0B = "0x0603B0C2A9036C60326D00A2304A0D0301A1E86012646040C0000510E860002411A28000A3708C66" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_0A = "0x0200108AD11000500E46000141BA19108000A4740C826110041A28C02088106881844F048F30042A" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_09 = "0x0603B0C2A9016C20126D00A2304A0D0101A1E82012642040C0000510E820002411A08000A3708466" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_08 = "0x0200108AD01000500E42000141BA09108000A47404826110041A08C02088106881844F048F30042A" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_07 = "0x0603B0C2A9076CE0726D00A2304A0D0701A1E8E01264E040C0000510E8E0002411A68000A3709C66" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_06 = "0x0200108AD31000500E4E000141BA39108000A4741C826110041A68C02088106881844F048F30042A" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_05 = "0x0603B0C2A9056CA0526D00A2304A0D0501A1E8A01264A040C0000510E8A0002411A48000A3709466" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_04 = "0x0200108AD21000500E4A000141BA29108000A47414826110041A48C02088106881844F048F30042A" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_03 = "0x0603B0C2A9036C60326D00A2304A0D0301A1E86012646040C0000510E860002411A28000A3708C66" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_02 = "0x0200108AD11000500E46000141BA19108000A4740C826110041A28C02088106881844F048F30042A" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_01 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ;
|
||||
defparam codeROM_0_0_2_1.INITVAL_00 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FECE158AA150BA15EBE176B8" ;
|
||||
defparam codeROM_0_0_2_1.CSDECODE_B = "0b111" ;
|
||||
defparam codeROM_0_0_2_1.CSDECODE_A = "0b000" ;
|
||||
defparam codeROM_0_0_2_1.WRITEMODE_B = "NORMAL" ;
|
||||
defparam codeROM_0_0_2_1.WRITEMODE_A = "NORMAL" ;
|
||||
defparam codeROM_0_0_2_1.GSR = "ENABLED" ;
|
||||
defparam codeROM_0_0_2_1.RESETMODE = "SYNC" ;
|
||||
defparam codeROM_0_0_2_1.REGMODE_B = "NOREG" ;
|
||||
defparam codeROM_0_0_2_1.REGMODE_A = "OUTREG" ;
|
||||
defparam codeROM_0_0_2_1.DATA_WIDTH_B = 2 ;
|
||||
defparam codeROM_0_0_2_1.DATA_WIDTH_A = 2 ;
|
||||
DP8KC codeROM_0_0_2_1 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
|
||||
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
|
||||
.DIA1(scuba_vlo), .DIA0(scuba_vlo), .ADA12(Address[11]), .ADA11(Address[10]),
|
||||
.ADA10(Address[9]), .ADA9(Address[8]), .ADA8(Address[7]), .ADA7(Address[6]),
|
||||
.ADA6(Address[5]), .ADA5(Address[4]), .ADA4(Address[3]), .ADA3(Address[2]),
|
||||
.ADA2(Address[1]), .ADA1(Address[0]), .ADA0(scuba_vlo), .CEA(OutClockEn),
|
||||
.OCEA(OutClockEn), .CLKA(OutClock), .WEA(scuba_vlo), .CSA2(scuba_vlo),
|
||||
.CSA1(scuba_vlo), .CSA0(scuba_vlo), .RSTA(Reset), .DIB8(scuba_vlo),
|
||||
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
|
||||
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
|
||||
.ADB12(scuba_vlo), .ADB11(scuba_vlo), .ADB10(scuba_vlo), .ADB9(scuba_vlo),
|
||||
.ADB8(scuba_vlo), .ADB7(scuba_vlo), .ADB6(scuba_vlo), .ADB5(scuba_vlo),
|
||||
.ADB4(scuba_vlo), .ADB3(scuba_vlo), .ADB2(scuba_vlo), .ADB1(scuba_vlo),
|
||||
.ADB0(scuba_vlo), .CEB(scuba_vhi), .OCEB(scuba_vhi), .CLKB(scuba_vlo),
|
||||
.WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo),
|
||||
.RSTB(scuba_vlo), .DOA8(), .DOA7(), .DOA6(), .DOA5(), .DOA4(), .DOA3(),
|
||||
.DOA2(), .DOA1(Q[5]), .DOA0(Q[4]), .DOB8(), .DOB7(), .DOB6(), .DOB5(),
|
||||
.DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0())
|
||||
/* synthesis MEM_LPC_FILE="codeROM.lpc" */
|
||||
/* synthesis MEM_INIT_FILE="rom-full-4k.mem" */;
|
||||
|
||||
VHI scuba_vhi_inst (.Z(scuba_vhi));
|
||||
|
||||
VLO scuba_vlo_inst (.Z(scuba_vlo));
|
||||
|
||||
defparam codeROM_0_0_3_0.INIT_DATA = "STATIC" ;
|
||||
defparam codeROM_0_0_3_0.ASYNC_RESET_RELEASE = "SYNC" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_1F = "0x1E0FE17EAF1FEFB1FEAA156BF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FE00086FE1F6FE1E6FF" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_1D = "0x1FEBF1FCF31FCFF1FEBB1E6FF176C71FE0F1C4330463206698110B0044E419E2305C3800C000C608" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_1C = "0x1E08B18C000D8861908E0349903439122B41D46512C4E0CCF61A617058181309F00CA604C6604C26" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_1B = "0x04C590CAA718C00110101A419034381C6D90429A06633066220E40111C39130C8182860C69800C63" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_1A = "0x0DA381DC191128D100660642D034991328C110CF0AE2512885152881983E0CC660CCD300CA60CC66" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_19 = "0x06C620C8F9100660CC6604C2E0E698158AC1588F06C331CE48130B6076E604CBD110EF096C2066F7" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_18 = "0x0523E0CE6F10C620CC2E090D81329B1366604C1911CF400C6E02431000000DE0818AD31669B06A89" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_17 = "0x03211130431201A17A490CE27032C909ED004C2913E0E0DCAE0F4E90E4610324C128011302602C65" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_16 = "0x0324C12866052990CAF90A8D91B8CD0AEE50BE8D1126C0DE0D12EE60643507C2410298136E61F294" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_15 = "0x04E3314C630DA0000000000411E6DB01E0816838132C11F8F604C1911CC00CC3910C8E0C4A60328E" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_14 = "0x1E4BB10ECA05C08110881108810482104821002A1002A10000054AA1300113CBA1D6AC03CBA182FF" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_13 = "0x13EBC0583C0DCBA182651D63A142791EC92098E9118E813059128361929608C4C1D0BF1E4CE116AC" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_12 = "0x1D6AC036460C4660CC6218AFF086FF0F4E819C881808E05CBD074F317885174CE142B506ED00CCEA" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_11 = "0x03641136A80DA060DCA112ED707A060DCA116819174861A0661D4191209712E3D00C661D63A0D06E" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_10 = "0x130BC09AB91C2BE176861C66F042BC10CF319E1B19E21164EB170DB15C2E16A3E01C8B15CB80583C" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_0F = "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_0E = "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_0D = "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_0C = "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_0B = "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_0A = "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_09 = "0x04034046241F63E1F0EF1EA230C6FC1F250066E60B63E188DF0CA6D0E6ED12AB519EB60ACC707C67" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_08 = "0x07A9516ACF16C561AE3E1B25B038F919E650D8731CC061025619EB906A8B1BE881DC050408206422" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_07 = "0x04034046241D63A1D0EF1EA230C6FC1D250066A60B63A188DF0CA6D0E6AD12AB519CB60ACC707467" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_06 = "0x07A9516ACE16C561AE3A1B25B038E919E650D87314C061025619CB906A8B1BE881DC050408206422" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_05 = "0x04034046241D63A1D0EF1EA230C6FC1D250066A60B63A188DF0CA6D0E6AD12AB519CB60ACC707467" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_04 = "0x07A9516ACE16C561AE3A1B25B038E919E650D87314C061025619CB906A8B1BE881DC050408206422" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_03 = "0x04034046241D63A1D0EF1EA230C6FC1D250066A60B63A188DF0CA6D0E6AD12AB519CB60ACC707467" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_02 = "0x07A9516ACE16C561AE3A1B25B038E919E650D87314C061025619CB906A8B1BE881DC050408206422" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_01 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF" ;
|
||||
defparam codeROM_0_0_3_0.INITVAL_00 = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FECF1FEBF1FEBE1FEFE1FEFF" ;
|
||||
defparam codeROM_0_0_3_0.CSDECODE_B = "0b111" ;
|
||||
defparam codeROM_0_0_3_0.CSDECODE_A = "0b000" ;
|
||||
defparam codeROM_0_0_3_0.WRITEMODE_B = "NORMAL" ;
|
||||
defparam codeROM_0_0_3_0.WRITEMODE_A = "NORMAL" ;
|
||||
defparam codeROM_0_0_3_0.GSR = "ENABLED" ;
|
||||
defparam codeROM_0_0_3_0.RESETMODE = "SYNC" ;
|
||||
defparam codeROM_0_0_3_0.REGMODE_B = "NOREG" ;
|
||||
defparam codeROM_0_0_3_0.REGMODE_A = "OUTREG" ;
|
||||
defparam codeROM_0_0_3_0.DATA_WIDTH_B = 2 ;
|
||||
defparam codeROM_0_0_3_0.DATA_WIDTH_A = 2 ;
|
||||
DP8KC codeROM_0_0_3_0 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
|
||||
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
|
||||
.DIA1(scuba_vlo), .DIA0(scuba_vlo), .ADA12(Address[11]), .ADA11(Address[10]),
|
||||
.ADA10(Address[9]), .ADA9(Address[8]), .ADA8(Address[7]), .ADA7(Address[6]),
|
||||
.ADA6(Address[5]), .ADA5(Address[4]), .ADA4(Address[3]), .ADA3(Address[2]),
|
||||
.ADA2(Address[1]), .ADA1(Address[0]), .ADA0(scuba_vlo), .CEA(OutClockEn),
|
||||
.OCEA(OutClockEn), .CLKA(OutClock), .WEA(scuba_vlo), .CSA2(scuba_vlo),
|
||||
.CSA1(scuba_vlo), .CSA0(scuba_vlo), .RSTA(Reset), .DIB8(scuba_vlo),
|
||||
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
|
||||
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
|
||||
.ADB12(scuba_vlo), .ADB11(scuba_vlo), .ADB10(scuba_vlo), .ADB9(scuba_vlo),
|
||||
.ADB8(scuba_vlo), .ADB7(scuba_vlo), .ADB6(scuba_vlo), .ADB5(scuba_vlo),
|
||||
.ADB4(scuba_vlo), .ADB3(scuba_vlo), .ADB2(scuba_vlo), .ADB1(scuba_vlo),
|
||||
.ADB0(scuba_vlo), .CEB(scuba_vhi), .OCEB(scuba_vhi), .CLKB(scuba_vlo),
|
||||
.WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo),
|
||||
.RSTB(scuba_vlo), .DOA8(), .DOA7(), .DOA6(), .DOA5(), .DOA4(), .DOA3(),
|
||||
.DOA2(), .DOA1(Q[7]), .DOA0(Q[6]), .DOB8(), .DOB7(), .DOB6(), .DOB5(),
|
||||
.DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0())
|
||||
/* synthesis MEM_LPC_FILE="codeROM.lpc" */
|
||||
/* synthesis MEM_INIT_FILE="rom-full-4k.mem" */;
|
||||
|
||||
|
||||
|
||||
// exemplar begin
|
||||
// exemplar attribute codeROM_0_0_0_3 MEM_LPC_FILE codeROM.lpc
|
||||
// exemplar attribute codeROM_0_0_0_3 MEM_INIT_FILE rom-full-4k.mem
|
||||
// exemplar attribute codeROM_0_0_1_2 MEM_LPC_FILE codeROM.lpc
|
||||
// exemplar attribute codeROM_0_0_1_2 MEM_INIT_FILE rom-full-4k.mem
|
||||
// exemplar attribute codeROM_0_0_2_1 MEM_LPC_FILE codeROM.lpc
|
||||
// exemplar attribute codeROM_0_0_2_1 MEM_INIT_FILE rom-full-4k.mem
|
||||
// exemplar attribute codeROM_0_0_3_0 MEM_LPC_FILE codeROM.lpc
|
||||
// exemplar attribute codeROM_0_0_3_0 MEM_INIT_FILE rom-full-4k.mem
|
||||
// exemplar end
|
||||
|
||||
endmodule
|
||||
6
lattice/codeROM_tmpl.v
Normal file
6
lattice/codeROM_tmpl.v
Normal file
@ -0,0 +1,6 @@
|
||||
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.9.0.99.2 */
|
||||
/* Module Version: 5.4 */
|
||||
/* Tue Jan 30 17:35:12 2018 */
|
||||
|
||||
/* parameterized module instance */
|
||||
codeROM __ (.Address( ), .OutClock( ), .OutClockEn( ), .Reset( ), .Q( ));
|
||||
40
lattice/fpgatop/.build_status
Normal file
40
lattice/fpgatop/.build_status
Normal file
@ -0,0 +1,40 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BuildStatus>
|
||||
<Strategy name="Strategy1">
|
||||
<Milestone name="Export" build_result="0" build_time="0">
|
||||
<Task name="IBIS" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="Bitgen" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="Jedecgen" build_result="0" update_result="2" update_time="1519325808"/>
|
||||
</Milestone>
|
||||
<Milestone name="Map" build_result="0" build_time="1519325799">
|
||||
<Task name="Map" build_result="0" update_result="2" update_time="1519325799"/>
|
||||
<Task name="MapTrace" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Milestone name="PAR" build_result="0" build_time="1519325804">
|
||||
<Task name="PAR" build_result="0" update_result="2" update_time="1519325804"/>
|
||||
<Task name="PARTrace" build_result="0" update_result="2" update_time="1519325805"/>
|
||||
<Task name="IOTiming" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Milestone name="Synthesis" build_result="0" build_time="1519325798">
|
||||
<Task name="Lattice_Synthesis" build_result="0" update_result="2" update_time="1519325798"/>
|
||||
<Task name="LSE_Compile" build_result="0" update_result="2" update_time="1519325808"/>
|
||||
</Milestone>
|
||||
<Milestone name="TOOL_Report" build_result="0" build_time="0">
|
||||
<Task name="HDLE" build_result="0" update_result="2" update_time="1519325793"/>
|
||||
<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Report name=".vdbs/liron_fpgatop_map.vdb" last_build_time="1519325799" last_build_size="60806"/>
|
||||
<Report name="liron_fpgatop.bgn" last_build_time="1519325808" last_build_size="4508"/>
|
||||
<Report name="liron_fpgatop.jed" last_build_time="1519325808" last_build_size="351577"/>
|
||||
<Report name="liron_fpgatop.lsedata" last_build_time="1519325797" last_build_size="225045"/>
|
||||
<Report name="liron_fpgatop.ncd" last_build_time="1519325804" last_build_size="193114"/>
|
||||
<Report name="liron_fpgatop.ngd" last_build_time="1519325798" last_build_size="138411"/>
|
||||
<Report name="liron_fpgatop.twr" last_build_time="1519325805" last_build_size="49333"/>
|
||||
<Report name="liron_fpgatop_map.ncd" last_build_time="1519325799" last_build_size="145088"/>
|
||||
</Strategy>
|
||||
</BuildStatus>
|
||||
1
lattice/fpgatop/.vdbs/dbStat.txt
Normal file
1
lattice/fpgatop/.vdbs/dbStat.txt
Normal file
@ -0,0 +1 @@
|
||||
top_rtl.vdb
|
||||
BIN
lattice/fpgatop/.vdbs/liron_fpgatop_map.vdb
Normal file
BIN
lattice/fpgatop/.vdbs/liron_fpgatop_map.vdb
Normal file
Binary file not shown.
BIN
lattice/fpgatop/.vdbs/top_rtl.vdb
Normal file
BIN
lattice/fpgatop/.vdbs/top_rtl.vdb
Normal file
Binary file not shown.
BIN
lattice/fpgatop/.vdbs/top_tech.vdb
Normal file
BIN
lattice/fpgatop/.vdbs/top_tech.vdb
Normal file
Binary file not shown.
5
lattice/fpgatop/Untitled.tpf.prf
Normal file
5
lattice/fpgatop/Untitled.tpf.prf
Normal file
@ -0,0 +1,5 @@
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
AUTOMOTIVE ;
|
||||
FREQUENCY NET "fclk_c" 318.066000 MHz ;
|
||||
COMMERCIAL ;
|
||||
34
lattice/fpgatop/Untitled.tpf.prf_cdmp
Normal file
34
lattice/fpgatop/Untitled.tpf.prf_cdmp
Normal file
@ -0,0 +1,34 @@
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
IOBUF PORT "data[7]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[6]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[5]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[4]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[3]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[2]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[1]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[0]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "wrdata" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "phase[3]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "phase[2]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "phase[1]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "phase[0]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_wrreq" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_enbl1" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_enbl2" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_romoe" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_enbuf" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "addr[3]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "addr[2]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "addr[1]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "addr[0]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_xFFx" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "fclk" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "q3" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_iostrobe" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_iosel" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_devsel" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_reset" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "sense" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "rddata" IO_TYPE=LVCMOS25 ;
|
||||
FREQUENCY NET "fclk_c" 318.066016 MHz ;
|
||||
4
lattice/fpgatop/Untitled.tpf.prf_cdmp0
Normal file
4
lattice/fpgatop/Untitled.tpf.prf_cdmp0
Normal file
@ -0,0 +1,4 @@
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
AUTOMOTIVE ;
|
||||
FREQUENCY NET "fclk_c" 318.066000 MHz ;
|
||||
34
lattice/fpgatop/Untitled.tpf.prf_cdmp2
Normal file
34
lattice/fpgatop/Untitled.tpf.prf_cdmp2
Normal file
@ -0,0 +1,34 @@
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
IOBUF PORT "data[7]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[6]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[5]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[4]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[3]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[2]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[1]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "data[0]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "wrdata" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "phase[3]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "phase[2]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "phase[1]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "phase[0]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_wrreq" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_enbl1" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_enbl2" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_romoe" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_enbuf" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "addr[3]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "addr[2]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "addr[1]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "addr[0]" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_xFFx" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "fclk" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "q3" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_iostrobe" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_iosel" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_devsel" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "_reset" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "sense" IO_TYPE=LVCMOS25 ;
|
||||
IOBUF PORT "rddata" IO_TYPE=LVCMOS25 ;
|
||||
FREQUENCY NET "fclk_c" 318.066016 MHz ;
|
||||
535
lattice/fpgatop/Untitled.tpf_hold.html
Normal file
535
lattice/fpgatop/Untitled.tpf_hold.html
Normal file
@ -0,0 +1,535 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
<HTML><HEAD>
|
||||
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
|
||||
<STYLE type=text/css>
|
||||
<!--
|
||||
.blink {text-decoration:blink}
|
||||
.ms {font-size: 9pt; font-family: monospace; font-weight: normal}
|
||||
.msb {font-size: 9pt; font-family: monospace; font-weight: bold }
|
||||
-->
|
||||
</STYLE>
|
||||
<META content="MSHTML 6.00.2900.2180" name=GENERATOR></HEAD>
|
||||
<BODY><B>
|
||||
</B>
|
||||
<BR><PRE><A name="Report Header"></A>
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.9.0.99.2
|
||||
Wed Jul 26 13:46:07 2017
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Design file: top
|
||||
Device,speed: LAMXO256C,M
|
||||
Report level: verbose report, limited to 10 items per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
</A><A name="FREQUENCY NET 'fclk_c' 318.066000 MH"></A>================================================================================
|
||||
Preference: FREQUENCY NET "fclk_c" 318.066000 MHz ;
|
||||
10 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
<font color=#000000>
|
||||
|
||||
Passed: The following path meets requirements by 0.281ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_33">myIwm/bitCounter_154__i0</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_33">myIwm/bitCounter_154__i0</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 0.264ns (47.7% logic, 52.3% route), 1 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.264ns physical path delay myIwm/SLICE_33 to myIwm/SLICE_33 meets
|
||||
-0.017ns M_HLD and
|
||||
0.000ns delay constraint less
|
||||
0.000ns skew requirement (totaling -0.017ns) by 0.281ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.126,R7C5B.CLK,R7C5B.Q0,myIwm/SLICE_33:ROUTE, 0.138,R7C5B.Q0,R7C5B.M0,myIwm/bitCounter_0">Data path</A> myIwm/SLICE_33 to myIwm/SLICE_33:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.126 R7C5B.CLK to R7C5B.Q0 <A href="#@comp:myIwm/SLICE_33">myIwm/SLICE_33</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 4 0.138<A href="#@net:myIwm/bitCounter_0:R7C5B.Q0:R7C5B.M0:0.138"> R7C5B.Q0 to R7C5B.M0 </A> <A href="#@net:myIwm/bitCounter_0">myIwm/bitCounter_0</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
0.264 (47.7% logic, 52.3% route), 1 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R7C5B.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_33:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R7C5B.CLK:0.333"> 36.PADDI to R7C5B.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R7C5B.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_33:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R7C5B.CLK:0.333"> 36.PADDI to R7C5B.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#000000>
|
||||
|
||||
Passed: The following path meets requirements by 0.281ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_38">myIwm/rddataSync_i0</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_38">myIwm/rddataSync_i1</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 0.264ns (47.7% logic, 52.3% route), 1 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.264ns physical path delay myIwm/SLICE_38 to myIwm/SLICE_38 meets
|
||||
-0.017ns M_HLD and
|
||||
0.000ns delay constraint less
|
||||
0.000ns skew requirement (totaling -0.017ns) by 0.281ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.126,R5C3D.CLK,R5C3D.Q0,myIwm/SLICE_38:ROUTE, 0.138,R5C3D.Q0,R5C3D.M1,myIwm/rddataSync_0">Data path</A> myIwm/SLICE_38 to myIwm/SLICE_38:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.126 R5C3D.CLK to R5C3D.Q0 <A href="#@comp:myIwm/SLICE_38">myIwm/SLICE_38</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 7 0.138<A href="#@net:myIwm/rddataSync_0:R5C3D.Q0:R5C3D.M1:0.138"> R5C3D.Q0 to R5C3D.M1 </A> <A href="#@net:myIwm/rddataSync_0">myIwm/rddataSync_0</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
0.264 (47.7% logic, 52.3% route), 1 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R5C3D.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_38:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R5C3D.CLK:0.333"> 36.PADDI to R5C3D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R5C3D.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_38:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R5C3D.CLK:0.333"> 36.PADDI to R5C3D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#000000>
|
||||
|
||||
Passed: The following path meets requirements by 0.339ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_3">myIwm/bitCounter_154__i2</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_3">myIwm/bitCounter_154__i2</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 0.331ns (60.4% logic, 39.6% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.331ns physical path delay myIwm/SLICE_3 to myIwm/SLICE_3 meets
|
||||
-0.008ns DIN_HLD and
|
||||
0.000ns delay constraint less
|
||||
0.000ns skew requirement (totaling -0.008ns) by 0.339ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.126,R7C5A.CLK,R7C5A.Q1,myIwm/SLICE_3:ROUTE, 0.131,R7C5A.Q1,R7C5A.A1,myIwm/bitCounter_2:CTOF_DEL, 0.074,R7C5A.A1,R7C5A.F1,myIwm/SLICE_3:ROUTE, 0.000,R7C5A.F1,R7C5A.DI1,myIwm/n18">Data path</A> myIwm/SLICE_3 to myIwm/SLICE_3:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.126 R7C5A.CLK to R7C5A.Q1 <A href="#@comp:myIwm/SLICE_3">myIwm/SLICE_3</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 2 0.131<A href="#@net:myIwm/bitCounter_2:R7C5A.Q1:R7C5A.A1:0.131"> R7C5A.Q1 to R7C5A.A1 </A> <A href="#@net:myIwm/bitCounter_2">myIwm/bitCounter_2</A>
|
||||
CTOF_DEL --- 0.074 R7C5A.A1 to R7C5A.F1 <A href="#@comp:myIwm/SLICE_3">myIwm/SLICE_3</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/n18:R7C5A.F1:R7C5A.DI1:0.000"> R7C5A.F1 to R7C5A.DI1 </A> <A href="#@net:myIwm/n18">myIwm/n18</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
0.331 (60.4% logic, 39.6% route), 2 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R7C5A.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_3:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R7C5A.CLK:0.333"> 36.PADDI to R7C5A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R7C5A.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_3:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R7C5A.CLK:0.333"> 36.PADDI to R7C5A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#000000>
|
||||
|
||||
Passed: The following path meets requirements by 0.339ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_3">myIwm/bitCounter_154__i1</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_3">myIwm/bitCounter_154__i1</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 0.331ns (60.4% logic, 39.6% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.331ns physical path delay myIwm/SLICE_3 to myIwm/SLICE_3 meets
|
||||
-0.008ns DIN_HLD and
|
||||
0.000ns delay constraint less
|
||||
0.000ns skew requirement (totaling -0.008ns) by 0.339ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.126,R7C5A.CLK,R7C5A.Q0,myIwm/SLICE_3:ROUTE, 0.131,R7C5A.Q0,R7C5A.A0,myIwm/bitCounter_1:CTOF_DEL, 0.074,R7C5A.A0,R7C5A.F0,myIwm/SLICE_3:ROUTE, 0.000,R7C5A.F0,R7C5A.DI0,myIwm/n19">Data path</A> myIwm/SLICE_3 to myIwm/SLICE_3:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.126 R7C5A.CLK to R7C5A.Q0 <A href="#@comp:myIwm/SLICE_3">myIwm/SLICE_3</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 3 0.131<A href="#@net:myIwm/bitCounter_1:R7C5A.Q0:R7C5A.A0:0.131"> R7C5A.Q0 to R7C5A.A0 </A> <A href="#@net:myIwm/bitCounter_1">myIwm/bitCounter_1</A>
|
||||
CTOF_DEL --- 0.074 R7C5A.A0 to R7C5A.F0 <A href="#@comp:myIwm/SLICE_3">myIwm/SLICE_3</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/n19:R7C5A.F0:R7C5A.DI0:0.000"> R7C5A.F0 to R7C5A.DI0 </A> <A href="#@net:myIwm/n19">myIwm/n19</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
0.331 (60.4% logic, 39.6% route), 2 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R7C5A.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_3:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R7C5A.CLK:0.333"> 36.PADDI to R7C5A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R7C5A.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_3:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R7C5A.CLK:0.333"> 36.PADDI to R7C5A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#000000>
|
||||
|
||||
Passed: The following path meets requirements by 0.340ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_3">myIwm/bitCounter_154__i1</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_3">myIwm/bitCounter_154__i2</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 0.332ns (60.2% logic, 39.8% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.332ns physical path delay myIwm/SLICE_3 to myIwm/SLICE_3 meets
|
||||
-0.008ns DIN_HLD and
|
||||
0.000ns delay constraint less
|
||||
0.000ns skew requirement (totaling -0.008ns) by 0.340ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.126,R7C5A.CLK,R7C5A.Q0,myIwm/SLICE_3:ROUTE, 0.132,R7C5A.Q0,R7C5A.D1,myIwm/bitCounter_1:CTOF_DEL, 0.074,R7C5A.D1,R7C5A.F1,myIwm/SLICE_3:ROUTE, 0.000,R7C5A.F1,R7C5A.DI1,myIwm/n18">Data path</A> myIwm/SLICE_3 to myIwm/SLICE_3:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.126 R7C5A.CLK to R7C5A.Q0 <A href="#@comp:myIwm/SLICE_3">myIwm/SLICE_3</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 3 0.132<A href="#@net:myIwm/bitCounter_1:R7C5A.Q0:R7C5A.D1:0.132"> R7C5A.Q0 to R7C5A.D1 </A> <A href="#@net:myIwm/bitCounter_1">myIwm/bitCounter_1</A>
|
||||
CTOF_DEL --- 0.074 R7C5A.D1 to R7C5A.F1 <A href="#@comp:myIwm/SLICE_3">myIwm/SLICE_3</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/n18:R7C5A.F1:R7C5A.DI1:0.000"> R7C5A.F1 to R7C5A.DI1 </A> <A href="#@net:myIwm/n18">myIwm/n18</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
0.332 (60.2% logic, 39.8% route), 2 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R7C5A.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_3:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R7C5A.CLK:0.333"> 36.PADDI to R7C5A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R7C5A.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_3:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R7C5A.CLK:0.333"> 36.PADDI to R7C5A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#000000>
|
||||
|
||||
Passed: The following path meets requirements by 0.342ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_5">myIwm/bitTimer__i3</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_6">myIwm/bitTimer__i4</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 0.334ns (59.9% logic, 40.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.334ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_6 meets
|
||||
-0.008ns DIN_HLD and
|
||||
0.000ns delay constraint less
|
||||
0.000ns skew requirement (totaling -0.008ns) by 0.342ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.126,R7C4A.CLK,R7C4A.Q1,myIwm/SLICE_5:ROUTE, 0.134,R7C4A.Q1,R7C4D.D0,myIwm/bitTimer_3:CTOF_DEL, 0.074,R7C4D.D0,R7C4D.F0,myIwm/SLICE_6:ROUTE, 0.000,R7C4D.F0,R7C4D.DI0,myIwm/n183">Data path</A> myIwm/SLICE_5 to myIwm/SLICE_6:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.126 R7C4A.CLK to R7C4A.Q1 <A href="#@comp:myIwm/SLICE_5">myIwm/SLICE_5</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 9 0.134<A href="#@net:myIwm/bitTimer_3:R7C4A.Q1:R7C4D.D0:0.134"> R7C4A.Q1 to R7C4D.D0 </A> <A href="#@net:myIwm/bitTimer_3">myIwm/bitTimer_3</A>
|
||||
CTOF_DEL --- 0.074 R7C4D.D0 to R7C4D.F0 <A href="#@comp:myIwm/SLICE_6">myIwm/SLICE_6</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/n183:R7C4D.F0:R7C4D.DI0:0.000"> R7C4D.F0 to R7C4D.DI0 </A> <A href="#@net:myIwm/n183">myIwm/n183</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
0.334 (59.9% logic, 40.1% route), 2 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R7C4A.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_5:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R7C4A.CLK:0.333"> 36.PADDI to R7C4A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R7C4D.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_6:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R7C4D.CLK:0.333"> 36.PADDI to R7C4D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#000000>
|
||||
|
||||
Passed: The following path meets requirements by 0.342ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_13">myIwm/clearBufferTimer_i0_i3</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_13">myIwm/clearBufferTimer_i0_i3</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 0.334ns (59.9% logic, 40.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.334ns physical path delay myIwm/SLICE_13 to myIwm/SLICE_13 meets
|
||||
-0.008ns DIN_HLD and
|
||||
0.000ns delay constraint less
|
||||
0.000ns skew requirement (totaling -0.008ns) by 0.342ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.126,R5C2D.CLK,R5C2D.Q0,myIwm/SLICE_13:ROUTE, 0.134,R5C2D.Q0,R5C2D.A0,myIwm/clearBufferTimer_3:CTOF_DEL, 0.074,R5C2D.A0,R5C2D.F0,myIwm/SLICE_13:ROUTE, 0.000,R5C2D.F0,R5C2D.DI0,myIwm/n105">Data path</A> myIwm/SLICE_13 to myIwm/SLICE_13:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.126 R5C2D.CLK to R5C2D.Q0 <A href="#@comp:myIwm/SLICE_13">myIwm/SLICE_13</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 4 0.134<A href="#@net:myIwm/clearBufferTimer_3:R5C2D.Q0:R5C2D.A0:0.134"> R5C2D.Q0 to R5C2D.A0 </A> <A href="#@net:myIwm/clearBufferTimer_3">myIwm/clearBufferTimer_3</A>
|
||||
CTOF_DEL --- 0.074 R5C2D.A0 to R5C2D.F0 <A href="#@comp:myIwm/SLICE_13">myIwm/SLICE_13</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/n105:R5C2D.F0:R5C2D.DI0:0.000"> R5C2D.F0 to R5C2D.DI0 </A> <A href="#@net:myIwm/n105">myIwm/n105</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
0.334 (59.9% logic, 40.1% route), 2 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R5C2D.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_13:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R5C2D.CLK:0.333"> 36.PADDI to R5C2D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R5C2D.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_13:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R5C2D.CLK:0.333"> 36.PADDI to R5C2D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#000000>
|
||||
|
||||
Passed: The following path meets requirements by 0.342ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_12">myIwm/clearBufferTimer_i0_i2</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_12">myIwm/clearBufferTimer_i0_i2</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 0.334ns (59.9% logic, 40.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.334ns physical path delay myIwm/SLICE_12 to myIwm/SLICE_12 meets
|
||||
-0.008ns DIN_HLD and
|
||||
0.000ns delay constraint less
|
||||
0.000ns skew requirement (totaling -0.008ns) by 0.342ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.126,R5C2A.CLK,R5C2A.Q1,myIwm/SLICE_12:ROUTE, 0.134,R5C2A.Q1,R5C2A.A1,myIwm/clearBufferTimer_2:CTOF_DEL, 0.074,R5C2A.A1,R5C2A.F1,myIwm/SLICE_12:ROUTE, 0.000,R5C2A.F1,R5C2A.DI1,myIwm/n106">Data path</A> myIwm/SLICE_12 to myIwm/SLICE_12:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.126 R5C2A.CLK to R5C2A.Q1 <A href="#@comp:myIwm/SLICE_12">myIwm/SLICE_12</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 5 0.134<A href="#@net:myIwm/clearBufferTimer_2:R5C2A.Q1:R5C2A.A1:0.134"> R5C2A.Q1 to R5C2A.A1 </A> <A href="#@net:myIwm/clearBufferTimer_2">myIwm/clearBufferTimer_2</A>
|
||||
CTOF_DEL --- 0.074 R5C2A.A1 to R5C2A.F1 <A href="#@comp:myIwm/SLICE_12">myIwm/SLICE_12</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/n106:R5C2A.F1:R5C2A.DI1:0.000"> R5C2A.F1 to R5C2A.DI1 </A> <A href="#@net:myIwm/n106">myIwm/n106</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
0.334 (59.9% logic, 40.1% route), 2 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R5C2A.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_12:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R5C2A.CLK:0.333"> 36.PADDI to R5C2A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R5C2A.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_12:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R5C2A.CLK:0.333"> 36.PADDI to R5C2A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#000000>
|
||||
|
||||
Passed: The following path meets requirements by 0.342ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_6">myIwm/bitTimer__i5</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_6">myIwm/bitTimer__i5</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 0.334ns (59.9% logic, 40.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.334ns physical path delay myIwm/SLICE_6 to myIwm/SLICE_6 meets
|
||||
-0.008ns DIN_HLD and
|
||||
0.000ns delay constraint less
|
||||
0.000ns skew requirement (totaling -0.008ns) by 0.342ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.126,R7C4D.CLK,R7C4D.Q1,myIwm/SLICE_6:ROUTE, 0.134,R7C4D.Q1,R7C4D.D1,myIwm/bitTimer_5:CTOF_DEL, 0.074,R7C4D.D1,R7C4D.F1,myIwm/SLICE_6:ROUTE, 0.000,R7C4D.F1,R7C4D.DI1,myIwm/n184">Data path</A> myIwm/SLICE_6 to myIwm/SLICE_6:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.126 R7C4D.CLK to R7C4D.Q1 <A href="#@comp:myIwm/SLICE_6">myIwm/SLICE_6</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 5 0.134<A href="#@net:myIwm/bitTimer_5:R7C4D.Q1:R7C4D.D1:0.134"> R7C4D.Q1 to R7C4D.D1 </A> <A href="#@net:myIwm/bitTimer_5">myIwm/bitTimer_5</A>
|
||||
CTOF_DEL --- 0.074 R7C4D.D1 to R7C4D.F1 <A href="#@comp:myIwm/SLICE_6">myIwm/SLICE_6</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/n184:R7C4D.F1:R7C4D.DI1:0.000"> R7C4D.F1 to R7C4D.DI1 </A> <A href="#@net:myIwm/n184">myIwm/n184</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
0.334 (59.9% logic, 40.1% route), 2 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R7C4D.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_6:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R7C4D.CLK:0.333"> 36.PADDI to R7C4D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R7C4D.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_6:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R7C4D.CLK:0.333"> 36.PADDI to R7C4D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#000000>
|
||||
|
||||
Passed: The following path meets requirements by 0.342ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_4">myIwm/bitTimer__i1</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_4">myIwm/bitTimer__i1</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 0.334ns (59.9% logic, 40.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.334ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_4 meets
|
||||
-0.008ns DIN_HLD and
|
||||
0.000ns delay constraint less
|
||||
0.000ns skew requirement (totaling -0.008ns) by 0.342ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.126,R6C4D.CLK,R6C4D.Q1,myIwm/SLICE_4:ROUTE, 0.134,R6C4D.Q1,R6C4D.A1,myIwm/bitTimer_1:CTOF_DEL, 0.074,R6C4D.A1,R6C4D.F1,myIwm/SLICE_4:ROUTE, 0.000,R6C4D.F1,R6C4D.DI1,myIwm/n180">Data path</A> myIwm/SLICE_4 to myIwm/SLICE_4:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.126 R6C4D.CLK to R6C4D.Q1 <A href="#@comp:myIwm/SLICE_4">myIwm/SLICE_4</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 8 0.134<A href="#@net:myIwm/bitTimer_1:R6C4D.Q1:R6C4D.A1:0.134"> R6C4D.Q1 to R6C4D.A1 </A> <A href="#@net:myIwm/bitTimer_1">myIwm/bitTimer_1</A>
|
||||
CTOF_DEL --- 0.074 R6C4D.A1 to R6C4D.F1 <A href="#@comp:myIwm/SLICE_4">myIwm/SLICE_4</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/n180:R6C4D.F1:R6C4D.DI1:0.000"> R6C4D.F1 to R6C4D.DI1 </A> <A href="#@net:myIwm/n180">myIwm/n180</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
0.334 (59.9% logic, 40.1% route), 2 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R6C4D.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_4:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R6C4D.CLK:0.333"> 36.PADDI to R6C4D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 0.333,36.PADDI,R6C4D.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_4:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 0.333<A href="#@net:fclk_c:36.PADDI:R6C4D.CLK:0.333"> 36.PADDI to R6C4D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
0.333 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A name="Report Summary"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference(MIN Delays) | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY NET "fclk_c" 318.066000 MHz ; | 0.000 ns| 0.281 ns| 1
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
<A name="Clock Domains Analysis"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
||||
------------------------
|
||||
|
||||
Found 3 clocks:
|
||||
|
||||
Clock Domain: <A href="#@net:fclk_c">fclk_c</A> Source: fclk.PAD Loads: 24
|
||||
Covered under: FREQUENCY NET "fclk_c" 318.066000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: <A href="#@net:_devsel_c">_devsel_c</A> Source: _devsel.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: <A href="#@net:_devsel_c">_devsel_c</A> Source: _devsel.PAD Loads: 11
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: <A href="#@net:_iosel_c">_iosel_c</A> Source: _iosel.PAD Loads: 2
|
||||
No transfer within this clock domain is found
|
||||
|
||||
|
||||
Timing summary (Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 841 paths, 1 nets, and 319 connections (64.84% coverage)
|
||||
|
||||
|
||||
|
||||
Timing summary (Setup and Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 10 (setup), 0 (hold)
|
||||
Score: 59154 (setup), 0 (hold)
|
||||
Cumulative negative slack: 59154 (59154+0)
|
||||
662
lattice/fpgatop/Untitled.tpf_setup.html
Normal file
662
lattice/fpgatop/Untitled.tpf_setup.html
Normal file
@ -0,0 +1,662 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
<HTML><HEAD>
|
||||
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
|
||||
<STYLE type=text/css>
|
||||
<!--
|
||||
.blink {text-decoration:blink}
|
||||
.ms {font-size: 9pt; font-family: monospace; font-weight: normal}
|
||||
.msb {font-size: 9pt; font-family: monospace; font-weight: bold }
|
||||
-->
|
||||
</STYLE>
|
||||
<META content="MSHTML 6.00.2900.2180" name=GENERATOR></HEAD>
|
||||
<BODY><B>
|
||||
</B>
|
||||
<BR><PRE><A name="Report Header"></A>
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.9.0.99.2
|
||||
Wed Jul 26 13:46:07 2017
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Design file: top
|
||||
Device,speed: LAMXO256C,3
|
||||
Report level: verbose report, limited to 10 items per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
</A><A name="FREQUENCY NET 'fclk_c' 318.066000 MH"></A>================================================================================
|
||||
Preference: FREQUENCY NET "fclk_c" 318.066000 MHz ;
|
||||
10 items scored, 10 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
<font color=#FF0000>
|
||||
|
||||
Error: The following path exceeds requirements by 6.415ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_5">myIwm/bitTimer__i2</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_26">myIwm/shifter_i0_i7</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 9.378ns (32.3% logic, 67.7% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.378ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_26 exceeds
|
||||
3.144ns delay constraint less
|
||||
0.000ns skew and
|
||||
0.181ns DIN_SET requirement (totaling 2.963ns) by 6.415ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.560,R7C4A.CLK,R7C4A.Q0,myIwm/SLICE_5:ROUTE, 1.209,R7C4A.Q0,R6C3D.D0,myIwm/bitTimer_2:CTOF_DEL, 0.371,R6C3D.D0,R6C3D.F0,myIwm/SLICE_51:ROUTE, 0.901,R6C3D.F0,R6C4C.C0,myIwm/n6:CTOF_DEL, 0.371,R6C4C.C0,R6C4C.F0,myIwm/SLICE_36:ROUTE, 1.138,R6C4C.F0,R5C4D.B1,myIwm/n133:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,myIwm/SLICE_35:ROUTE, 0.497,R5C4D.F1,R5C4D.C0,myIwm/n1516:CTOF_DEL, 0.371,R5C4D.C0,R5C4D.F0,myIwm/SLICE_35:ROUTE, 0.657,R5C4D.F0,R5C4C.D1,myIwm/n65:CTOF_DEL, 0.371,R5C4C.D1,R5C4C.F1,myIwm/SLICE_27:ROUTE, 1.946,R5C4C.F1,R4C5C.B1,myIwm/n395:CTOOFX_DEL, 0.615,R4C5C.B1,R4C5C.OFX0,myIwm/SLICE_26:ROUTE, 0.000,R4C5C.OFX0,R4C5C.DI0,myIwm/shifter_7_N_85_7">Data path</A> myIwm/SLICE_5 to myIwm/SLICE_26:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 R7C4A.CLK to R7C4A.Q0 <A href="#@comp:myIwm/SLICE_5">myIwm/SLICE_5</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 7 1.209<A href="#@net:myIwm/bitTimer_2:R7C4A.Q0:R6C3D.D0:1.209"> R7C4A.Q0 to R6C3D.D0 </A> <A href="#@net:myIwm/bitTimer_2">myIwm/bitTimer_2</A>
|
||||
CTOF_DEL --- 0.371 R6C3D.D0 to R6C3D.F0 <A href="#@comp:myIwm/SLICE_51">myIwm/SLICE_51</A>
|
||||
ROUTE 2 0.901<A href="#@net:myIwm/n6:R6C3D.F0:R6C4C.C0:0.901"> R6C3D.F0 to R6C4C.C0 </A> <A href="#@net:myIwm/n6">myIwm/n6</A>
|
||||
CTOF_DEL --- 0.371 R6C4C.C0 to R6C4C.F0 <A href="#@comp:myIwm/SLICE_36">myIwm/SLICE_36</A>
|
||||
ROUTE 5 1.138<A href="#@net:myIwm/n133:R6C4C.F0:R5C4D.B1:1.138"> R6C4C.F0 to R5C4D.B1 </A> <A href="#@net:myIwm/n133">myIwm/n133</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 1 0.497<A href="#@net:myIwm/n1516:R5C4D.F1:R5C4D.C0:0.497"> R5C4D.F1 to R5C4D.C0 </A> <A href="#@net:myIwm/n1516">myIwm/n1516</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.C0 to R5C4D.F0 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 3 0.657<A href="#@net:myIwm/n65:R5C4D.F0:R5C4C.D1:0.657"> R5C4D.F0 to R5C4C.D1 </A> <A href="#@net:myIwm/n65">myIwm/n65</A>
|
||||
CTOF_DEL --- 0.371 R5C4C.D1 to R5C4C.F1 <A href="#@comp:myIwm/SLICE_27">myIwm/SLICE_27</A>
|
||||
ROUTE 7 1.946<A href="#@net:myIwm/n395:R5C4C.F1:R4C5C.B1:1.946"> R5C4C.F1 to R4C5C.B1 </A> <A href="#@net:myIwm/n395">myIwm/n395</A>
|
||||
CTOOFX_DEL --- 0.615 R4C5C.B1 to R4C5C.OFX0 <A href="#@comp:myIwm/SLICE_26">myIwm/SLICE_26</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/shifter_7_N_85_7:R4C5C.OFX0:R4C5C.DI0:0.000"> R4C5C.OFX0 to R4C5C.DI0 </A> <A href="#@net:myIwm/shifter_7_N_85_7">myIwm/shifter_7_N_85_7</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
9.378 (32.3% logic, 67.7% route), 7 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R7C4A.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_5:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R7C4A.CLK:1.353"> 36.PADDI to R7C4A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R4C5C.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_26:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R4C5C.CLK:1.353"> 36.PADDI to R4C5C.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#FF0000>
|
||||
|
||||
Error: The following path exceeds requirements by 6.286ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_4">myIwm/bitTimer__i1</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_26">myIwm/shifter_i0_i7</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 9.249ns (32.8% logic, 67.2% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.249ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_26 exceeds
|
||||
3.144ns delay constraint less
|
||||
0.000ns skew and
|
||||
0.181ns DIN_SET requirement (totaling 2.963ns) by 6.286ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.560,R6C4D.CLK,R6C4D.Q1,myIwm/SLICE_4:ROUTE, 1.080,R6C4D.Q1,R6C3D.A0,myIwm/bitTimer_1:CTOF_DEL, 0.371,R6C3D.A0,R6C3D.F0,myIwm/SLICE_51:ROUTE, 0.901,R6C3D.F0,R6C4C.C0,myIwm/n6:CTOF_DEL, 0.371,R6C4C.C0,R6C4C.F0,myIwm/SLICE_36:ROUTE, 1.138,R6C4C.F0,R5C4D.B1,myIwm/n133:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,myIwm/SLICE_35:ROUTE, 0.497,R5C4D.F1,R5C4D.C0,myIwm/n1516:CTOF_DEL, 0.371,R5C4D.C0,R5C4D.F0,myIwm/SLICE_35:ROUTE, 0.657,R5C4D.F0,R5C4C.D1,myIwm/n65:CTOF_DEL, 0.371,R5C4C.D1,R5C4C.F1,myIwm/SLICE_27:ROUTE, 1.946,R5C4C.F1,R4C5C.B1,myIwm/n395:CTOOFX_DEL, 0.615,R4C5C.B1,R4C5C.OFX0,myIwm/SLICE_26:ROUTE, 0.000,R4C5C.OFX0,R4C5C.DI0,myIwm/shifter_7_N_85_7">Data path</A> myIwm/SLICE_4 to myIwm/SLICE_26:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 R6C4D.CLK to R6C4D.Q1 <A href="#@comp:myIwm/SLICE_4">myIwm/SLICE_4</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 8 1.080<A href="#@net:myIwm/bitTimer_1:R6C4D.Q1:R6C3D.A0:1.080"> R6C4D.Q1 to R6C3D.A0 </A> <A href="#@net:myIwm/bitTimer_1">myIwm/bitTimer_1</A>
|
||||
CTOF_DEL --- 0.371 R6C3D.A0 to R6C3D.F0 <A href="#@comp:myIwm/SLICE_51">myIwm/SLICE_51</A>
|
||||
ROUTE 2 0.901<A href="#@net:myIwm/n6:R6C3D.F0:R6C4C.C0:0.901"> R6C3D.F0 to R6C4C.C0 </A> <A href="#@net:myIwm/n6">myIwm/n6</A>
|
||||
CTOF_DEL --- 0.371 R6C4C.C0 to R6C4C.F0 <A href="#@comp:myIwm/SLICE_36">myIwm/SLICE_36</A>
|
||||
ROUTE 5 1.138<A href="#@net:myIwm/n133:R6C4C.F0:R5C4D.B1:1.138"> R6C4C.F0 to R5C4D.B1 </A> <A href="#@net:myIwm/n133">myIwm/n133</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 1 0.497<A href="#@net:myIwm/n1516:R5C4D.F1:R5C4D.C0:0.497"> R5C4D.F1 to R5C4D.C0 </A> <A href="#@net:myIwm/n1516">myIwm/n1516</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.C0 to R5C4D.F0 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 3 0.657<A href="#@net:myIwm/n65:R5C4D.F0:R5C4C.D1:0.657"> R5C4D.F0 to R5C4C.D1 </A> <A href="#@net:myIwm/n65">myIwm/n65</A>
|
||||
CTOF_DEL --- 0.371 R5C4C.D1 to R5C4C.F1 <A href="#@comp:myIwm/SLICE_27">myIwm/SLICE_27</A>
|
||||
ROUTE 7 1.946<A href="#@net:myIwm/n395:R5C4C.F1:R4C5C.B1:1.946"> R5C4C.F1 to R4C5C.B1 </A> <A href="#@net:myIwm/n395">myIwm/n395</A>
|
||||
CTOOFX_DEL --- 0.615 R4C5C.B1 to R4C5C.OFX0 <A href="#@comp:myIwm/SLICE_26">myIwm/SLICE_26</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/shifter_7_N_85_7:R4C5C.OFX0:R4C5C.DI0:0.000"> R4C5C.OFX0 to R4C5C.DI0 </A> <A href="#@net:myIwm/shifter_7_N_85_7">myIwm/shifter_7_N_85_7</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
9.249 (32.8% logic, 67.2% route), 7 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R6C4D.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_4:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R6C4D.CLK:1.353"> 36.PADDI to R6C4D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R4C5C.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_26:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R4C5C.CLK:1.353"> 36.PADDI to R4C5C.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#FF0000>
|
||||
|
||||
Error: The following path exceeds requirements by 5.997ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_5">myIwm/bitTimer__i2</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_24">myIwm/shifter_i0_i5</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 8.960ns (33.8% logic, 66.2% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.960ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_24 exceeds
|
||||
3.144ns delay constraint less
|
||||
0.000ns skew and
|
||||
0.181ns DIN_SET requirement (totaling 2.963ns) by 5.997ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.560,R7C4A.CLK,R7C4A.Q0,myIwm/SLICE_5:ROUTE, 1.209,R7C4A.Q0,R6C3D.D0,myIwm/bitTimer_2:CTOF_DEL, 0.371,R6C3D.D0,R6C3D.F0,myIwm/SLICE_51:ROUTE, 0.901,R6C3D.F0,R6C4C.C0,myIwm/n6:CTOF_DEL, 0.371,R6C4C.C0,R6C4C.F0,myIwm/SLICE_36:ROUTE, 1.138,R6C4C.F0,R5C4D.B1,myIwm/n133:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,myIwm/SLICE_35:ROUTE, 0.497,R5C4D.F1,R5C4D.C0,myIwm/n1516:CTOF_DEL, 0.371,R5C4D.C0,R5C4D.F0,myIwm/SLICE_35:ROUTE, 0.657,R5C4D.F0,R5C4C.D1,myIwm/n65:CTOF_DEL, 0.371,R5C4C.D1,R5C4C.F1,myIwm/SLICE_27:ROUTE, 1.528,R5C4C.F1,R4C5B.A1,myIwm/n395:CTOOFX_DEL, 0.615,R4C5B.A1,R4C5B.OFX0,myIwm/SLICE_24:ROUTE, 0.000,R4C5B.OFX0,R4C5B.DI0,myIwm/shifter_7_N_85_5">Data path</A> myIwm/SLICE_5 to myIwm/SLICE_24:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 R7C4A.CLK to R7C4A.Q0 <A href="#@comp:myIwm/SLICE_5">myIwm/SLICE_5</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 7 1.209<A href="#@net:myIwm/bitTimer_2:R7C4A.Q0:R6C3D.D0:1.209"> R7C4A.Q0 to R6C3D.D0 </A> <A href="#@net:myIwm/bitTimer_2">myIwm/bitTimer_2</A>
|
||||
CTOF_DEL --- 0.371 R6C3D.D0 to R6C3D.F0 <A href="#@comp:myIwm/SLICE_51">myIwm/SLICE_51</A>
|
||||
ROUTE 2 0.901<A href="#@net:myIwm/n6:R6C3D.F0:R6C4C.C0:0.901"> R6C3D.F0 to R6C4C.C0 </A> <A href="#@net:myIwm/n6">myIwm/n6</A>
|
||||
CTOF_DEL --- 0.371 R6C4C.C0 to R6C4C.F0 <A href="#@comp:myIwm/SLICE_36">myIwm/SLICE_36</A>
|
||||
ROUTE 5 1.138<A href="#@net:myIwm/n133:R6C4C.F0:R5C4D.B1:1.138"> R6C4C.F0 to R5C4D.B1 </A> <A href="#@net:myIwm/n133">myIwm/n133</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 1 0.497<A href="#@net:myIwm/n1516:R5C4D.F1:R5C4D.C0:0.497"> R5C4D.F1 to R5C4D.C0 </A> <A href="#@net:myIwm/n1516">myIwm/n1516</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.C0 to R5C4D.F0 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 3 0.657<A href="#@net:myIwm/n65:R5C4D.F0:R5C4C.D1:0.657"> R5C4D.F0 to R5C4C.D1 </A> <A href="#@net:myIwm/n65">myIwm/n65</A>
|
||||
CTOF_DEL --- 0.371 R5C4C.D1 to R5C4C.F1 <A href="#@comp:myIwm/SLICE_27">myIwm/SLICE_27</A>
|
||||
ROUTE 7 1.528<A href="#@net:myIwm/n395:R5C4C.F1:R4C5B.A1:1.528"> R5C4C.F1 to R4C5B.A1 </A> <A href="#@net:myIwm/n395">myIwm/n395</A>
|
||||
CTOOFX_DEL --- 0.615 R4C5B.A1 to R4C5B.OFX0 <A href="#@comp:myIwm/SLICE_24">myIwm/SLICE_24</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/shifter_7_N_85_5:R4C5B.OFX0:R4C5B.DI0:0.000"> R4C5B.OFX0 to R4C5B.DI0 </A> <A href="#@net:myIwm/shifter_7_N_85_5">myIwm/shifter_7_N_85_5</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
8.960 (33.8% logic, 66.2% route), 7 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R7C4A.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_5:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R7C4A.CLK:1.353"> 36.PADDI to R7C4A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R4C5B.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_24:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R4C5B.CLK:1.353"> 36.PADDI to R4C5B.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#FF0000>
|
||||
|
||||
Error: The following path exceeds requirements by 5.997ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_5">myIwm/bitTimer__i2</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_25">myIwm/shifter_i0_i6</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 8.960ns (33.8% logic, 66.2% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.960ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_25 exceeds
|
||||
3.144ns delay constraint less
|
||||
0.000ns skew and
|
||||
0.181ns DIN_SET requirement (totaling 2.963ns) by 5.997ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.560,R7C4A.CLK,R7C4A.Q0,myIwm/SLICE_5:ROUTE, 1.209,R7C4A.Q0,R6C3D.D0,myIwm/bitTimer_2:CTOF_DEL, 0.371,R6C3D.D0,R6C3D.F0,myIwm/SLICE_51:ROUTE, 0.901,R6C3D.F0,R6C4C.C0,myIwm/n6:CTOF_DEL, 0.371,R6C4C.C0,R6C4C.F0,myIwm/SLICE_36:ROUTE, 1.138,R6C4C.F0,R5C4D.B1,myIwm/n133:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,myIwm/SLICE_35:ROUTE, 0.497,R5C4D.F1,R5C4D.C0,myIwm/n1516:CTOF_DEL, 0.371,R5C4D.C0,R5C4D.F0,myIwm/SLICE_35:ROUTE, 0.657,R5C4D.F0,R5C4C.D1,myIwm/n65:CTOF_DEL, 0.371,R5C4C.D1,R5C4C.F1,myIwm/SLICE_27:ROUTE, 1.528,R5C4C.F1,R4C5D.A1,myIwm/n395:CTOOFX_DEL, 0.615,R4C5D.A1,R4C5D.OFX0,myIwm/SLICE_25:ROUTE, 0.000,R4C5D.OFX0,R4C5D.DI0,myIwm/shifter_7_N_85_6">Data path</A> myIwm/SLICE_5 to myIwm/SLICE_25:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 R7C4A.CLK to R7C4A.Q0 <A href="#@comp:myIwm/SLICE_5">myIwm/SLICE_5</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 7 1.209<A href="#@net:myIwm/bitTimer_2:R7C4A.Q0:R6C3D.D0:1.209"> R7C4A.Q0 to R6C3D.D0 </A> <A href="#@net:myIwm/bitTimer_2">myIwm/bitTimer_2</A>
|
||||
CTOF_DEL --- 0.371 R6C3D.D0 to R6C3D.F0 <A href="#@comp:myIwm/SLICE_51">myIwm/SLICE_51</A>
|
||||
ROUTE 2 0.901<A href="#@net:myIwm/n6:R6C3D.F0:R6C4C.C0:0.901"> R6C3D.F0 to R6C4C.C0 </A> <A href="#@net:myIwm/n6">myIwm/n6</A>
|
||||
CTOF_DEL --- 0.371 R6C4C.C0 to R6C4C.F0 <A href="#@comp:myIwm/SLICE_36">myIwm/SLICE_36</A>
|
||||
ROUTE 5 1.138<A href="#@net:myIwm/n133:R6C4C.F0:R5C4D.B1:1.138"> R6C4C.F0 to R5C4D.B1 </A> <A href="#@net:myIwm/n133">myIwm/n133</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 1 0.497<A href="#@net:myIwm/n1516:R5C4D.F1:R5C4D.C0:0.497"> R5C4D.F1 to R5C4D.C0 </A> <A href="#@net:myIwm/n1516">myIwm/n1516</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.C0 to R5C4D.F0 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 3 0.657<A href="#@net:myIwm/n65:R5C4D.F0:R5C4C.D1:0.657"> R5C4D.F0 to R5C4C.D1 </A> <A href="#@net:myIwm/n65">myIwm/n65</A>
|
||||
CTOF_DEL --- 0.371 R5C4C.D1 to R5C4C.F1 <A href="#@comp:myIwm/SLICE_27">myIwm/SLICE_27</A>
|
||||
ROUTE 7 1.528<A href="#@net:myIwm/n395:R5C4C.F1:R4C5D.A1:1.528"> R5C4C.F1 to R4C5D.A1 </A> <A href="#@net:myIwm/n395">myIwm/n395</A>
|
||||
CTOOFX_DEL --- 0.615 R4C5D.A1 to R4C5D.OFX0 <A href="#@comp:myIwm/SLICE_25">myIwm/SLICE_25</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/shifter_7_N_85_6:R4C5D.OFX0:R4C5D.DI0:0.000"> R4C5D.OFX0 to R4C5D.DI0 </A> <A href="#@net:myIwm/shifter_7_N_85_6">myIwm/shifter_7_N_85_6</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
8.960 (33.8% logic, 66.2% route), 7 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R7C4A.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_5:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R7C4A.CLK:1.353"> 36.PADDI to R7C4A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R4C5D.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_25:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R4C5D.CLK:1.353"> 36.PADDI to R4C5D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#FF0000>
|
||||
|
||||
Error: The following path exceeds requirements by 5.868ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_4">myIwm/bitTimer__i1</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_24">myIwm/shifter_i0_i5</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 8.831ns (34.3% logic, 65.7% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.831ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_24 exceeds
|
||||
3.144ns delay constraint less
|
||||
0.000ns skew and
|
||||
0.181ns DIN_SET requirement (totaling 2.963ns) by 5.868ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.560,R6C4D.CLK,R6C4D.Q1,myIwm/SLICE_4:ROUTE, 1.080,R6C4D.Q1,R6C3D.A0,myIwm/bitTimer_1:CTOF_DEL, 0.371,R6C3D.A0,R6C3D.F0,myIwm/SLICE_51:ROUTE, 0.901,R6C3D.F0,R6C4C.C0,myIwm/n6:CTOF_DEL, 0.371,R6C4C.C0,R6C4C.F0,myIwm/SLICE_36:ROUTE, 1.138,R6C4C.F0,R5C4D.B1,myIwm/n133:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,myIwm/SLICE_35:ROUTE, 0.497,R5C4D.F1,R5C4D.C0,myIwm/n1516:CTOF_DEL, 0.371,R5C4D.C0,R5C4D.F0,myIwm/SLICE_35:ROUTE, 0.657,R5C4D.F0,R5C4C.D1,myIwm/n65:CTOF_DEL, 0.371,R5C4C.D1,R5C4C.F1,myIwm/SLICE_27:ROUTE, 1.528,R5C4C.F1,R4C5B.A1,myIwm/n395:CTOOFX_DEL, 0.615,R4C5B.A1,R4C5B.OFX0,myIwm/SLICE_24:ROUTE, 0.000,R4C5B.OFX0,R4C5B.DI0,myIwm/shifter_7_N_85_5">Data path</A> myIwm/SLICE_4 to myIwm/SLICE_24:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 R6C4D.CLK to R6C4D.Q1 <A href="#@comp:myIwm/SLICE_4">myIwm/SLICE_4</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 8 1.080<A href="#@net:myIwm/bitTimer_1:R6C4D.Q1:R6C3D.A0:1.080"> R6C4D.Q1 to R6C3D.A0 </A> <A href="#@net:myIwm/bitTimer_1">myIwm/bitTimer_1</A>
|
||||
CTOF_DEL --- 0.371 R6C3D.A0 to R6C3D.F0 <A href="#@comp:myIwm/SLICE_51">myIwm/SLICE_51</A>
|
||||
ROUTE 2 0.901<A href="#@net:myIwm/n6:R6C3D.F0:R6C4C.C0:0.901"> R6C3D.F0 to R6C4C.C0 </A> <A href="#@net:myIwm/n6">myIwm/n6</A>
|
||||
CTOF_DEL --- 0.371 R6C4C.C0 to R6C4C.F0 <A href="#@comp:myIwm/SLICE_36">myIwm/SLICE_36</A>
|
||||
ROUTE 5 1.138<A href="#@net:myIwm/n133:R6C4C.F0:R5C4D.B1:1.138"> R6C4C.F0 to R5C4D.B1 </A> <A href="#@net:myIwm/n133">myIwm/n133</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 1 0.497<A href="#@net:myIwm/n1516:R5C4D.F1:R5C4D.C0:0.497"> R5C4D.F1 to R5C4D.C0 </A> <A href="#@net:myIwm/n1516">myIwm/n1516</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.C0 to R5C4D.F0 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 3 0.657<A href="#@net:myIwm/n65:R5C4D.F0:R5C4C.D1:0.657"> R5C4D.F0 to R5C4C.D1 </A> <A href="#@net:myIwm/n65">myIwm/n65</A>
|
||||
CTOF_DEL --- 0.371 R5C4C.D1 to R5C4C.F1 <A href="#@comp:myIwm/SLICE_27">myIwm/SLICE_27</A>
|
||||
ROUTE 7 1.528<A href="#@net:myIwm/n395:R5C4C.F1:R4C5B.A1:1.528"> R5C4C.F1 to R4C5B.A1 </A> <A href="#@net:myIwm/n395">myIwm/n395</A>
|
||||
CTOOFX_DEL --- 0.615 R4C5B.A1 to R4C5B.OFX0 <A href="#@comp:myIwm/SLICE_24">myIwm/SLICE_24</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/shifter_7_N_85_5:R4C5B.OFX0:R4C5B.DI0:0.000"> R4C5B.OFX0 to R4C5B.DI0 </A> <A href="#@net:myIwm/shifter_7_N_85_5">myIwm/shifter_7_N_85_5</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
8.831 (34.3% logic, 65.7% route), 7 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R6C4D.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_4:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R6C4D.CLK:1.353"> 36.PADDI to R6C4D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R4C5B.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_24:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R4C5B.CLK:1.353"> 36.PADDI to R4C5B.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#FF0000>
|
||||
|
||||
Error: The following path exceeds requirements by 5.868ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_4">myIwm/bitTimer__i1</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_25">myIwm/shifter_i0_i6</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 8.831ns (34.3% logic, 65.7% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.831ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_25 exceeds
|
||||
3.144ns delay constraint less
|
||||
0.000ns skew and
|
||||
0.181ns DIN_SET requirement (totaling 2.963ns) by 5.868ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.560,R6C4D.CLK,R6C4D.Q1,myIwm/SLICE_4:ROUTE, 1.080,R6C4D.Q1,R6C3D.A0,myIwm/bitTimer_1:CTOF_DEL, 0.371,R6C3D.A0,R6C3D.F0,myIwm/SLICE_51:ROUTE, 0.901,R6C3D.F0,R6C4C.C0,myIwm/n6:CTOF_DEL, 0.371,R6C4C.C0,R6C4C.F0,myIwm/SLICE_36:ROUTE, 1.138,R6C4C.F0,R5C4D.B1,myIwm/n133:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,myIwm/SLICE_35:ROUTE, 0.497,R5C4D.F1,R5C4D.C0,myIwm/n1516:CTOF_DEL, 0.371,R5C4D.C0,R5C4D.F0,myIwm/SLICE_35:ROUTE, 0.657,R5C4D.F0,R5C4C.D1,myIwm/n65:CTOF_DEL, 0.371,R5C4C.D1,R5C4C.F1,myIwm/SLICE_27:ROUTE, 1.528,R5C4C.F1,R4C5D.A1,myIwm/n395:CTOOFX_DEL, 0.615,R4C5D.A1,R4C5D.OFX0,myIwm/SLICE_25:ROUTE, 0.000,R4C5D.OFX0,R4C5D.DI0,myIwm/shifter_7_N_85_6">Data path</A> myIwm/SLICE_4 to myIwm/SLICE_25:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 R6C4D.CLK to R6C4D.Q1 <A href="#@comp:myIwm/SLICE_4">myIwm/SLICE_4</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 8 1.080<A href="#@net:myIwm/bitTimer_1:R6C4D.Q1:R6C3D.A0:1.080"> R6C4D.Q1 to R6C3D.A0 </A> <A href="#@net:myIwm/bitTimer_1">myIwm/bitTimer_1</A>
|
||||
CTOF_DEL --- 0.371 R6C3D.A0 to R6C3D.F0 <A href="#@comp:myIwm/SLICE_51">myIwm/SLICE_51</A>
|
||||
ROUTE 2 0.901<A href="#@net:myIwm/n6:R6C3D.F0:R6C4C.C0:0.901"> R6C3D.F0 to R6C4C.C0 </A> <A href="#@net:myIwm/n6">myIwm/n6</A>
|
||||
CTOF_DEL --- 0.371 R6C4C.C0 to R6C4C.F0 <A href="#@comp:myIwm/SLICE_36">myIwm/SLICE_36</A>
|
||||
ROUTE 5 1.138<A href="#@net:myIwm/n133:R6C4C.F0:R5C4D.B1:1.138"> R6C4C.F0 to R5C4D.B1 </A> <A href="#@net:myIwm/n133">myIwm/n133</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 1 0.497<A href="#@net:myIwm/n1516:R5C4D.F1:R5C4D.C0:0.497"> R5C4D.F1 to R5C4D.C0 </A> <A href="#@net:myIwm/n1516">myIwm/n1516</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.C0 to R5C4D.F0 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 3 0.657<A href="#@net:myIwm/n65:R5C4D.F0:R5C4C.D1:0.657"> R5C4D.F0 to R5C4C.D1 </A> <A href="#@net:myIwm/n65">myIwm/n65</A>
|
||||
CTOF_DEL --- 0.371 R5C4C.D1 to R5C4C.F1 <A href="#@comp:myIwm/SLICE_27">myIwm/SLICE_27</A>
|
||||
ROUTE 7 1.528<A href="#@net:myIwm/n395:R5C4C.F1:R4C5D.A1:1.528"> R5C4C.F1 to R4C5D.A1 </A> <A href="#@net:myIwm/n395">myIwm/n395</A>
|
||||
CTOOFX_DEL --- 0.615 R4C5D.A1 to R4C5D.OFX0 <A href="#@comp:myIwm/SLICE_25">myIwm/SLICE_25</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/shifter_7_N_85_6:R4C5D.OFX0:R4C5D.DI0:0.000"> R4C5D.OFX0 to R4C5D.DI0 </A> <A href="#@net:myIwm/shifter_7_N_85_6">myIwm/shifter_7_N_85_6</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
8.831 (34.3% logic, 65.7% route), 7 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R6C4D.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_4:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R6C4D.CLK:1.353"> 36.PADDI to R6C4D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R4C5D.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_25:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R4C5D.CLK:1.353"> 36.PADDI to R4C5D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#FF0000>
|
||||
|
||||
Error: The following path exceeds requirements by 5.861ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_5">myIwm/bitTimer__i2</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_26">myIwm/shifter_i0_i7</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 8.824ns (34.3% logic, 65.7% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.824ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_26 exceeds
|
||||
3.144ns delay constraint less
|
||||
0.000ns skew and
|
||||
0.181ns DIN_SET requirement (totaling 2.963ns) by 5.861ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.560,R7C4A.CLK,R7C4A.Q0,myIwm/SLICE_5:ROUTE, 1.209,R7C4A.Q0,R6C3D.D1,myIwm/bitTimer_2:CTOF_DEL, 0.371,R6C3D.D1,R6C3D.F1,myIwm/SLICE_51:ROUTE, 0.636,R6C3D.F1,R6C4A.A0,myIwm/n4:CTOF_DEL, 0.371,R6C4A.A0,R6C4A.F0,myIwm/SLICE_37:ROUTE, 0.652,R6C4A.F0,R6C4A.A1,myIwm/n123:CTOF_DEL, 0.371,R6C4A.A1,R6C4A.F1,myIwm/SLICE_37:ROUTE, 0.694,R6C4A.F1,R5C4D.D0,myIwm/n59:CTOF_DEL, 0.371,R5C4D.D0,R5C4D.F0,myIwm/SLICE_35:ROUTE, 0.657,R5C4D.F0,R5C4C.D1,myIwm/n65:CTOF_DEL, 0.371,R5C4C.D1,R5C4C.F1,myIwm/SLICE_27:ROUTE, 1.946,R5C4C.F1,R4C5C.B1,myIwm/n395:CTOOFX_DEL, 0.615,R4C5C.B1,R4C5C.OFX0,myIwm/SLICE_26:ROUTE, 0.000,R4C5C.OFX0,R4C5C.DI0,myIwm/shifter_7_N_85_7">Data path</A> myIwm/SLICE_5 to myIwm/SLICE_26:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 R7C4A.CLK to R7C4A.Q0 <A href="#@comp:myIwm/SLICE_5">myIwm/SLICE_5</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 7 1.209<A href="#@net:myIwm/bitTimer_2:R7C4A.Q0:R6C3D.D1:1.209"> R7C4A.Q0 to R6C3D.D1 </A> <A href="#@net:myIwm/bitTimer_2">myIwm/bitTimer_2</A>
|
||||
CTOF_DEL --- 0.371 R6C3D.D1 to R6C3D.F1 <A href="#@comp:myIwm/SLICE_51">myIwm/SLICE_51</A>
|
||||
ROUTE 1 0.636<A href="#@net:myIwm/n4:R6C3D.F1:R6C4A.A0:0.636"> R6C3D.F1 to R6C4A.A0 </A> <A href="#@net:myIwm/n4">myIwm/n4</A>
|
||||
CTOF_DEL --- 0.371 R6C4A.A0 to R6C4A.F0 <A href="#@comp:myIwm/SLICE_37">myIwm/SLICE_37</A>
|
||||
ROUTE 3 0.652<A href="#@net:myIwm/n123:R6C4A.F0:R6C4A.A1:0.652"> R6C4A.F0 to R6C4A.A1 </A> <A href="#@net:myIwm/n123">myIwm/n123</A>
|
||||
CTOF_DEL --- 0.371 R6C4A.A1 to R6C4A.F1 <A href="#@comp:myIwm/SLICE_37">myIwm/SLICE_37</A>
|
||||
ROUTE 1 0.694<A href="#@net:myIwm/n59:R6C4A.F1:R5C4D.D0:0.694"> R6C4A.F1 to R5C4D.D0 </A> <A href="#@net:myIwm/n59">myIwm/n59</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.D0 to R5C4D.F0 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 3 0.657<A href="#@net:myIwm/n65:R5C4D.F0:R5C4C.D1:0.657"> R5C4D.F0 to R5C4C.D1 </A> <A href="#@net:myIwm/n65">myIwm/n65</A>
|
||||
CTOF_DEL --- 0.371 R5C4C.D1 to R5C4C.F1 <A href="#@comp:myIwm/SLICE_27">myIwm/SLICE_27</A>
|
||||
ROUTE 7 1.946<A href="#@net:myIwm/n395:R5C4C.F1:R4C5C.B1:1.946"> R5C4C.F1 to R4C5C.B1 </A> <A href="#@net:myIwm/n395">myIwm/n395</A>
|
||||
CTOOFX_DEL --- 0.615 R4C5C.B1 to R4C5C.OFX0 <A href="#@comp:myIwm/SLICE_26">myIwm/SLICE_26</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/shifter_7_N_85_7:R4C5C.OFX0:R4C5C.DI0:0.000"> R4C5C.OFX0 to R4C5C.DI0 </A> <A href="#@net:myIwm/shifter_7_N_85_7">myIwm/shifter_7_N_85_7</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
8.824 (34.3% logic, 65.7% route), 7 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R7C4A.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_5:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R7C4A.CLK:1.353"> 36.PADDI to R7C4A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R4C5C.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_26:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R4C5C.CLK:1.353"> 36.PADDI to R4C5C.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#FF0000>
|
||||
|
||||
Error: The following path exceeds requirements by 5.732ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_4">myIwm/bitTimer__i1</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_26">myIwm/shifter_i0_i7</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 8.695ns (34.8% logic, 65.2% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.695ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_26 exceeds
|
||||
3.144ns delay constraint less
|
||||
0.000ns skew and
|
||||
0.181ns DIN_SET requirement (totaling 2.963ns) by 5.732ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.560,R6C4D.CLK,R6C4D.Q1,myIwm/SLICE_4:ROUTE, 1.080,R6C4D.Q1,R6C3D.A1,myIwm/bitTimer_1:CTOF_DEL, 0.371,R6C3D.A1,R6C3D.F1,myIwm/SLICE_51:ROUTE, 0.636,R6C3D.F1,R6C4A.A0,myIwm/n4:CTOF_DEL, 0.371,R6C4A.A0,R6C4A.F0,myIwm/SLICE_37:ROUTE, 0.652,R6C4A.F0,R6C4A.A1,myIwm/n123:CTOF_DEL, 0.371,R6C4A.A1,R6C4A.F1,myIwm/SLICE_37:ROUTE, 0.694,R6C4A.F1,R5C4D.D0,myIwm/n59:CTOF_DEL, 0.371,R5C4D.D0,R5C4D.F0,myIwm/SLICE_35:ROUTE, 0.657,R5C4D.F0,R5C4C.D1,myIwm/n65:CTOF_DEL, 0.371,R5C4C.D1,R5C4C.F1,myIwm/SLICE_27:ROUTE, 1.946,R5C4C.F1,R4C5C.B1,myIwm/n395:CTOOFX_DEL, 0.615,R4C5C.B1,R4C5C.OFX0,myIwm/SLICE_26:ROUTE, 0.000,R4C5C.OFX0,R4C5C.DI0,myIwm/shifter_7_N_85_7">Data path</A> myIwm/SLICE_4 to myIwm/SLICE_26:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 R6C4D.CLK to R6C4D.Q1 <A href="#@comp:myIwm/SLICE_4">myIwm/SLICE_4</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 8 1.080<A href="#@net:myIwm/bitTimer_1:R6C4D.Q1:R6C3D.A1:1.080"> R6C4D.Q1 to R6C3D.A1 </A> <A href="#@net:myIwm/bitTimer_1">myIwm/bitTimer_1</A>
|
||||
CTOF_DEL --- 0.371 R6C3D.A1 to R6C3D.F1 <A href="#@comp:myIwm/SLICE_51">myIwm/SLICE_51</A>
|
||||
ROUTE 1 0.636<A href="#@net:myIwm/n4:R6C3D.F1:R6C4A.A0:0.636"> R6C3D.F1 to R6C4A.A0 </A> <A href="#@net:myIwm/n4">myIwm/n4</A>
|
||||
CTOF_DEL --- 0.371 R6C4A.A0 to R6C4A.F0 <A href="#@comp:myIwm/SLICE_37">myIwm/SLICE_37</A>
|
||||
ROUTE 3 0.652<A href="#@net:myIwm/n123:R6C4A.F0:R6C4A.A1:0.652"> R6C4A.F0 to R6C4A.A1 </A> <A href="#@net:myIwm/n123">myIwm/n123</A>
|
||||
CTOF_DEL --- 0.371 R6C4A.A1 to R6C4A.F1 <A href="#@comp:myIwm/SLICE_37">myIwm/SLICE_37</A>
|
||||
ROUTE 1 0.694<A href="#@net:myIwm/n59:R6C4A.F1:R5C4D.D0:0.694"> R6C4A.F1 to R5C4D.D0 </A> <A href="#@net:myIwm/n59">myIwm/n59</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.D0 to R5C4D.F0 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 3 0.657<A href="#@net:myIwm/n65:R5C4D.F0:R5C4C.D1:0.657"> R5C4D.F0 to R5C4C.D1 </A> <A href="#@net:myIwm/n65">myIwm/n65</A>
|
||||
CTOF_DEL --- 0.371 R5C4C.D1 to R5C4C.F1 <A href="#@comp:myIwm/SLICE_27">myIwm/SLICE_27</A>
|
||||
ROUTE 7 1.946<A href="#@net:myIwm/n395:R5C4C.F1:R4C5C.B1:1.946"> R5C4C.F1 to R4C5C.B1 </A> <A href="#@net:myIwm/n395">myIwm/n395</A>
|
||||
CTOOFX_DEL --- 0.615 R4C5C.B1 to R4C5C.OFX0 <A href="#@comp:myIwm/SLICE_26">myIwm/SLICE_26</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/shifter_7_N_85_7:R4C5C.OFX0:R4C5C.DI0:0.000"> R4C5C.OFX0 to R4C5C.DI0 </A> <A href="#@net:myIwm/shifter_7_N_85_7">myIwm/shifter_7_N_85_7</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
8.695 (34.8% logic, 65.2% route), 7 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R6C4D.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_4:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R6C4D.CLK:1.353"> 36.PADDI to R6C4D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R4C5C.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_26:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R4C5C.CLK:1.353"> 36.PADDI to R4C5C.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#FF0000>
|
||||
|
||||
Error: The following path exceeds requirements by 5.579ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_5">myIwm/bitTimer__i2</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_21">myIwm/shifter_i0_i2</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 8.542ns (35.5% logic, 64.5% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.542ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_21 exceeds
|
||||
3.144ns delay constraint less
|
||||
0.000ns skew and
|
||||
0.181ns DIN_SET requirement (totaling 2.963ns) by 5.579ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.560,R7C4A.CLK,R7C4A.Q0,myIwm/SLICE_5:ROUTE, 1.209,R7C4A.Q0,R6C3D.D0,myIwm/bitTimer_2:CTOF_DEL, 0.371,R6C3D.D0,R6C3D.F0,myIwm/SLICE_51:ROUTE, 0.901,R6C3D.F0,R6C4C.C0,myIwm/n6:CTOF_DEL, 0.371,R6C4C.C0,R6C4C.F0,myIwm/SLICE_36:ROUTE, 1.138,R6C4C.F0,R5C4D.B1,myIwm/n133:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,myIwm/SLICE_35:ROUTE, 0.497,R5C4D.F1,R5C4D.C0,myIwm/n1516:CTOF_DEL, 0.371,R5C4D.C0,R5C4D.F0,myIwm/SLICE_35:ROUTE, 0.657,R5C4D.F0,R5C4C.D1,myIwm/n65:CTOF_DEL, 0.371,R5C4C.D1,R5C4C.F1,myIwm/SLICE_27:ROUTE, 1.110,R5C4C.F1,R4C4D.B1,myIwm/n395:CTOOFX_DEL, 0.615,R4C4D.B1,R4C4D.OFX0,myIwm/SLICE_21:ROUTE, 0.000,R4C4D.OFX0,R4C4D.DI0,myIwm/shifter_7_N_85_2">Data path</A> myIwm/SLICE_5 to myIwm/SLICE_21:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 R7C4A.CLK to R7C4A.Q0 <A href="#@comp:myIwm/SLICE_5">myIwm/SLICE_5</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 7 1.209<A href="#@net:myIwm/bitTimer_2:R7C4A.Q0:R6C3D.D0:1.209"> R7C4A.Q0 to R6C3D.D0 </A> <A href="#@net:myIwm/bitTimer_2">myIwm/bitTimer_2</A>
|
||||
CTOF_DEL --- 0.371 R6C3D.D0 to R6C3D.F0 <A href="#@comp:myIwm/SLICE_51">myIwm/SLICE_51</A>
|
||||
ROUTE 2 0.901<A href="#@net:myIwm/n6:R6C3D.F0:R6C4C.C0:0.901"> R6C3D.F0 to R6C4C.C0 </A> <A href="#@net:myIwm/n6">myIwm/n6</A>
|
||||
CTOF_DEL --- 0.371 R6C4C.C0 to R6C4C.F0 <A href="#@comp:myIwm/SLICE_36">myIwm/SLICE_36</A>
|
||||
ROUTE 5 1.138<A href="#@net:myIwm/n133:R6C4C.F0:R5C4D.B1:1.138"> R6C4C.F0 to R5C4D.B1 </A> <A href="#@net:myIwm/n133">myIwm/n133</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 1 0.497<A href="#@net:myIwm/n1516:R5C4D.F1:R5C4D.C0:0.497"> R5C4D.F1 to R5C4D.C0 </A> <A href="#@net:myIwm/n1516">myIwm/n1516</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.C0 to R5C4D.F0 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 3 0.657<A href="#@net:myIwm/n65:R5C4D.F0:R5C4C.D1:0.657"> R5C4D.F0 to R5C4C.D1 </A> <A href="#@net:myIwm/n65">myIwm/n65</A>
|
||||
CTOF_DEL --- 0.371 R5C4C.D1 to R5C4C.F1 <A href="#@comp:myIwm/SLICE_27">myIwm/SLICE_27</A>
|
||||
ROUTE 7 1.110<A href="#@net:myIwm/n395:R5C4C.F1:R4C4D.B1:1.110"> R5C4C.F1 to R4C4D.B1 </A> <A href="#@net:myIwm/n395">myIwm/n395</A>
|
||||
CTOOFX_DEL --- 0.615 R4C4D.B1 to R4C4D.OFX0 <A href="#@comp:myIwm/SLICE_21">myIwm/SLICE_21</A>
|
||||
ROUTE 1 0.000<A href="#@net:myIwm/shifter_7_N_85_2:R4C4D.OFX0:R4C4D.DI0:0.000"> R4C4D.OFX0 to R4C4D.DI0 </A> <A href="#@net:myIwm/shifter_7_N_85_2">myIwm/shifter_7_N_85_2</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
8.542 (35.5% logic, 64.5% route), 7 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R7C4A.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_5:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R7C4A.CLK:1.353"> 36.PADDI to R7C4A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R4C4D.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_21:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R4C4D.CLK:1.353"> 36.PADDI to R4C4D.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
<font color=#FF0000>
|
||||
|
||||
Error: The following path exceeds requirements by 5.551ns
|
||||
</font>
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q <A href="#@comp:myIwm/SLICE_5">myIwm/bitTimer__i2</A> (from <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
Destination: FF Data in <A href="#@comp:myIwm/SLICE_26">myIwm/shifter_i0_i7</A> (to <A href="#@net:fclk_c">fclk_c</A> +)
|
||||
|
||||
Delay: 8.451ns (28.6% logic, 71.4% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.451ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_26 exceeds
|
||||
3.144ns delay constraint less
|
||||
0.000ns skew and
|
||||
0.244ns CE_SET requirement (totaling 2.900ns) by 5.551ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:REG_DEL, 0.560,R7C4A.CLK,R7C4A.Q0,myIwm/SLICE_5:ROUTE, 1.209,R7C4A.Q0,R6C3D.D0,myIwm/bitTimer_2:CTOF_DEL, 0.371,R6C3D.D0,R6C3D.F0,myIwm/SLICE_51:ROUTE, 0.901,R6C3D.F0,R6C4C.C0,myIwm/n6:CTOF_DEL, 0.371,R6C4C.C0,R6C4C.F0,myIwm/SLICE_36:ROUTE, 1.138,R6C4C.F0,R5C4D.B1,myIwm/n133:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,myIwm/SLICE_35:ROUTE, 0.497,R5C4D.F1,R5C4D.C0,myIwm/n1516:CTOF_DEL, 0.371,R5C4D.C0,R5C4D.F0,myIwm/SLICE_35:ROUTE, 0.727,R5C4D.F0,R5C4B.B1,myIwm/n65:CTOF_DEL, 0.371,R5C4B.B1,R5C4B.F1,myIwm/SLICE_45:ROUTE, 1.564,R5C4B.F1,R4C5C.CE,myIwm/fclk_c_enable_14">Data path</A> myIwm/SLICE_5 to myIwm/SLICE_26:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 R7C4A.CLK to R7C4A.Q0 <A href="#@comp:myIwm/SLICE_5">myIwm/SLICE_5</A> (from <A href="#@net:fclk_c">fclk_c</A>)
|
||||
ROUTE 7 1.209<A href="#@net:myIwm/bitTimer_2:R7C4A.Q0:R6C3D.D0:1.209"> R7C4A.Q0 to R6C3D.D0 </A> <A href="#@net:myIwm/bitTimer_2">myIwm/bitTimer_2</A>
|
||||
CTOF_DEL --- 0.371 R6C3D.D0 to R6C3D.F0 <A href="#@comp:myIwm/SLICE_51">myIwm/SLICE_51</A>
|
||||
ROUTE 2 0.901<A href="#@net:myIwm/n6:R6C3D.F0:R6C4C.C0:0.901"> R6C3D.F0 to R6C4C.C0 </A> <A href="#@net:myIwm/n6">myIwm/n6</A>
|
||||
CTOF_DEL --- 0.371 R6C4C.C0 to R6C4C.F0 <A href="#@comp:myIwm/SLICE_36">myIwm/SLICE_36</A>
|
||||
ROUTE 5 1.138<A href="#@net:myIwm/n133:R6C4C.F0:R5C4D.B1:1.138"> R6C4C.F0 to R5C4D.B1 </A> <A href="#@net:myIwm/n133">myIwm/n133</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 1 0.497<A href="#@net:myIwm/n1516:R5C4D.F1:R5C4D.C0:0.497"> R5C4D.F1 to R5C4D.C0 </A> <A href="#@net:myIwm/n1516">myIwm/n1516</A>
|
||||
CTOF_DEL --- 0.371 R5C4D.C0 to R5C4D.F0 <A href="#@comp:myIwm/SLICE_35">myIwm/SLICE_35</A>
|
||||
ROUTE 3 0.727<A href="#@net:myIwm/n65:R5C4D.F0:R5C4B.B1:0.727"> R5C4D.F0 to R5C4B.B1 </A> <A href="#@net:myIwm/n65">myIwm/n65</A>
|
||||
CTOF_DEL --- 0.371 R5C4B.B1 to R5C4B.F1 <A href="#@comp:myIwm/SLICE_45">myIwm/SLICE_45</A>
|
||||
ROUTE 8 1.564<A href="#@net:myIwm/fclk_c_enable_14:R5C4B.F1:R4C5C.CE:1.564"> R5C4B.F1 to R4C5C.CE </A> <A href="#@net:myIwm/fclk_c_enable_14">myIwm/fclk_c_enable_14</A> (to <A href="#@net:fclk_c">fclk_c</A>)
|
||||
--------
|
||||
8.451 (28.6% logic, 71.4% route), 6 logic levels.
|
||||
|
||||
Clock Skew Details:
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R7C4A.CLK,fclk_c">Source Clock Path</A> fclk to myIwm/SLICE_5:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R7C4A.CLK:1.353"> 36.PADDI to R7C4A.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
<A href="#@path:FREQUENCY NET 'fclk_c' 318.066000 MHz ;:ROUTE, 1.353,36.PADDI,R4C5C.CLK,fclk_c">Destination Clock Path</A> fclk to myIwm/SLICE_26:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
ROUTE 24 1.353<A href="#@net:fclk_c:36.PADDI:R4C5C.CLK:1.353"> 36.PADDI to R4C5C.CLK </A> <A href="#@net:fclk_c">fclk_c</A>
|
||||
--------
|
||||
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
||||
|
||||
Warning: 104.613MHz is the maximum frequency for this preference.
|
||||
|
||||
<A name="Report Summary"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY NET "fclk_c" 318.066000 MHz ; | 318.066 MHz| 104.613 MHz| 7 *
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
1 preference(marked by "*" above) not met.
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
Critical Nets | Loads| Errors| % of total
|
||||
----------------------------------------------------------------------------
|
||||
myIwm/n65 | 3| 10| 100.00%
|
||||
| | |
|
||||
myIwm/n395 | 7| 9| 90.00%
|
||||
| | |
|
||||
myIwm/n133 | 5| 8| 80.00%
|
||||
| | |
|
||||
myIwm/n6 | 2| 8| 80.00%
|
||||
| | |
|
||||
myIwm/n1516 | 1| 8| 80.00%
|
||||
| | |
|
||||
myIwm/bitTimer_2 | 7| 6| 60.00%
|
||||
| | |
|
||||
myIwm/shifter_7_N_85_7 | 1| 4| 40.00%
|
||||
| | |
|
||||
myIwm/bitTimer_1 | 8| 4| 40.00%
|
||||
| | |
|
||||
myIwm/shifter_7_N_85_6 | 1| 2| 20.00%
|
||||
| | |
|
||||
myIwm/shifter_7_N_85_5 | 1| 2| 20.00%
|
||||
| | |
|
||||
myIwm/n123 | 3| 2| 20.00%
|
||||
| | |
|
||||
myIwm/n4 | 1| 2| 20.00%
|
||||
| | |
|
||||
myIwm/n59 | 1| 2| 20.00%
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
<A name="Clock Domains Analysis"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
||||
------------------------
|
||||
|
||||
Found 3 clocks:
|
||||
|
||||
Clock Domain: <A href="#@net:fclk_c">fclk_c</A> Source: fclk.PAD Loads: 24
|
||||
Covered under: FREQUENCY NET "fclk_c" 318.066000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: <A href="#@net:_devsel_c">_devsel_c</A> Source: _devsel.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: <A href="#@net:_devsel_c">_devsel_c</A> Source: _devsel.PAD Loads: 11
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: <A href="#@net:_iosel_c">_iosel_c</A> Source: _iosel.PAD Loads: 2
|
||||
No transfer within this clock domain is found
|
||||
|
||||
|
||||
Timing summary (Setup):
|
||||
---------------
|
||||
|
||||
Timing errors: 10 Score: 59154
|
||||
Cumulative negative slack: 59154
|
||||
|
||||
Constraints cover 841 paths, 1 nets, and 319 connections (64.84% coverage)
|
||||
|
||||
50
lattice/fpgatop/codeROM_lse.twr
Normal file
50
lattice/fpgatop/codeROM_lse.twr
Normal file
@ -0,0 +1,50 @@
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice Synthesis Timing Report, Version
|
||||
Thu Jul 27 11:14:19 2017
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Design: codeROM
|
||||
Constraint file:
|
||||
Report level: verbose report, limited to 3 items per constraint
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 1000.000000 -name clk0 [get_nets OutClock_c]
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Timing Report Summary
|
||||
--------------
|
||||
--------------------------------------------------------------------------------
|
||||
Constraint | Constraint| Actual|Levels
|
||||
--------------------------------------------------------------------------------
|
||||
| | |
|
||||
create_clock -period 1000.000000 -name | | |
|
||||
clk0 [get_nets OutClock_c] | -| -| 0
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
All constraints were met.
|
||||
|
||||
|
||||
|
||||
Timing summary:
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
|
||||
Constraints cover 0 paths, 0 nets, and 2 connections (5.6% coverage)
|
||||
|
||||
|
||||
Peak memory: 48201728 bytes, TRCE: 1507328 bytes, DLYMAN: 0 bytes
|
||||
CPU_TIME_REPORT: 0 secs
|
||||
184
lattice/fpgatop/codeROM_prim.v
Normal file
184
lattice/fpgatop/codeROM_prim.v
Normal file
@ -0,0 +1,184 @@
|
||||
// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.9.0.99.2
|
||||
// Netlist written on Thu Jul 27 11:14:19 2017
|
||||
//
|
||||
// Verilog Description of module codeROM
|
||||
//
|
||||
|
||||
module codeROM (Address, OutClock, OutClockEn, Reset, Q) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ; // c:/users/chamberlin/documents/liron/lattice/coderom.v(8[8:15])
|
||||
input [10:0]Address; // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
|
||||
input OutClock; // c:/users/chamberlin/documents/liron/lattice/coderom.v(10[16:24])
|
||||
input OutClockEn; // c:/users/chamberlin/documents/liron/lattice/coderom.v(11[16:26])
|
||||
input Reset; // c:/users/chamberlin/documents/liron/lattice/coderom.v(12[16:21])
|
||||
output [7:0]Q; // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
|
||||
|
||||
wire OutClock_c /* synthesis is_clock=1 */ ; // c:/users/chamberlin/documents/liron/lattice/coderom.v(10[16:24])
|
||||
|
||||
wire Address_c_10, Address_c_9, Address_c_8, Address_c_7, Address_c_6,
|
||||
Address_c_5, Address_c_4, Address_c_3, Address_c_2, Address_c_1,
|
||||
Address_c_0, OutClockEn_c, Reset_c, Q_c_7, Q_c_6, Q_c_5,
|
||||
Q_c_4, Q_c_3, Q_c_2, Q_c_1, Q_c_0, scuba_vlo, VCC_net;
|
||||
|
||||
OB Q_pad_4 (.I(Q_c_4), .O(Q[4])); // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
|
||||
VLO scuba_vlo_inst (.Z(scuba_vlo));
|
||||
DP8KC codeROM_0_0_1_0 (.DIA0(scuba_vlo), .DIA1(scuba_vlo), .DIA2(scuba_vlo),
|
||||
.DIA3(scuba_vlo), .DIA4(scuba_vlo), .DIA5(scuba_vlo), .DIA6(scuba_vlo),
|
||||
.DIA7(scuba_vlo), .DIA8(scuba_vlo), .ADA0(scuba_vlo), .ADA1(scuba_vlo),
|
||||
.ADA2(Address_c_0), .ADA3(Address_c_1), .ADA4(Address_c_2),
|
||||
.ADA5(Address_c_3), .ADA6(Address_c_4), .ADA7(Address_c_5),
|
||||
.ADA8(Address_c_6), .ADA9(Address_c_7), .ADA10(Address_c_8),
|
||||
.ADA11(Address_c_9), .ADA12(Address_c_10), .CEA(OutClockEn_c),
|
||||
.OCEA(OutClockEn_c), .CLKA(OutClock_c), .WEA(scuba_vlo), .CSA0(scuba_vlo),
|
||||
.CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(Reset_c), .DIB0(scuba_vlo),
|
||||
.DIB1(scuba_vlo), .DIB2(scuba_vlo), .DIB3(scuba_vlo), .DIB4(scuba_vlo),
|
||||
.DIB5(scuba_vlo), .DIB6(scuba_vlo), .DIB7(scuba_vlo), .DIB8(scuba_vlo),
|
||||
.ADB0(scuba_vlo), .ADB1(scuba_vlo), .ADB2(scuba_vlo), .ADB3(scuba_vlo),
|
||||
.ADB4(scuba_vlo), .ADB5(scuba_vlo), .ADB6(scuba_vlo), .ADB7(scuba_vlo),
|
||||
.ADB8(scuba_vlo), .ADB9(scuba_vlo), .ADB10(scuba_vlo), .ADB11(scuba_vlo),
|
||||
.ADB12(scuba_vlo), .CEB(VCC_net), .OCEB(VCC_net), .CLKB(scuba_vlo),
|
||||
.WEB(scuba_vlo), .CSB0(scuba_vlo), .CSB1(scuba_vlo), .CSB2(scuba_vlo),
|
||||
.RSTB(scuba_vlo), .DOA0(Q_c_4), .DOA1(Q_c_5), .DOA2(Q_c_6),
|
||||
.DOA3(Q_c_7)) /* synthesis MEM_LPC_FILE="codeROM.lpc", MEM_INIT_FILE="rom-upper-2k.mem", syn_instantiated=1 */ ;
|
||||
defparam codeROM_0_0_1_0.DATA_WIDTH_A = 4;
|
||||
defparam codeROM_0_0_1_0.DATA_WIDTH_B = 4;
|
||||
defparam codeROM_0_0_1_0.REGMODE_A = "OUTREG";
|
||||
defparam codeROM_0_0_1_0.REGMODE_B = "NOREG";
|
||||
defparam codeROM_0_0_1_0.CSDECODE_A = "0b000";
|
||||
defparam codeROM_0_0_1_0.CSDECODE_B = "0b111";
|
||||
defparam codeROM_0_0_1_0.WRITEMODE_A = "NORMAL";
|
||||
defparam codeROM_0_0_1_0.WRITEMODE_B = "NORMAL";
|
||||
defparam codeROM_0_0_1_0.GSR = "ENABLED";
|
||||
defparam codeROM_0_0_1_0.RESETMODE = "SYNC";
|
||||
defparam codeROM_0_0_1_0.ASYNC_RESET_RELEASE = "SYNC";
|
||||
defparam codeROM_0_0_1_0.INIT_DATA = "STATIC";
|
||||
defparam codeROM_0_0_1_0.INITVAL_00 = "0x1A4CD0500515E181909F1388118ABC112FA014C81784407ED8006C8166AC116C8178A2014C0058E2";
|
||||
defparam codeROM_0_0_1_0.INITVAL_01 = "0x128A015CC1080D415C9419005178C813E9C1025A1F41F094CD05004158D21004A19A2C1A4CD04AAC";
|
||||
defparam codeROM_0_0_1_0.INITVAL_02 = "0x178891004A188200905B19098008A41080014C4C1485E01AC4040480B65A1909F0388B0B080094C8";
|
||||
defparam codeROM_0_0_1_0.INITVAL_03 = "0x00AAC0840510ABC112800B4C4040580B6C81300514C4C1A85E01AC4040580B6C8130051584200885";
|
||||
defparam codeROM_0_0_1_0.INITVAL_04 = "0x18220140D8014C813ED40588B19A2C158D214044158891E2C8174041587401E4C188200B05B19098";
|
||||
defparam codeROM_0_0_1_0.INITVAL_05 = "0x190BC116C004A8C0C25A0B02A0B05A0B05A0900A186461DCEC0A43C1FEFC0D88B190B11E6C8160B3";
|
||||
defparam codeROM_0_0_1_0.INITVAL_06 = "0x100F1190B014A800CAA510A6105E4A1C28410848080490E4F1190B015EDC198381E2C8162AC116F1";
|
||||
defparam codeROM_0_0_1_0.INITVAL_07 = "0x14CFD118F2014C0058F20B4C81788B18026090441909F0388B114050DC94198591080B080F1190B4";
|
||||
defparam codeROM_0_0_1_0.INITVAL_08 = "0x10000010881000000000010881108810CA00000514CC81788B190BC116C104CC81788B182261FACC";
|
||||
defparam codeROM_0_0_1_0.INITVAL_09 = "0x19C2815E9C1046C1C48A012C8040A014080100801008010080100081000810008100081000001088";
|
||||
defparam codeROM_0_0_1_0.INITVAL_0A = "0x14AA61A2071BCD01FA5A0124800EA4100FA180200F04A01E8414079120F90B40A1744800EA4100FA";
|
||||
defparam codeROM_0_0_1_0.INITVAL_0B = "0x0145E01E0E114580B41F094F700000000010000000000084061DA0F1AAAC064CF040A01386201E90";
|
||||
defparam codeROM_0_0_1_0.INITVAL_0C = "0x140A40B4C1092ED006C41086C1B64801C0901846038EB0325014025108A01488C1B64819AB510A61";
|
||||
defparam codeROM_0_0_1_0.INITVAL_0D = "0x028A50C6F110A600B6580148414A86090551FA850AA501E8A51CAE01E0E50AA5F1B0550AACE162F4";
|
||||
defparam codeROM_0_0_1_0.INITVAL_0E = "0x14CFD024C80B2C8132CB0988B190B60BC090B00602AA40C6F1108610060412AB30145800C5A0B056";
|
||||
defparam codeROM_0_0_1_0.INITVAL_0F = "0x0088400C0712CA00C20F12C1300EBA11AC5080960944C0164E068841C0940C2FD1882001448014A4";
|
||||
defparam codeROM_0_0_1_0.INITVAL_10 = "0x100FB198400207B090EA0080B018040042204402094CE040A01E0751E80D1580F16A8F03844162A7";
|
||||
defparam codeROM_0_0_1_0.INITVAL_11 = "0x014A7058EB0945D094FD100490B60A0B05B014C9080901C8A014A8510ABC14ABC0905B0145800EB5";
|
||||
defparam codeROM_0_0_1_0.INITVAL_12 = "0x01E4A01A0C1904C08480148901584901EBF1B0490145A118D4144A21B0CC080AC1C40A01A0E1BA5C";
|
||||
defparam codeROM_0_0_1_0.INITVAL_13 = "0x01A4A0900A0B07219CB4142100F65A0B04A0B04801448014E909C0F16AA2152D1152D1152D2140FC";
|
||||
defparam codeROM_0_0_1_0.INITVAL_14 = "0x0885E0326510A6014245170A5160A11A0E3038EB09458094580944B18E2C00458114480B04A0B448";
|
||||
defparam codeROM_0_0_1_0.INITVAL_15 = "0x094C4058B21D6CB04A85100A4140D4140100F65A07A0A012C604A8814884108A4140D0140A01A0EC";
|
||||
defparam codeROM_0_0_1_0.INITVAL_16 = "0x01E2C01E2C01E2C0540B0980A02207162FA01E95148A01A4A01A224140790940F128A10207B0B41D";
|
||||
defparam codeROM_0_0_1_0.INITVAL_17 = "0x01448088A4094441546C1C448000001008000C301EC1A00EB400EBA01EB21F21E1C8960140712AA8";
|
||||
defparam codeROM_0_0_1_0.INITVAL_18 = "0x10C480C0F90B45A1DE4A18C2C0685C012C0048801488014AEC004581145801458094480145801448";
|
||||
defparam codeROM_0_0_1_0.INITVAL_19 = "0x1B800142BC1C448000000B4F110049182B0140F900E9A14A8600E9901E9514C0713E401F2AA09064";
|
||||
defparam codeROM_0_0_1_0.INITVAL_1A = "0x0340D0580A01A0F16AA01448015E220501A1F6401A0FE0140D014F805E920004A000000B40F000A0";
|
||||
defparam codeROM_0_0_1_0.INITVAL_1B = "0x198CC158CC1B8CA1980C1B8CA198CC1B8CC158AD1980D19ADC158AC1C04F1BCFE040FC1B63A01A2C";
|
||||
defparam codeROM_0_0_1_0.INITVAL_1C = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF000000A00D198CA19AAC1B8CA1980C19ACC";
|
||||
defparam codeROM_0_0_1_0.INITVAL_1D = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
|
||||
defparam codeROM_0_0_1_0.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
|
||||
defparam codeROM_0_0_1_0.INITVAL_1F = "0x1FE1019ACA15CEC154FE1FEFE1D8AE1DEFC156BB174AC15EFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
|
||||
OB Q_pad_5 (.I(Q_c_5), .O(Q[5])); // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
|
||||
OB Q_pad_6 (.I(Q_c_6), .O(Q[6])); // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
|
||||
DP8KC codeROM_0_0_0_1 (.DIA0(scuba_vlo), .DIA1(scuba_vlo), .DIA2(scuba_vlo),
|
||||
.DIA3(scuba_vlo), .DIA4(scuba_vlo), .DIA5(scuba_vlo), .DIA6(scuba_vlo),
|
||||
.DIA7(scuba_vlo), .DIA8(scuba_vlo), .ADA0(scuba_vlo), .ADA1(scuba_vlo),
|
||||
.ADA2(Address_c_0), .ADA3(Address_c_1), .ADA4(Address_c_2),
|
||||
.ADA5(Address_c_3), .ADA6(Address_c_4), .ADA7(Address_c_5),
|
||||
.ADA8(Address_c_6), .ADA9(Address_c_7), .ADA10(Address_c_8),
|
||||
.ADA11(Address_c_9), .ADA12(Address_c_10), .CEA(OutClockEn_c),
|
||||
.OCEA(OutClockEn_c), .CLKA(OutClock_c), .WEA(scuba_vlo), .CSA0(scuba_vlo),
|
||||
.CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(Reset_c), .DIB0(scuba_vlo),
|
||||
.DIB1(scuba_vlo), .DIB2(scuba_vlo), .DIB3(scuba_vlo), .DIB4(scuba_vlo),
|
||||
.DIB5(scuba_vlo), .DIB6(scuba_vlo), .DIB7(scuba_vlo), .DIB8(scuba_vlo),
|
||||
.ADB0(scuba_vlo), .ADB1(scuba_vlo), .ADB2(scuba_vlo), .ADB3(scuba_vlo),
|
||||
.ADB4(scuba_vlo), .ADB5(scuba_vlo), .ADB6(scuba_vlo), .ADB7(scuba_vlo),
|
||||
.ADB8(scuba_vlo), .ADB9(scuba_vlo), .ADB10(scuba_vlo), .ADB11(scuba_vlo),
|
||||
.ADB12(scuba_vlo), .CEB(VCC_net), .OCEB(VCC_net), .CLKB(scuba_vlo),
|
||||
.WEB(scuba_vlo), .CSB0(scuba_vlo), .CSB1(scuba_vlo), .CSB2(scuba_vlo),
|
||||
.RSTB(scuba_vlo), .DOA0(Q_c_0), .DOA1(Q_c_1), .DOA2(Q_c_2),
|
||||
.DOA3(Q_c_3)) /* synthesis MEM_LPC_FILE="codeROM.lpc", MEM_INIT_FILE="rom-upper-2k.mem", syn_instantiated=1 */ ;
|
||||
defparam codeROM_0_0_0_1.DATA_WIDTH_A = 4;
|
||||
defparam codeROM_0_0_0_1.DATA_WIDTH_B = 4;
|
||||
defparam codeROM_0_0_0_1.REGMODE_A = "OUTREG";
|
||||
defparam codeROM_0_0_0_1.REGMODE_B = "NOREG";
|
||||
defparam codeROM_0_0_0_1.CSDECODE_A = "0b000";
|
||||
defparam codeROM_0_0_0_1.CSDECODE_B = "0b111";
|
||||
defparam codeROM_0_0_0_1.WRITEMODE_A = "NORMAL";
|
||||
defparam codeROM_0_0_0_1.WRITEMODE_B = "NORMAL";
|
||||
defparam codeROM_0_0_0_1.GSR = "ENABLED";
|
||||
defparam codeROM_0_0_0_1.RESETMODE = "SYNC";
|
||||
defparam codeROM_0_0_0_1.ASYNC_RESET_RELEASE = "SYNC";
|
||||
defparam codeROM_0_0_0_1.INIT_DATA = "STATIC";
|
||||
defparam codeROM_0_0_0_1.INITVAL_00 = "0x0C0980009A0A40801ADB000CE120901FAF90A0011B29C110080E00E1A40013A0B1B6900E0A5014E0";
|
||||
defparam codeROM_0_0_0_1.INITVAL_01 = "0x1A250014931860B0BE0C080940300D1B60019C951E05018A980009B0B280012C512C090C09801659";
|
||||
defparam codeROM_0_0_0_1.INITVAL_02 = "0x020DD012F51026A1CA6101AD013C510A25213088078760A0810D4D50C29401ADB000CC128091AA0D";
|
||||
defparam codeROM_0_0_0_1.INITVAL_03 = "0x1265802CA20AC101BA0904A810D4150C20D1A0910B0881F8760A0810D4050C20D1A0900B01615E56";
|
||||
defparam codeROM_0_0_0_1.INITVAL_04 = "0x15E01130081400D1B200120CD1300813280152A00A0DD1600C194900B0DC060B61026A06A6101AD0";
|
||||
defparam codeROM_0_0_0_1.INITVAL_05 = "0x01CD01BAA5006501308504A190EA550CA4500A0913AC0154A9160FF078F3000CD000D80000E1AC08";
|
||||
defparam codeROM_0_0_0_1.INITVAL_06 = "0x0B4B0018D000E5012A560A8580E0C51A0800A050120B91F2B0018D60080313C081600C1BC0003AB0";
|
||||
defparam codeROM_0_0_0_1.INITVAL_07 = "0x040A0112F0140AF01280000051A01D15E0000A0501ADB000CC0120219C0C090410122002CB0018D1";
|
||||
defparam codeROM_0_0_0_1.INITVAL_08 = "0x000000000000000000000000000000000AA154A80A0061A04D004D001AAF000071A03D15E001A0A8";
|
||||
defparam codeROM_0_0_0_1.INITVAL_09 = "0x1BA001340A1400D1A0090A0AA0000512000000000000000000000000000000000000000000000000";
|
||||
defparam codeROM_0_0_0_1.INITVAL_0A = "0x13040160581C00411C86180E50F0DD0AC8D1000711AE50D0DD0AA8D1088D10CB0112E50F0DD0AC8D";
|
||||
defparam codeROM_0_0_0_1.INITVAL_0B = "0x0127608010012750AA301CCFF0041404202128210024012800180481D0691A0980020F0120009095";
|
||||
defparam codeROM_0_0_0_1.INITVAL_0C = "0x0C0980AABF190200C0AB0B65A1FAC50F2200F2C51145D0A09610E990BA550585A19AB5152D60A858";
|
||||
defparam codeROM_0_0_0_1.INITVAL_0D = "0x118590D0801126A082950128C08A5800A41160840281901A450CA62002060281901061082AB18C0E";
|
||||
defparam codeROM_0_0_0_1.INITVAL_0E = "0x0A0401F20E1B00F1B0B6180DD010D00EC200CA7910C510D020102680200D12C180C075012550CA45";
|
||||
defparam codeROM_0_0_0_1.INITVAL_0F = "0x110A801268130A3130581301009098150E918600168B6040C51184B0C40C0B0A01566A064B60048B";
|
||||
defparam codeROM_0_0_0_1.INITVAL_10 = "0x0AA8919EC30088906C8A0522008029072A81548A06ADD0009500E891F2700B2681304A014800B628";
|
||||
defparam codeROM_0_0_0_1.INITVAL_11 = "0x0928F13A3D04C9006A80100290828014A41000DF1860A00461128650A8181481804A41020550D094";
|
||||
defparam codeROM_0_0_0_1.INITVAL_12 = "0x160661604919ACE1E08812810130410F0DB010410E086148060C293014D11809D1A00914050160A4";
|
||||
defparam codeROM_0_0_0_1.INITVAL_13 = "0x0402510A0914AF91A6D20C60411A8608A290AAE5012D5132B0068781D0481200F12801130011300A";
|
||||
defparam codeROM_0_0_0_1.INITVAL_14 = "0x1F856060840A85213084030A4022080080B01A3D04C550AA4508A6014C0A1E0B50123514C3614A65";
|
||||
defparam codeROM_0_0_0_1.INITVAL_15 = "0x04AEF016F0080AD00A640A025130020B804112841E069080A70165213A5E0CC570C802040960040D";
|
||||
defparam codeROM_0_0_0_1.INITVAL_16 = "0x020F90A089120B90E4E0012020A0481D40A0909809A5201E94000950AC8D0EA581AC540088D10CB0";
|
||||
defparam codeROM_0_0_0_1.INITVAL_17 = "0x0B26610C5806A820B4890A083062110623306081010880D0980B09A0B098100C010058004581304A";
|
||||
defparam codeROM_0_0_0_1.INITVAL_18 = "0x0B06510E89108A50A0D51200E098A60A08001C5013A591346A1E0B5012550124505235052A501225";
|
||||
defparam codeROM_0_0_0_1.INITVAL_19 = "0x014801CA0B0C035154AA10A70100291EC9500C8D090DA130600D0D80B0D80C07813E961125904A83";
|
||||
defparam codeROM_0_0_0_1.INITVAL_1A = "0x1C420112A2040481304004850138200AC72154C300E8C02CA000CE901C30102CA154AA10AA0102EF";
|
||||
defparam codeROM_0_0_0_1.INITVAL_1B = "0x1DCF300A390CA401FC0B072400B82109EF2002041FC021E42501EF9000C5010DD00C0E09A22040F9";
|
||||
defparam codeROM_0_0_0_1.INITVAL_1C = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF00080002041FE201E80B072401FC040A835";
|
||||
defparam codeROM_0_0_0_1.INITVAL_1D = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
|
||||
defparam codeROM_0_0_0_1.INITVAL_1E = "0x1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
|
||||
defparam codeROM_0_0_0_1.INITVAL_1F = "0x1FE00026D01C6E90182508A0D1E6051800100A890209311EFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF";
|
||||
OB Q_pad_7 (.I(Q_c_7), .O(Q[7])); // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
|
||||
OB Q_pad_3 (.I(Q_c_3), .O(Q[3])); // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
|
||||
OB Q_pad_2 (.I(Q_c_2), .O(Q[2])); // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
|
||||
OB Q_pad_1 (.I(Q_c_1), .O(Q[1])); // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
|
||||
OB Q_pad_0 (.I(Q_c_0), .O(Q[0])); // c:/users/chamberlin/documents/liron/lattice/coderom.v(13[23:24])
|
||||
IB Address_pad_10 (.I(Address[10]), .O(Address_c_10)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
|
||||
IB Address_pad_9 (.I(Address[9]), .O(Address_c_9)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
|
||||
IB Address_pad_8 (.I(Address[8]), .O(Address_c_8)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
|
||||
IB Address_pad_7 (.I(Address[7]), .O(Address_c_7)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
|
||||
IB Address_pad_6 (.I(Address[6]), .O(Address_c_6)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
|
||||
IB Address_pad_5 (.I(Address[5]), .O(Address_c_5)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
|
||||
IB Address_pad_4 (.I(Address[4]), .O(Address_c_4)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
|
||||
IB Address_pad_3 (.I(Address[3]), .O(Address_c_3)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
|
||||
IB Address_pad_2 (.I(Address[2]), .O(Address_c_2)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
|
||||
IB Address_pad_1 (.I(Address[1]), .O(Address_c_1)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
|
||||
IB Address_pad_0 (.I(Address[0]), .O(Address_c_0)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(9[23:30])
|
||||
IB OutClock_pad (.I(OutClock), .O(OutClock_c)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(10[16:24])
|
||||
IB OutClockEn_pad (.I(OutClockEn), .O(OutClockEn_c)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(11[16:26])
|
||||
IB Reset_pad (.I(Reset), .O(Reset_c)); // c:/users/chamberlin/documents/liron/lattice/coderom.v(12[16:21])
|
||||
GSR GSR_INST (.GSR(VCC_net));
|
||||
TSALL TSALL_INST (.TSALL(scuba_vlo));
|
||||
PUR PUR_INST (.PUR(VCC_net));
|
||||
defparam PUR_INST.RST_PULSE = 1;
|
||||
VHI i7 (.Z(VCC_net));
|
||||
|
||||
endmodule
|
||||
//
|
||||
// Verilog Description of module TSALL
|
||||
// module not written out since it is a black-box.
|
||||
//
|
||||
|
||||
//
|
||||
// Verilog Description of module PUR
|
||||
// module not written out since it is a black-box.
|
||||
//
|
||||
|
||||
51
lattice/fpgatop/fpgatop.xcf
Normal file
51
lattice/fpgatop/fpgatop.xcf
Normal file
@ -0,0 +1,51 @@
|
||||
<?xml version='1.0' encoding='utf-8' ?>
|
||||
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
|
||||
<ispXCF version="3.9.0">
|
||||
<Comment></Comment>
|
||||
<Chain>
|
||||
<Comm>JTAG</Comm>
|
||||
<Device>
|
||||
<SelectedProg value="TRUE"/>
|
||||
<Pos>1</Pos>
|
||||
<Vendor>Lattice</Vendor>
|
||||
<Family>MachXO2</Family>
|
||||
<Name>LCMXO2-1200HC</Name>
|
||||
<IDCode>0x012ba043</IDCode>
|
||||
<Package>All</Package>
|
||||
<PON>LCMXO2-1200HC</PON>
|
||||
<Bypass>
|
||||
<InstrLen>8</InstrLen>
|
||||
<InstrVal>11111111</InstrVal>
|
||||
<BScanLen>1</BScanLen>
|
||||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File>C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/liron_fpgatop.jed</File>
|
||||
<FileTime>02/22/18 10:56:48</FileTime>
|
||||
<JedecChecksum>0x3262</JedecChecksum>
|
||||
<Operation>FLASH Erase,Program,Verify</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
<IOState>HighZ</IOState>
|
||||
<PreloadLength>208</PreloadLength>
|
||||
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
|
||||
<SVFProcessor>SVF Processor</SVFProcessor>
|
||||
<Usercode>0x00000000</Usercode>
|
||||
<AccessMode>FLASH</AccessMode>
|
||||
</Option>
|
||||
</Device>
|
||||
</Chain>
|
||||
<ProjectOptions>
|
||||
<Program>SEQUENTIAL</Program>
|
||||
<Process>ENTIRED CHAIN</Process>
|
||||
<OperationOverride>No Override</OperationOverride>
|
||||
<StartTAP>TLR</StartTAP>
|
||||
<EndTAP>TLR</EndTAP>
|
||||
<VerifyUsercode value="FALSE"/>
|
||||
<TCKDelay>1</TCKDelay>
|
||||
</ProjectOptions>
|
||||
<CableOptions>
|
||||
<CableName>USB</CableName>
|
||||
<PortAdd>EzUSB-0</PortAdd>
|
||||
<USBID>\\?\usb#vid_1134&amp;pid_8001#5&amp;5cf71e0&amp;0&amp;4#</USBID>
|
||||
</CableOptions>
|
||||
</ispXCF>
|
||||
21
lattice/fpgatop/hdla_gen_hierarchy.html
Normal file
21
lattice/fpgatop/hdla_gen_hierarchy.html
Normal file
File diff suppressed because one or more lines are too long
60
lattice/fpgatop/liron_fpgatop.alt
Normal file
60
lattice/fpgatop/liron_fpgatop.alt
Normal file
@ -0,0 +1,60 @@
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Thu Feb 22 10:56:48 2018 *
|
||||
NOTE DESIGN NAME: top *
|
||||
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS data[7] : 52 : inout *
|
||||
NOTE PINS data[6] : 51 : inout *
|
||||
NOTE PINS data[5] : 47 : inout *
|
||||
NOTE PINS data[4] : 39 : inout *
|
||||
NOTE PINS data[3] : 38 : inout *
|
||||
NOTE PINS data[2] : 37 : inout *
|
||||
NOTE PINS data[1] : 36 : inout *
|
||||
NOTE PINS data[0] : 35 : inout *
|
||||
NOTE PINS wrdata : 83 : out *
|
||||
NOTE PINS phase[3] : 87 : out *
|
||||
NOTE PINS phase[2] : 86 : out *
|
||||
NOTE PINS phase[1] : 85 : out *
|
||||
NOTE PINS phase[0] : 84 : out *
|
||||
NOTE PINS _wrreq : 88 : out *
|
||||
NOTE PINS _enbl1 : 82 : out *
|
||||
NOTE PINS _enbl2 : 99 : out *
|
||||
NOTE PINS select : 78 : out *
|
||||
NOTE PINS _en35 : 98 : out *
|
||||
NOTE PINS spi_clk : 31 : out *
|
||||
NOTE PINS spi_mosi : 49 : out *
|
||||
NOTE PINS spi_cs : 27 : out *
|
||||
NOTE PINS _en245 : 30 : out *
|
||||
NOTE PINS debugInfo[7] : 25 : out *
|
||||
NOTE PINS debugInfo[6] : 24 : out *
|
||||
NOTE PINS debugInfo[5] : 17 : out *
|
||||
NOTE PINS debugInfo[4] : 16 : out *
|
||||
NOTE PINS debugInfo[3] : 15 : out *
|
||||
NOTE PINS debugInfo[2] : 14 : out *
|
||||
NOTE PINS debugInfo[1] : 13 : out *
|
||||
NOTE PINS debugInfo[0] : 12 : out *
|
||||
NOTE PINS addr[11] : 69 : in *
|
||||
NOTE PINS addr[10] : 68 : in *
|
||||
NOTE PINS addr[9] : 67 : in *
|
||||
NOTE PINS addr[8] : 66 : in *
|
||||
NOTE PINS addr[7] : 65 : in *
|
||||
NOTE PINS addr[6] : 64 : in *
|
||||
NOTE PINS addr[5] : 62 : in *
|
||||
NOTE PINS addr[4] : 60 : in *
|
||||
NOTE PINS addr[3] : 59 : in *
|
||||
NOTE PINS addr[2] : 58 : in *
|
||||
NOTE PINS addr[1] : 57 : in *
|
||||
NOTE PINS addr[0] : 54 : in *
|
||||
NOTE PINS fclk : 63 : in *
|
||||
NOTE PINS q3 : 70 : in *
|
||||
NOTE PINS rw : 71 : in *
|
||||
NOTE PINS _iostrobe : 74 : in *
|
||||
NOTE PINS _iosel : 53 : in *
|
||||
NOTE PINS _devsel : 34 : in *
|
||||
NOTE PINS _reset : 75 : in *
|
||||
NOTE PINS sense : 97 : in *
|
||||
NOTE PINS rddata : 96 : in *
|
||||
NOTE PINS spi_miso : 32 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
NOTE COMPRESSION: on *
|
||||
53
lattice/fpgatop/liron_fpgatop.arearep
Normal file
53
lattice/fpgatop/liron_fpgatop.arearep
Normal file
@ -0,0 +1,53 @@
|
||||
----------------------------------------------------------------------
|
||||
Report for cell top.TECH
|
||||
Register bits: 43 of 1520 (2.829%)
|
||||
I/O cells: 52
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
DP8KC 4 100.0
|
||||
FD1P3AX 29 100.0
|
||||
FD1P3IX 10 100.0
|
||||
FD1P3JX 1 100.0
|
||||
FD1S3AX 2 100.0
|
||||
FD1S3AY 1 100.0
|
||||
GSR 1 100.0
|
||||
IB 22 100.0
|
||||
INV 1 100.0
|
||||
LUT4 115 100.0
|
||||
OB 19 100.0
|
||||
OBZ 3 100.0
|
||||
PFUMX 1 100.0
|
||||
SUB MODULES
|
||||
addrDecoder 1
|
||||
codeROM 1
|
||||
iwm 1
|
||||
TOTAL 220
|
||||
----------------------------------------------------------------------
|
||||
Report for cell iwm.v1
|
||||
Instance Path : myIwm
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
FD1P3AX 29 100.0
|
||||
FD1P3IX 9 90.0
|
||||
FD1P3JX 1 100.0
|
||||
FD1S3AX 2 100.0
|
||||
FD1S3AY 1 100.0
|
||||
LUT4 103 89.6
|
||||
PFUMX 1 100.0
|
||||
TOTAL 146
|
||||
----------------------------------------------------------------------
|
||||
Report for cell codeROM.v1
|
||||
Instance Path : myROM
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
DP8KC 4 100.0
|
||||
TOTAL 4
|
||||
----------------------------------------------------------------------
|
||||
Report for cell addrDecoder.v1
|
||||
Instance Path : myAddrDecoder
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
FD1P3IX 1 10.0
|
||||
LUT4 4 3.5
|
||||
TOTAL 5
|
||||
82
lattice/fpgatop/liron_fpgatop.bgn
Normal file
82
lattice/fpgatop/liron_fpgatop.bgn
Normal file
@ -0,0 +1,82 @@
|
||||
BITGEN: Bitstream Generator Diamond (64-bit) 3.9.0.99.2
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path C:/Users/chamberlin/Documents/Liron/lattice -w -jedec -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml liron_fpgatop.ncd liron_fpgatop.prf
|
||||
|
||||
Loading design for application Bitgen from file liron_fpgatop.ncd.
|
||||
Design name: top
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
|
||||
Package Status: Final Version 1.42.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from liron_fpgatop.prf.
|
||||
|
||||
Preference Summary:
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.94.
|
||||
|
||||
Saving bit stream in "liron_fpgatop.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 511 Pages (128*511 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 0 Page.
|
||||
|
||||
BIN
lattice/fpgatop/liron_fpgatop.dir/5_1.ncd
Normal file
BIN
lattice/fpgatop/liron_fpgatop.dir/5_1.ncd
Normal file
Binary file not shown.
279
lattice/fpgatop/liron_fpgatop.dir/5_1.pad
Normal file
279
lattice/fpgatop/liron_fpgatop.dir/5_1.pad
Normal file
@ -0,0 +1,279 @@
|
||||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-1200HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.42
|
||||
|
||||
Thu Feb 22 10:56:42 2018
|
||||
|
||||
Pinout by Port Name:
|
||||
+--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| _devsel | 34/2 | LVCMOS33_IN | PB9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| _en245 | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| _en35 | 98/0 | LVCMOS33_OUT | PT9B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| _enbl1 | 82/0 | LVCMOS33_OUT | PT15C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| _enbl2 | 99/0 | LVCMOS33_OUT | PT9A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| _iosel | 53/1 | LVCMOS33_IN | PR9D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| _iostrobe | 74/1 | LVCMOS33_IN | PR2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| _reset | 75/1 | LVCMOS33_IN | PR2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| _wrreq | 88/0 | LVCMOS33_OUT | PT12A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| addr[0] | 54/1 | LVCMOS33_IN | PR9C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[10] | 68/1 | LVCMOS33_IN | PR4B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[11] | 69/1 | LVCMOS33_IN | PR4A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[1] | 57/1 | LVCMOS33_IN | PR9B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[2] | 58/1 | LVCMOS33_IN | PR9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[3] | 59/1 | LVCMOS33_IN | PR8D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[4] | 60/1 | LVCMOS33_IN | PR8C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[5] | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[6] | 64/1 | LVCMOS33_IN | PR5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[7] | 65/1 | LVCMOS33_IN | PR5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[8] | 66/1 | LVCMOS33_IN | PR4D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[9] | 67/1 | LVCMOS33_IN | PR4C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| data[0] | 35/2 | LVCMOS33_BIDI | PB9B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[1] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[2] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[3] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[4] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[5] | 47/2 | LVCMOS33_BIDI | PB18D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[6] | 51/1 | LVCMOS33_BIDI | PR10D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[7] | 52/1 | LVCMOS33_BIDI | PR10C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| debugInfo[0] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[1] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[2] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[3] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[4] | 16/3 | LVCMOS33_OUT | PL8A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[5] | 17/3 | LVCMOS33_OUT | PL8B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[6] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[7] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| fclk | 63/1 | LVCMOS33_IN | PR5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| phase[0] | 84/0 | LVCMOS33_OUT | PT15A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| phase[1] | 85/0 | LVCMOS33_OUT | PT12D | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| phase[2] | 86/0 | LVCMOS33_OUT | PT12C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| phase[3] | 87/0 | LVCMOS33_OUT | PT12B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| q3 | 70/1 | LVCMOS33_IN | PR3B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| rddata | 96/0 | LVCMOS33_IN | PT10B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| rw | 71/1 | LVCMOS33_IN | PR3A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| select | 78/0 | LVCMOS33_OUT | PT16C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| sense | 97/0 | LVCMOS33_IN | PT10A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| spi_clk | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| spi_cs | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| spi_miso | 32/2 | LVCMOS33_IN | PB6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| spi_mosi | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| wrdata | 83/0 | LVCMOS33_OUT | PT15B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
+--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | unused, PULL:DOWN | | | PL2C | L_GPLLT_IN | | |
|
||||
| 2/3 | unused, PULL:DOWN | | | PL2D | L_GPLLC_IN | | |
|
||||
| 3/3 | unused, PULL:DOWN | | | PL3A | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3C | | | |
|
||||
| 8/3 | unused, PULL:DOWN | | | PL3D | | | |
|
||||
| 9/3 | unused, PULL:DOWN | | | PL4A | | | |
|
||||
| 10/3 | unused, PULL:DOWN | | | PL4B | | | |
|
||||
| 12/3 | debugInfo[0] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | debugInfo[1] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | debugInfo[2] | LOCATED | LVCMOS33_OUT | PL5C | | | |
|
||||
| 15/3 | debugInfo[3] | LOCATED | LVCMOS33_OUT | PL5D | | | |
|
||||
| 16/3 | debugInfo[4] | LOCATED | LVCMOS33_OUT | PL8A | | | |
|
||||
| 17/3 | debugInfo[5] | LOCATED | LVCMOS33_OUT | PL8B | | | |
|
||||
| 18/3 | unused, PULL:DOWN | | | PL8C | | | |
|
||||
| 19/3 | unused, PULL:DOWN | | | PL8D | | | |
|
||||
| 20/3 | unused, PULL:DOWN | | | PL9A | PCLKT3_0 | | |
|
||||
| 21/3 | unused, PULL:DOWN | | | PL9B | PCLKC3_0 | | |
|
||||
| 24/3 | debugInfo[6] | LOCATED | LVCMOS33_OUT | PL10C | | | |
|
||||
| 25/3 | debugInfo[7] | LOCATED | LVCMOS33_OUT | PL10D | | | |
|
||||
| 27/2 | spi_cs | LOCATED | LVCMOS33_OUT | PB4C | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB6A | | | |
|
||||
| 30/2 | _en245 | LOCATED | LVCMOS33_OUT | PB6B | | | |
|
||||
| 31/2 | spi_clk | LOCATED | LVCMOS33_OUT | PB6C | MCLK/CCLK | | |
|
||||
| 32/2 | spi_miso | LOCATED | LVCMOS33_IN | PB6D | SO/SPISO | | |
|
||||
| 34/2 | _devsel | LOCATED | LVCMOS33_IN | PB9A | PCLKT2_0 | | |
|
||||
| 35/2 | data[0] | LOCATED | LVCMOS33_BIDI | PB9B | PCLKC2_0 | | |
|
||||
| 36/2 | data[1] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
|
||||
| 37/2 | data[2] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
|
||||
| 38/2 | data[3] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
|
||||
| 39/2 | data[4] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
|
||||
| 40/2 | unused, PULL:DOWN | | | PB15A | | | |
|
||||
| 41/2 | unused, PULL:DOWN | | | PB15B | | | |
|
||||
| 42/2 | unused, PULL:DOWN | | | PB18A | | | |
|
||||
| 43/2 | unused, PULL:DOWN | | | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | data[5] | LOCATED | LVCMOS33_BIDI | PB18D | | | |
|
||||
| 48/2 | Prohibited/Reserved | PROHIBITED | | PB20C | SN | | |
|
||||
| 49/2 | spi_mosi | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | data[6] | LOCATED | LVCMOS33_BIDI | PR10D | DQ1 | | |
|
||||
| 52/1 | data[7] | LOCATED | LVCMOS33_BIDI | PR10C | DQ1 | | |
|
||||
| 53/1 | _iosel | LOCATED | LVCMOS33_IN | PR9D | DQ1 | | |
|
||||
| 54/1 | addr[0] | LOCATED | LVCMOS33_IN | PR9C | DQ1 | | |
|
||||
| 57/1 | addr[1] | LOCATED | LVCMOS33_IN | PR9B | DQ1 | | |
|
||||
| 58/1 | addr[2] | LOCATED | LVCMOS33_IN | PR9A | DQ1 | | |
|
||||
| 59/1 | addr[3] | LOCATED | LVCMOS33_IN | PR8D | DQ1 | | |
|
||||
| 60/1 | addr[4] | LOCATED | LVCMOS33_IN | PR8C | DQ1 | | |
|
||||
| 61/1 | Prohibited/Reserved | PROHIBITED | | PR8A | DQS1 | | |
|
||||
| 62/1 | addr[5] | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | fclk | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | addr[6] | LOCATED | LVCMOS33_IN | PR5B | DQS0N | | |
|
||||
| 65/1 | addr[7] | LOCATED | LVCMOS33_IN | PR5A | DQS0 | | |
|
||||
| 66/1 | addr[8] | LOCATED | LVCMOS33_IN | PR4D | DQ0 | | |
|
||||
| 67/1 | addr[9] | LOCATED | LVCMOS33_IN | PR4C | DQ0 | | |
|
||||
| 68/1 | addr[10] | LOCATED | LVCMOS33_IN | PR4B | DQ0 | | |
|
||||
| 69/1 | addr[11] | LOCATED | LVCMOS33_IN | PR4A | DQ0 | | |
|
||||
| 70/1 | q3 | LOCATED | LVCMOS33_IN | PR3B | DQ0 | | |
|
||||
| 71/1 | rw | LOCATED | LVCMOS33_IN | PR3A | DQ0 | | |
|
||||
| 74/1 | _iostrobe | LOCATED | LVCMOS33_IN | PR2B | DQ0 | | |
|
||||
| 75/1 | _reset | LOCATED | LVCMOS33_IN | PR2A | DQ0 | | |
|
||||
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | select | LOCATED | LVCMOS33_OUT | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | _enbl1 | LOCATED | LVCMOS33_OUT | PT15C | JTAGENB | | |
|
||||
| 83/0 | wrdata | LOCATED | LVCMOS33_OUT | PT15B | | | |
|
||||
| 84/0 | phase[0] | LOCATED | LVCMOS33_OUT | PT15A | | | |
|
||||
| 85/0 | phase[1] | LOCATED | LVCMOS33_OUT | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | phase[2] | LOCATED | LVCMOS33_OUT | PT12C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | phase[3] | LOCATED | LVCMOS33_OUT | PT12B | PCLKC0_1 | | |
|
||||
| 88/0 | _wrreq | LOCATED | LVCMOS33_OUT | PT12A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
|
||||
| 96/0 | rddata | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 97/0 | sense | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 98/0 | _en35 | LOCATED | LVCMOS33_OUT | PT9B | | | |
|
||||
| 99/0 | _enbl2 | LOCATED | LVCMOS33_OUT | PT9A | | | |
|
||||
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
|
||||
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
|
||||
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
|
||||
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
|
||||
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
|
||||
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
|
||||
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
|
||||
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
|
||||
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
|
||||
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
|
||||
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
|
||||
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
|
||||
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
|
||||
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
|
||||
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
|
||||
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
|
||||
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
|
||||
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
|
||||
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
|
||||
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
|
||||
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
|
||||
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
|
||||
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
|
||||
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
|
||||
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "_devsel" SITE "34";
|
||||
LOCATE COMP "_en245" SITE "30";
|
||||
LOCATE COMP "_en35" SITE "98";
|
||||
LOCATE COMP "_enbl1" SITE "82";
|
||||
LOCATE COMP "_enbl2" SITE "99";
|
||||
LOCATE COMP "_iosel" SITE "53";
|
||||
LOCATE COMP "_iostrobe" SITE "74";
|
||||
LOCATE COMP "_reset" SITE "75";
|
||||
LOCATE COMP "_wrreq" SITE "88";
|
||||
LOCATE COMP "addr[0]" SITE "54";
|
||||
LOCATE COMP "addr[10]" SITE "68";
|
||||
LOCATE COMP "addr[11]" SITE "69";
|
||||
LOCATE COMP "addr[1]" SITE "57";
|
||||
LOCATE COMP "addr[2]" SITE "58";
|
||||
LOCATE COMP "addr[3]" SITE "59";
|
||||
LOCATE COMP "addr[4]" SITE "60";
|
||||
LOCATE COMP "addr[5]" SITE "62";
|
||||
LOCATE COMP "addr[6]" SITE "64";
|
||||
LOCATE COMP "addr[7]" SITE "65";
|
||||
LOCATE COMP "addr[8]" SITE "66";
|
||||
LOCATE COMP "addr[9]" SITE "67";
|
||||
LOCATE COMP "data[0]" SITE "35";
|
||||
LOCATE COMP "data[1]" SITE "36";
|
||||
LOCATE COMP "data[2]" SITE "37";
|
||||
LOCATE COMP "data[3]" SITE "38";
|
||||
LOCATE COMP "data[4]" SITE "39";
|
||||
LOCATE COMP "data[5]" SITE "47";
|
||||
LOCATE COMP "data[6]" SITE "51";
|
||||
LOCATE COMP "data[7]" SITE "52";
|
||||
LOCATE COMP "debugInfo[0]" SITE "12";
|
||||
LOCATE COMP "debugInfo[1]" SITE "13";
|
||||
LOCATE COMP "debugInfo[2]" SITE "14";
|
||||
LOCATE COMP "debugInfo[3]" SITE "15";
|
||||
LOCATE COMP "debugInfo[4]" SITE "16";
|
||||
LOCATE COMP "debugInfo[5]" SITE "17";
|
||||
LOCATE COMP "debugInfo[6]" SITE "24";
|
||||
LOCATE COMP "debugInfo[7]" SITE "25";
|
||||
LOCATE COMP "fclk" SITE "63";
|
||||
LOCATE COMP "phase[0]" SITE "84";
|
||||
LOCATE COMP "phase[1]" SITE "85";
|
||||
LOCATE COMP "phase[2]" SITE "86";
|
||||
LOCATE COMP "phase[3]" SITE "87";
|
||||
LOCATE COMP "q3" SITE "70";
|
||||
LOCATE COMP "rddata" SITE "96";
|
||||
LOCATE COMP "rw" SITE "71";
|
||||
LOCATE COMP "select" SITE "78";
|
||||
LOCATE COMP "sense" SITE "97";
|
||||
LOCATE COMP "spi_clk" SITE "31";
|
||||
LOCATE COMP "spi_cs" SITE "27";
|
||||
LOCATE COMP "spi_miso" SITE "32";
|
||||
LOCATE COMP "spi_mosi" SITE "49";
|
||||
LOCATE COMP "wrdata" SITE "83";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Feb 22 10:56:42 2018
|
||||
|
||||
200
lattice/fpgatop/liron_fpgatop.dir/5_1.par
Normal file
200
lattice/fpgatop/liron_fpgatop.dir/5_1.par
Normal file
@ -0,0 +1,200 @@
|
||||
|
||||
Lattice Place and Route Report for Design "liron_fpgatop_map.ncd"
|
||||
Thu Feb 22 10:56:39 2018
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF liron_fpgatop_map.ncd liron_fpgatop.dir/5_1.ncd liron_fpgatop.prf
|
||||
Preference file: liron_fpgatop.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file liron_fpgatop_map.ncd.
|
||||
Design name: top
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
|
||||
Package Status: Final Version 1.42.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 52+4(JTAG)/108 52% used
|
||||
52+4(JTAG)/80 70% bonded
|
||||
|
||||
SLICE 58/640 9% used
|
||||
|
||||
GSR 1/1 100% used
|
||||
EBR 4/7 57% used
|
||||
|
||||
|
||||
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
|
||||
Number of Signals: 193
|
||||
Number of Connections: 582
|
||||
|
||||
Pin Constraint Summary:
|
||||
52 out of 52 pins locked (100% locked).
|
||||
|
||||
The following 1 signal is selected to use the primary clock routing resources:
|
||||
fclk_c (driver: fclk, clk load #: 27)
|
||||
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
_devsel_c (driver: _devsel, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
|
||||
Signal n440_c is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
.........
|
||||
Finished Placer Phase 0. REAL time: 2 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 43211.
|
||||
Finished Placer Phase 1. REAL time: 3 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 43211
|
||||
Finished Placer Phase 2. REAL time: 3 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 2 out of 8 (25%)
|
||||
PLL : 0 out of 1 (0%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Quadrants All (TL, TR, BL, BR) - Global Clocks:
|
||||
PRIMARY "fclk_c" from comp "fclk" on CLK_PIN site "63 (PR5C)", clk load = 27
|
||||
SECONDARY "_devsel_c" from comp "_devsel" on CLK_PIN site "34 (PB9A)", clk load = 8, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 1 out of 8 (12%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
Edge Clocks:
|
||||
No edge clock selected.
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
52 + 4(JTAG) out of 108 (51.9%) PIO sites used.
|
||||
52 + 4(JTAG) out of 80 (70.0%) bonded PIO sites used.
|
||||
Number of PIO comps: 52; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 12 / 19 ( 63%) | 3.3V | - |
|
||||
| 1 | 20 / 21 ( 95%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 3 | 8 / 20 ( 40%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 2 secs
|
||||
|
||||
Dumping design to file liron_fpgatop.dir/5_1.ncd.
|
||||
|
||||
|
||||
-----------------------------------------------------------------
|
||||
INFO - par: ASE feature is off due to non timing-driven settings.
|
||||
-----------------------------------------------------------------
|
||||
|
||||
0 connections routed; 582 unrouted.
|
||||
Starting router resource preassignment
|
||||
|
||||
Completed router resource preassignment. Real time: 4 secs
|
||||
|
||||
Start NBR router at 10:56:43 02/22/18
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 10:56:43 02/22/18
|
||||
|
||||
Start NBR section for initial routing at 10:56:43 02/22/18
|
||||
Level 4, iteration 1
|
||||
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 10:56:43 02/22/18
|
||||
Level 4, iteration 1
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
Level 4, iteration 2
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
|
||||
Start NBR section for re-routing at 10:56:43 02/22/18
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
|
||||
Start NBR section for post-routing at 10:56:43 02/22/18
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : <n/a>
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 3 secs
|
||||
Total REAL time: 4 secs
|
||||
Completely routed.
|
||||
End of route. 582 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file liron_fpgatop.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a>
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a>
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 3 secs
|
||||
Total REAL time to completion: 5 secs
|
||||
|
||||
par done!
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
34
lattice/fpgatop/liron_fpgatop.dir/5_1_par.asd
Normal file
34
lattice/fpgatop/liron_fpgatop.dir/5_1_par.asd
Normal file
@ -0,0 +1,34 @@
|
||||
[ActiveSupport PAR]
|
||||
; Global primary clocks
|
||||
GLOBAL_PRIMARY_USED = 1;
|
||||
; Global primary clock #0
|
||||
GLOBAL_PRIMARY_0_SIGNALNAME = fclk_c;
|
||||
GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
|
||||
GLOBAL_PRIMARY_0_LOADNUM = 27;
|
||||
; # of global secondary clocks
|
||||
GLOBAL_SECONDARY_USED = 1;
|
||||
; Global secondary clock #0
|
||||
GLOBAL_SECONDARY_0_SIGNALNAME = _devsel_c;
|
||||
GLOBAL_SECONDARY_0_DRIVERTYPE = CLK_PIN;
|
||||
GLOBAL_SECONDARY_0_LOADNUM = 13;
|
||||
GLOBAL_SECONDARY_0_SIGTYPE = CLK;
|
||||
; I/O Bank 0 Usage
|
||||
BANK_0_USED = 12;
|
||||
BANK_0_AVAIL = 19;
|
||||
BANK_0_VCCIO = 3.3V;
|
||||
BANK_0_VREF1 = NA;
|
||||
; I/O Bank 1 Usage
|
||||
BANK_1_USED = 20;
|
||||
BANK_1_AVAIL = 21;
|
||||
BANK_1_VCCIO = 3.3V;
|
||||
BANK_1_VREF1 = NA;
|
||||
; I/O Bank 2 Usage
|
||||
BANK_2_USED = 12;
|
||||
BANK_2_AVAIL = 20;
|
||||
BANK_2_VCCIO = 3.3V;
|
||||
BANK_2_VREF1 = NA;
|
||||
; I/O Bank 3 Usage
|
||||
BANK_3_USED = 8;
|
||||
BANK_3_AVAIL = 20;
|
||||
BANK_3_VCCIO = 3.3V;
|
||||
BANK_3_VREF1 = NA;
|
||||
26
lattice/fpgatop/liron_fpgatop.dir/liron_fpgatop.par
Normal file
26
lattice/fpgatop/liron_fpgatop.dir/liron_fpgatop.par
Normal file
@ -0,0 +1,26 @@
|
||||
PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Feb 22 10:56:39 2018
|
||||
|
||||
C:/lscc/diamond/3.9_x64/ispfpga\bin\nt64\par -f liron_fpgatop.p2t
|
||||
liron_fpgatop_map.ncd liron_fpgatop.dir liron_fpgatop.prf -gui -msgset
|
||||
C:/Users/chamberlin/Documents/Liron/lattice/promote.xml
|
||||
|
||||
|
||||
Preference file: liron_fpgatop.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 - - - - 05 Complete
|
||||
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 5 secs
|
||||
|
||||
par done!
|
||||
2
lattice/fpgatop/liron_fpgatop.drc
Normal file
2
lattice/fpgatop/liron_fpgatop.drc
Normal file
@ -0,0 +1,2 @@
|
||||
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
2767
lattice/fpgatop/liron_fpgatop.jed
Normal file
2767
lattice/fpgatop/liron_fpgatop.jed
Normal file
File diff suppressed because it is too large
Load Diff
4
lattice/fpgatop/liron_fpgatop.lpf
Normal file
4
lattice/fpgatop/liron_fpgatop.lpf
Normal file
@ -0,0 +1,4 @@
|
||||
#BLOCK ASYNCPATHS;
|
||||
#BLOCK RESETPATHS;
|
||||
|
||||
#FREQUENCY 1.000000 MHz;
|
||||
5083
lattice/fpgatop/liron_fpgatop.lsedata
Normal file
5083
lattice/fpgatop/liron_fpgatop.lsedata
Normal file
File diff suppressed because it is too large
Load Diff
468
lattice/fpgatop/liron_fpgatop.mrp
Normal file
468
lattice/fpgatop/liron_fpgatop.mrp
Normal file
@ -0,0 +1,468 @@
|
||||
|
||||
Lattice Mapping Report File for Design Module 'top'
|
||||
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
liron_fpgatop.ngd -o liron_fpgatop_map.ncd -pr liron_fpgatop.prf -mp
|
||||
liron_fpgatop.mrp -lpf
|
||||
C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/liron_fpgatop.lpf -lpf
|
||||
C:/Users/chamberlin/Documents/Liron/lattice/liron.lpf -c 0 -gui -msgset
|
||||
C:/Users/chamberlin/Documents/Liron/lattice/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.9.0.99.2
|
||||
Mapped on: 02/22/18 10:56:38
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 43 out of 1520 (3%)
|
||||
PFU registers: 43 out of 1280 (3%)
|
||||
PIO registers: 0 out of 240 (0%)
|
||||
Number of SLICEs: 58 out of 640 (9%)
|
||||
SLICEs as Logic/ROM: 58 out of 640 (9%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 0 out of 640 (0%)
|
||||
Number of LUT4s: 113 out of 1280 (9%)
|
||||
Number used as logic LUTs: 113
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 0
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 52 + 4(JTAG) out of 80 (70%)
|
||||
Number of block RAMs: 4 out of 7 (57%)
|
||||
Number of GSRs: 1 out of 1 (100%)
|
||||
EFB used : No
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Number of PLLs: 0 out of 1 (0%)
|
||||
Number of DQSDLLs: 0 out of 2 (0%)
|
||||
Number of CLKDIVC: 0 out of 4 (0%)
|
||||
Number of ECLKSYNCA: 0 out of 4 (0%)
|
||||
Number of ECLKBRIDGECS: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 2
|
||||
Net fclk_c: 27 loads, 27 rising, 0 falling (Driver: PIO fclk )
|
||||
Net _devsel_c: 8 loads, 0 rising, 8 falling (Driver: PIO _devsel )
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: top Date: 02/22/18 10:56:38
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Number of Clock Enables: 17
|
||||
Net q7: 1 loads, 1 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_1: 1 loads, 1 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_2: 1 loads, 1 LSLICEs
|
||||
Net myIwm/fclk_c_enable_14: 5 loads, 5 LSLICEs
|
||||
Net myIwm/fclk_c_enable_4: 1 loads, 1 LSLICEs
|
||||
Net myIwm/fclk_c_enable_16: 2 loads, 2 LSLICEs
|
||||
Net myIwm/fclk_c_enable_20: 3 loads, 3 LSLICEs
|
||||
Net myIwm/fclk_c_enable_26: 4 loads, 4 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_3: 1 loads, 1 LSLICEs
|
||||
Net myIwm/fclk_c_enable_30: 3 loads, 3 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_4: 1 loads, 1 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_7: 1 loads, 1 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_8: 1 loads, 1 LSLICEs
|
||||
Net myIwm/fclk_c_enable_27: 1 loads, 1 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_5: 1 loads, 1 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_6: 1 loads, 1 LSLICEs
|
||||
Net n438_c: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 4
|
||||
Net q7: 1 loads, 1 LSLICEs
|
||||
Net myIwm/n302: 3 loads, 3 LSLICEs
|
||||
Net histrobe: 1 loads, 1 LSLICEs
|
||||
Net myIwm/n648: 2 loads, 2 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net q7: 22 loads
|
||||
Net addr_c_0: 17 loads
|
||||
Net addr_c_1: 13 loads
|
||||
Net addr_c_2: 13 loads
|
||||
Net addr_c_3: 13 loads
|
||||
Net q6: 13 loads
|
||||
Net writeBufferEmpty: 12 loads
|
||||
Net myIwm/n142: 11 loads
|
||||
Net myIwm/n1871: 11 loads
|
||||
Net myIwm/bitTimer_3: 10 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 0
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
No errors or warnings present.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[7] | BIDIR | LVCMOS33 | |
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: top Date: 02/22/18 10:56:38
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[6] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[5] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[4] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[3] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[2] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[1] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[0] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| wrdata | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| phase[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| phase[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| phase[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| phase[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _wrreq | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _enbl1 | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _enbl2 | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| select | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _en35 | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| spi_clk | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| spi_mosi | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| spi_cs | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _en245 | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[1] | OUTPUT | LVCMOS33 | |
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: top Date: 02/22/18 10:56:38
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[11] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[10] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[9] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[8] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| fclk | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| q3 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| rw | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _iostrobe | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _iosel | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _devsel | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _reset | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| sense | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| rddata | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| spi_miso | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Removed logic
|
||||
-------------
|
||||
|
||||
Signal _devsel_N_40 was merged into signal _devsel_c
|
||||
Signal myAddrDecoder/_iosel_N_24 was merged into signal n438_c
|
||||
Signal myIwm/n1873 was merged into signal q7
|
||||
Signal VCC_net undriven or does not drive anything - clipped.
|
||||
Signal n1904 undriven or does not drive anything - clipped.
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: top Date: 02/22/18 10:56:38
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Block i1779 was optimized away.
|
||||
Block myAddrDecoder/_iosel_I_0_1_lut was optimized away.
|
||||
Block myIwm/i673_1_lut_rep_31 was optimized away.
|
||||
Block i2 was optimized away.
|
||||
Block m0_lut was optimized away.
|
||||
|
||||
Memory Usage
|
||||
------------
|
||||
|
||||
|
||||
|
||||
INFO: Design contains EBR with GSR enabled. The GSR is only applicable for
|
||||
output registers except FIFO.
|
||||
/myROM:
|
||||
EBRs: 4
|
||||
RAM SLICEs: 0
|
||||
Logic SLICEs: 0
|
||||
PFU Registers: 0
|
||||
-Contains EBR codeROM_0_0_3_0: TYPE= DP8KC, Width_A= 2, Depth_A= 4096,
|
||||
REGMODE_A= OUTREG, REGMODE_B= NOREG, RESETMODE= SYNC,
|
||||
ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL,
|
||||
GSR= ENABLED, MEM_INIT_FILE= rom-full-4k.mem, MEM_LPC_FILE=
|
||||
codeROM.lpc
|
||||
-Contains EBR codeROM_0_0_1_2: TYPE= DP8KC, Width_A= 2, Depth_A= 4096,
|
||||
REGMODE_A= OUTREG, REGMODE_B= NOREG, RESETMODE= SYNC,
|
||||
ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL,
|
||||
GSR= ENABLED, MEM_INIT_FILE= rom-full-4k.mem, MEM_LPC_FILE=
|
||||
codeROM.lpc
|
||||
-Contains EBR codeROM_0_0_0_3: TYPE= DP8KC, Width_A= 2, Depth_A= 4096,
|
||||
REGMODE_A= OUTREG, REGMODE_B= NOREG, RESETMODE= SYNC,
|
||||
ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL,
|
||||
GSR= ENABLED, MEM_INIT_FILE= rom-full-4k.mem, MEM_LPC_FILE=
|
||||
codeROM.lpc
|
||||
-Contains EBR codeROM_0_0_2_1: TYPE= DP8KC, Width_A= 2, Depth_A= 4096,
|
||||
REGMODE_A= OUTREG, REGMODE_B= NOREG, RESETMODE= SYNC,
|
||||
ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL,
|
||||
GSR= ENABLED, MEM_INIT_FILE= rom-full-4k.mem, MEM_LPC_FILE=
|
||||
codeROM.lpc
|
||||
|
||||
|
||||
|
||||
ASIC Components
|
||||
---------------
|
||||
|
||||
Instance Name: myROM/codeROM_0_0_3_0
|
||||
Type: DP8KC
|
||||
Instance Name: myROM/codeROM_0_0_1_2
|
||||
Type: DP8KC
|
||||
Instance Name: myROM/codeROM_0_0_0_3
|
||||
Type: DP8KC
|
||||
Instance Name: myROM/codeROM_0_0_2_1
|
||||
Type: DP8KC
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: top Date: 02/22/18 10:56:38
|
||||
|
||||
GSR Usage
|
||||
---------
|
||||
|
||||
GSR Component:
|
||||
The Global Set Reset (GSR) resource has been used to implement a global reset
|
||||
of the design. The reset signal used for GSR control is 'n440_c'.
|
||||
|
||||
|
||||
GSR Property:
|
||||
The design components with GSR property set to ENABLED will respond to global
|
||||
set reset while the components with GSR property set to DISABLED will
|
||||
not.
|
||||
|
||||
|
||||
Components with disabled GSR Property
|
||||
-------------------------------------
|
||||
|
||||
These components have the GSR property set to DISABLED. The components will
|
||||
not respond to the reset signal 'n440_c' via the GSR component.
|
||||
|
||||
Type and number of components of the type:
|
||||
Register = 17
|
||||
|
||||
Type and instance name of component:
|
||||
Register : myIwm/rddataSync_i0
|
||||
Register : myIwm/shifter_i0_i0
|
||||
Register : myIwm/bitTimer__i0
|
||||
Register : myIwm/rddataSync_i1
|
||||
Register : myIwm/shifter_i0_i1
|
||||
Register : myIwm/shifter_i0_i2
|
||||
Register : myIwm/shifter_i0_i3
|
||||
Register : myIwm/shifter_i0_i4
|
||||
Register : myIwm/shifter_i0_i5
|
||||
Register : myIwm/shifter_i0_i6
|
||||
Register : myIwm/shifter_i0_i7
|
||||
Register : myIwm/bitTimer__i1
|
||||
Register : myIwm/bitTimer__i2
|
||||
Register : myIwm/bitTimer__i3
|
||||
Register : myIwm/bitTimer__i4
|
||||
Register : myIwm/bitTimer__i5
|
||||
Register : myAddrDecoder/romExpansionActive_16
|
||||
|
||||
Components with synchronous local reset also reset by asynchronous GSR
|
||||
----------------------------------------------------------------------
|
||||
|
||||
These components have the GSR property set to ENABLED and the local reset
|
||||
is synchronous. The components will respond to the synchronous local reset
|
||||
and to the unrelated asynchronous reset signal 'n440_c' via the GSR
|
||||
component.
|
||||
|
||||
Type and number of components of the type:
|
||||
Register = 4
|
||||
DP8KC = 4
|
||||
|
||||
Type and instance name of component:
|
||||
Register : myIwm/_underrun_125
|
||||
Register : myIwm/clearBufferTimer_i0_i3
|
||||
Register : myIwm/clearBufferTimer_i0_i2
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: top Date: 02/22/18 10:56:38
|
||||
|
||||
GSR Usage (cont)
|
||||
----------------
|
||||
Register : myIwm/clearBufferTimer_i0_i1
|
||||
DP8KC : myROM/codeROM_0_0_3_0
|
||||
DP8KC : myROM/codeROM_0_0_1_2
|
||||
DP8KC : myROM/codeROM_0_0_0_3
|
||||
DP8KC : myROM/codeROM_0_0_2_1
|
||||
|
||||
EBR components with enabled GSR
|
||||
-------------------------------
|
||||
|
||||
These EBR components have the GSR property set to ENABLED. The components
|
||||
will respond to the asynchronous reset signal 'n440_c' via the GSR
|
||||
component.
|
||||
|
||||
Type and number of components of the type:
|
||||
DP8KC = 4
|
||||
|
||||
Type and instance name of component:
|
||||
DP8KC : myROM/codeROM_0_0_3_0
|
||||
DP8KC : myROM/codeROM_0_0_1_2
|
||||
DP8KC : myROM/codeROM_0_0_0_3
|
||||
DP8KC : myROM/codeROM_0_0_2_1
|
||||
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 38 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 7
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
BIN
lattice/fpgatop/liron_fpgatop.ncd
Normal file
BIN
lattice/fpgatop/liron_fpgatop.ncd
Normal file
Binary file not shown.
BIN
lattice/fpgatop/liron_fpgatop.ngd
Normal file
BIN
lattice/fpgatop/liron_fpgatop.ngd
Normal file
Binary file not shown.
9
lattice/fpgatop/liron_fpgatop.p2t
Normal file
9
lattice/fpgatop/liron_fpgatop.p2t
Normal file
@ -0,0 +1,9 @@
|
||||
-w
|
||||
-l 5
|
||||
-i 6
|
||||
-n 1
|
||||
-t 1
|
||||
-s 1
|
||||
-c 0
|
||||
-e 0
|
||||
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF
|
||||
5
lattice/fpgatop/liron_fpgatop.p3t
Normal file
5
lattice/fpgatop/liron_fpgatop.p3t
Normal file
@ -0,0 +1,5 @@
|
||||
-rem
|
||||
-distrce
|
||||
-log "liron_fpgatop.log"
|
||||
-o "liron_fpgatop.csv"
|
||||
-pr "liron_fpgatop.prf"
|
||||
279
lattice/fpgatop/liron_fpgatop.pad
Normal file
279
lattice/fpgatop/liron_fpgatop.pad
Normal file
@ -0,0 +1,279 @@
|
||||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-1200HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.42
|
||||
|
||||
Thu Feb 22 10:56:42 2018
|
||||
|
||||
Pinout by Port Name:
|
||||
+--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| _devsel | 34/2 | LVCMOS33_IN | PB9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| _en245 | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| _en35 | 98/0 | LVCMOS33_OUT | PT9B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| _enbl1 | 82/0 | LVCMOS33_OUT | PT15C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| _enbl2 | 99/0 | LVCMOS33_OUT | PT9A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| _iosel | 53/1 | LVCMOS33_IN | PR9D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| _iostrobe | 74/1 | LVCMOS33_IN | PR2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| _reset | 75/1 | LVCMOS33_IN | PR2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| _wrreq | 88/0 | LVCMOS33_OUT | PT12A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| addr[0] | 54/1 | LVCMOS33_IN | PR9C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[10] | 68/1 | LVCMOS33_IN | PR4B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[11] | 69/1 | LVCMOS33_IN | PR4A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[1] | 57/1 | LVCMOS33_IN | PR9B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[2] | 58/1 | LVCMOS33_IN | PR9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[3] | 59/1 | LVCMOS33_IN | PR8D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[4] | 60/1 | LVCMOS33_IN | PR8C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[5] | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[6] | 64/1 | LVCMOS33_IN | PR5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[7] | 65/1 | LVCMOS33_IN | PR5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[8] | 66/1 | LVCMOS33_IN | PR4D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[9] | 67/1 | LVCMOS33_IN | PR4C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| data[0] | 35/2 | LVCMOS33_BIDI | PB9B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[1] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[2] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[3] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[4] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[5] | 47/2 | LVCMOS33_BIDI | PB18D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[6] | 51/1 | LVCMOS33_BIDI | PR10D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[7] | 52/1 | LVCMOS33_BIDI | PR10C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| debugInfo[0] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[1] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[2] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[3] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[4] | 16/3 | LVCMOS33_OUT | PL8A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[5] | 17/3 | LVCMOS33_OUT | PL8B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[6] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[7] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| fclk | 63/1 | LVCMOS33_IN | PR5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| phase[0] | 84/0 | LVCMOS33_OUT | PT15A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| phase[1] | 85/0 | LVCMOS33_OUT | PT12D | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| phase[2] | 86/0 | LVCMOS33_OUT | PT12C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| phase[3] | 87/0 | LVCMOS33_OUT | PT12B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| q3 | 70/1 | LVCMOS33_IN | PR3B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| rddata | 96/0 | LVCMOS33_IN | PT10B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| rw | 71/1 | LVCMOS33_IN | PR3A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| select | 78/0 | LVCMOS33_OUT | PT16C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| sense | 97/0 | LVCMOS33_IN | PT10A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| spi_clk | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| spi_cs | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| spi_miso | 32/2 | LVCMOS33_IN | PB6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| spi_mosi | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| wrdata | 83/0 | LVCMOS33_OUT | PT15B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
+--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | unused, PULL:DOWN | | | PL2C | L_GPLLT_IN | | |
|
||||
| 2/3 | unused, PULL:DOWN | | | PL2D | L_GPLLC_IN | | |
|
||||
| 3/3 | unused, PULL:DOWN | | | PL3A | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3C | | | |
|
||||
| 8/3 | unused, PULL:DOWN | | | PL3D | | | |
|
||||
| 9/3 | unused, PULL:DOWN | | | PL4A | | | |
|
||||
| 10/3 | unused, PULL:DOWN | | | PL4B | | | |
|
||||
| 12/3 | debugInfo[0] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | debugInfo[1] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | debugInfo[2] | LOCATED | LVCMOS33_OUT | PL5C | | | |
|
||||
| 15/3 | debugInfo[3] | LOCATED | LVCMOS33_OUT | PL5D | | | |
|
||||
| 16/3 | debugInfo[4] | LOCATED | LVCMOS33_OUT | PL8A | | | |
|
||||
| 17/3 | debugInfo[5] | LOCATED | LVCMOS33_OUT | PL8B | | | |
|
||||
| 18/3 | unused, PULL:DOWN | | | PL8C | | | |
|
||||
| 19/3 | unused, PULL:DOWN | | | PL8D | | | |
|
||||
| 20/3 | unused, PULL:DOWN | | | PL9A | PCLKT3_0 | | |
|
||||
| 21/3 | unused, PULL:DOWN | | | PL9B | PCLKC3_0 | | |
|
||||
| 24/3 | debugInfo[6] | LOCATED | LVCMOS33_OUT | PL10C | | | |
|
||||
| 25/3 | debugInfo[7] | LOCATED | LVCMOS33_OUT | PL10D | | | |
|
||||
| 27/2 | spi_cs | LOCATED | LVCMOS33_OUT | PB4C | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB6A | | | |
|
||||
| 30/2 | _en245 | LOCATED | LVCMOS33_OUT | PB6B | | | |
|
||||
| 31/2 | spi_clk | LOCATED | LVCMOS33_OUT | PB6C | MCLK/CCLK | | |
|
||||
| 32/2 | spi_miso | LOCATED | LVCMOS33_IN | PB6D | SO/SPISO | | |
|
||||
| 34/2 | _devsel | LOCATED | LVCMOS33_IN | PB9A | PCLKT2_0 | | |
|
||||
| 35/2 | data[0] | LOCATED | LVCMOS33_BIDI | PB9B | PCLKC2_0 | | |
|
||||
| 36/2 | data[1] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
|
||||
| 37/2 | data[2] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
|
||||
| 38/2 | data[3] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
|
||||
| 39/2 | data[4] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
|
||||
| 40/2 | unused, PULL:DOWN | | | PB15A | | | |
|
||||
| 41/2 | unused, PULL:DOWN | | | PB15B | | | |
|
||||
| 42/2 | unused, PULL:DOWN | | | PB18A | | | |
|
||||
| 43/2 | unused, PULL:DOWN | | | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | data[5] | LOCATED | LVCMOS33_BIDI | PB18D | | | |
|
||||
| 48/2 | Prohibited/Reserved | PROHIBITED | | PB20C | SN | | |
|
||||
| 49/2 | spi_mosi | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | data[6] | LOCATED | LVCMOS33_BIDI | PR10D | DQ1 | | |
|
||||
| 52/1 | data[7] | LOCATED | LVCMOS33_BIDI | PR10C | DQ1 | | |
|
||||
| 53/1 | _iosel | LOCATED | LVCMOS33_IN | PR9D | DQ1 | | |
|
||||
| 54/1 | addr[0] | LOCATED | LVCMOS33_IN | PR9C | DQ1 | | |
|
||||
| 57/1 | addr[1] | LOCATED | LVCMOS33_IN | PR9B | DQ1 | | |
|
||||
| 58/1 | addr[2] | LOCATED | LVCMOS33_IN | PR9A | DQ1 | | |
|
||||
| 59/1 | addr[3] | LOCATED | LVCMOS33_IN | PR8D | DQ1 | | |
|
||||
| 60/1 | addr[4] | LOCATED | LVCMOS33_IN | PR8C | DQ1 | | |
|
||||
| 61/1 | Prohibited/Reserved | PROHIBITED | | PR8A | DQS1 | | |
|
||||
| 62/1 | addr[5] | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | fclk | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | addr[6] | LOCATED | LVCMOS33_IN | PR5B | DQS0N | | |
|
||||
| 65/1 | addr[7] | LOCATED | LVCMOS33_IN | PR5A | DQS0 | | |
|
||||
| 66/1 | addr[8] | LOCATED | LVCMOS33_IN | PR4D | DQ0 | | |
|
||||
| 67/1 | addr[9] | LOCATED | LVCMOS33_IN | PR4C | DQ0 | | |
|
||||
| 68/1 | addr[10] | LOCATED | LVCMOS33_IN | PR4B | DQ0 | | |
|
||||
| 69/1 | addr[11] | LOCATED | LVCMOS33_IN | PR4A | DQ0 | | |
|
||||
| 70/1 | q3 | LOCATED | LVCMOS33_IN | PR3B | DQ0 | | |
|
||||
| 71/1 | rw | LOCATED | LVCMOS33_IN | PR3A | DQ0 | | |
|
||||
| 74/1 | _iostrobe | LOCATED | LVCMOS33_IN | PR2B | DQ0 | | |
|
||||
| 75/1 | _reset | LOCATED | LVCMOS33_IN | PR2A | DQ0 | | |
|
||||
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | select | LOCATED | LVCMOS33_OUT | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | _enbl1 | LOCATED | LVCMOS33_OUT | PT15C | JTAGENB | | |
|
||||
| 83/0 | wrdata | LOCATED | LVCMOS33_OUT | PT15B | | | |
|
||||
| 84/0 | phase[0] | LOCATED | LVCMOS33_OUT | PT15A | | | |
|
||||
| 85/0 | phase[1] | LOCATED | LVCMOS33_OUT | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | phase[2] | LOCATED | LVCMOS33_OUT | PT12C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | phase[3] | LOCATED | LVCMOS33_OUT | PT12B | PCLKC0_1 | | |
|
||||
| 88/0 | _wrreq | LOCATED | LVCMOS33_OUT | PT12A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
|
||||
| 96/0 | rddata | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 97/0 | sense | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 98/0 | _en35 | LOCATED | LVCMOS33_OUT | PT9B | | | |
|
||||
| 99/0 | _enbl2 | LOCATED | LVCMOS33_OUT | PT9A | | | |
|
||||
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
|
||||
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
|
||||
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
|
||||
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
|
||||
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
|
||||
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
|
||||
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
|
||||
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
|
||||
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
|
||||
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
|
||||
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
|
||||
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
|
||||
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
|
||||
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
|
||||
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
|
||||
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
|
||||
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
|
||||
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
|
||||
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
|
||||
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
|
||||
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
|
||||
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
|
||||
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
|
||||
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
|
||||
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "_devsel" SITE "34";
|
||||
LOCATE COMP "_en245" SITE "30";
|
||||
LOCATE COMP "_en35" SITE "98";
|
||||
LOCATE COMP "_enbl1" SITE "82";
|
||||
LOCATE COMP "_enbl2" SITE "99";
|
||||
LOCATE COMP "_iosel" SITE "53";
|
||||
LOCATE COMP "_iostrobe" SITE "74";
|
||||
LOCATE COMP "_reset" SITE "75";
|
||||
LOCATE COMP "_wrreq" SITE "88";
|
||||
LOCATE COMP "addr[0]" SITE "54";
|
||||
LOCATE COMP "addr[10]" SITE "68";
|
||||
LOCATE COMP "addr[11]" SITE "69";
|
||||
LOCATE COMP "addr[1]" SITE "57";
|
||||
LOCATE COMP "addr[2]" SITE "58";
|
||||
LOCATE COMP "addr[3]" SITE "59";
|
||||
LOCATE COMP "addr[4]" SITE "60";
|
||||
LOCATE COMP "addr[5]" SITE "62";
|
||||
LOCATE COMP "addr[6]" SITE "64";
|
||||
LOCATE COMP "addr[7]" SITE "65";
|
||||
LOCATE COMP "addr[8]" SITE "66";
|
||||
LOCATE COMP "addr[9]" SITE "67";
|
||||
LOCATE COMP "data[0]" SITE "35";
|
||||
LOCATE COMP "data[1]" SITE "36";
|
||||
LOCATE COMP "data[2]" SITE "37";
|
||||
LOCATE COMP "data[3]" SITE "38";
|
||||
LOCATE COMP "data[4]" SITE "39";
|
||||
LOCATE COMP "data[5]" SITE "47";
|
||||
LOCATE COMP "data[6]" SITE "51";
|
||||
LOCATE COMP "data[7]" SITE "52";
|
||||
LOCATE COMP "debugInfo[0]" SITE "12";
|
||||
LOCATE COMP "debugInfo[1]" SITE "13";
|
||||
LOCATE COMP "debugInfo[2]" SITE "14";
|
||||
LOCATE COMP "debugInfo[3]" SITE "15";
|
||||
LOCATE COMP "debugInfo[4]" SITE "16";
|
||||
LOCATE COMP "debugInfo[5]" SITE "17";
|
||||
LOCATE COMP "debugInfo[6]" SITE "24";
|
||||
LOCATE COMP "debugInfo[7]" SITE "25";
|
||||
LOCATE COMP "fclk" SITE "63";
|
||||
LOCATE COMP "phase[0]" SITE "84";
|
||||
LOCATE COMP "phase[1]" SITE "85";
|
||||
LOCATE COMP "phase[2]" SITE "86";
|
||||
LOCATE COMP "phase[3]" SITE "87";
|
||||
LOCATE COMP "q3" SITE "70";
|
||||
LOCATE COMP "rddata" SITE "96";
|
||||
LOCATE COMP "rw" SITE "71";
|
||||
LOCATE COMP "select" SITE "78";
|
||||
LOCATE COMP "sense" SITE "97";
|
||||
LOCATE COMP "spi_clk" SITE "31";
|
||||
LOCATE COMP "spi_cs" SITE "27";
|
||||
LOCATE COMP "spi_miso" SITE "32";
|
||||
LOCATE COMP "spi_mosi" SITE "49";
|
||||
LOCATE COMP "wrdata" SITE "83";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Feb 22 10:56:42 2018
|
||||
|
||||
226
lattice/fpgatop/liron_fpgatop.par
Normal file
226
lattice/fpgatop/liron_fpgatop.par
Normal file
@ -0,0 +1,226 @@
|
||||
PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Feb 22 10:56:39 2018
|
||||
|
||||
C:/lscc/diamond/3.9_x64/ispfpga\bin\nt64\par -f liron_fpgatop.p2t
|
||||
liron_fpgatop_map.ncd liron_fpgatop.dir liron_fpgatop.prf -gui -msgset
|
||||
C:/Users/chamberlin/Documents/Liron/lattice/promote.xml
|
||||
|
||||
|
||||
Preference file: liron_fpgatop.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 - - - - 05 Complete
|
||||
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 5 secs
|
||||
|
||||
par done!
|
||||
|
||||
Lattice Place and Route Report for Design "liron_fpgatop_map.ncd"
|
||||
Thu Feb 22 10:56:39 2018
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF liron_fpgatop_map.ncd liron_fpgatop.dir/5_1.ncd liron_fpgatop.prf
|
||||
Preference file: liron_fpgatop.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file liron_fpgatop_map.ncd.
|
||||
Design name: top
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
|
||||
Package Status: Final Version 1.42.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 52+4(JTAG)/108 52% used
|
||||
52+4(JTAG)/80 70% bonded
|
||||
|
||||
SLICE 58/640 9% used
|
||||
|
||||
GSR 1/1 100% used
|
||||
EBR 4/7 57% used
|
||||
|
||||
|
||||
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
|
||||
Number of Signals: 193
|
||||
Number of Connections: 582
|
||||
|
||||
Pin Constraint Summary:
|
||||
52 out of 52 pins locked (100% locked).
|
||||
|
||||
The following 1 signal is selected to use the primary clock routing resources:
|
||||
fclk_c (driver: fclk, clk load #: 27)
|
||||
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
_devsel_c (driver: _devsel, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
|
||||
Signal n440_c is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
.........
|
||||
Finished Placer Phase 0. REAL time: 2 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 43211.
|
||||
Finished Placer Phase 1. REAL time: 3 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 43211
|
||||
Finished Placer Phase 2. REAL time: 3 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 2 out of 8 (25%)
|
||||
PLL : 0 out of 1 (0%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Quadrants All (TL, TR, BL, BR) - Global Clocks:
|
||||
PRIMARY "fclk_c" from comp "fclk" on CLK_PIN site "63 (PR5C)", clk load = 27
|
||||
SECONDARY "_devsel_c" from comp "_devsel" on CLK_PIN site "34 (PB9A)", clk load = 8, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 1 out of 8 (12%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
Edge Clocks:
|
||||
No edge clock selected.
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
52 + 4(JTAG) out of 108 (51.9%) PIO sites used.
|
||||
52 + 4(JTAG) out of 80 (70.0%) bonded PIO sites used.
|
||||
Number of PIO comps: 52; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 12 / 19 ( 63%) | 3.3V | - |
|
||||
| 1 | 20 / 21 ( 95%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 3 | 8 / 20 ( 40%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 2 secs
|
||||
|
||||
Dumping design to file liron_fpgatop.dir/5_1.ncd.
|
||||
|
||||
|
||||
-----------------------------------------------------------------
|
||||
INFO - par: ASE feature is off due to non timing-driven settings.
|
||||
-----------------------------------------------------------------
|
||||
|
||||
0 connections routed; 582 unrouted.
|
||||
Starting router resource preassignment
|
||||
|
||||
Completed router resource preassignment. Real time: 4 secs
|
||||
|
||||
Start NBR router at 10:56:43 02/22/18
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 10:56:43 02/22/18
|
||||
|
||||
Start NBR section for initial routing at 10:56:43 02/22/18
|
||||
Level 4, iteration 1
|
||||
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 10:56:43 02/22/18
|
||||
Level 4, iteration 1
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
Level 4, iteration 2
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
|
||||
Start NBR section for re-routing at 10:56:43 02/22/18
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
|
||||
Start NBR section for post-routing at 10:56:43 02/22/18
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : <n/a>
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 3 secs
|
||||
Total REAL time: 4 secs
|
||||
Completely routed.
|
||||
End of route. 582 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file liron_fpgatop.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a>
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a>
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 3 secs
|
||||
Total REAL time to completion: 5 secs
|
||||
|
||||
par done!
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
67
lattice/fpgatop/liron_fpgatop.prf
Normal file
67
lattice/fpgatop/liron_fpgatop.prf
Normal file
@ -0,0 +1,67 @@
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.9.0.99.2 -- WARNING: Map write only section -- Thu Feb 22 10:56:39 2018
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "data[7]" SITE "52" ;
|
||||
LOCATE COMP "data[6]" SITE "51" ;
|
||||
LOCATE COMP "data[5]" SITE "47" ;
|
||||
LOCATE COMP "data[4]" SITE "39" ;
|
||||
LOCATE COMP "data[3]" SITE "38" ;
|
||||
LOCATE COMP "data[2]" SITE "37" ;
|
||||
LOCATE COMP "data[1]" SITE "36" ;
|
||||
LOCATE COMP "data[0]" SITE "35" ;
|
||||
LOCATE COMP "wrdata" SITE "83" ;
|
||||
LOCATE COMP "phase[3]" SITE "87" ;
|
||||
LOCATE COMP "phase[2]" SITE "86" ;
|
||||
LOCATE COMP "phase[1]" SITE "85" ;
|
||||
LOCATE COMP "phase[0]" SITE "84" ;
|
||||
LOCATE COMP "_wrreq" SITE "88" ;
|
||||
LOCATE COMP "_enbl1" SITE "82" ;
|
||||
LOCATE COMP "_enbl2" SITE "99" ;
|
||||
LOCATE COMP "select" SITE "78" ;
|
||||
LOCATE COMP "_en35" SITE "98" ;
|
||||
LOCATE COMP "spi_clk" SITE "31" ;
|
||||
LOCATE COMP "spi_mosi" SITE "49" ;
|
||||
LOCATE COMP "spi_cs" SITE "27" ;
|
||||
LOCATE COMP "_en245" SITE "30" ;
|
||||
LOCATE COMP "debugInfo[7]" SITE "25" ;
|
||||
LOCATE COMP "debugInfo[6]" SITE "24" ;
|
||||
LOCATE COMP "debugInfo[5]" SITE "17" ;
|
||||
LOCATE COMP "debugInfo[4]" SITE "16" ;
|
||||
LOCATE COMP "debugInfo[3]" SITE "15" ;
|
||||
LOCATE COMP "debugInfo[2]" SITE "14" ;
|
||||
LOCATE COMP "debugInfo[1]" SITE "13" ;
|
||||
LOCATE COMP "debugInfo[0]" SITE "12" ;
|
||||
LOCATE COMP "addr[11]" SITE "69" ;
|
||||
LOCATE COMP "addr[10]" SITE "68" ;
|
||||
LOCATE COMP "addr[9]" SITE "67" ;
|
||||
LOCATE COMP "addr[8]" SITE "66" ;
|
||||
LOCATE COMP "addr[7]" SITE "65" ;
|
||||
LOCATE COMP "addr[6]" SITE "64" ;
|
||||
LOCATE COMP "addr[5]" SITE "62" ;
|
||||
LOCATE COMP "addr[4]" SITE "60" ;
|
||||
LOCATE COMP "addr[3]" SITE "59" ;
|
||||
LOCATE COMP "addr[2]" SITE "58" ;
|
||||
LOCATE COMP "addr[1]" SITE "57" ;
|
||||
LOCATE COMP "addr[0]" SITE "54" ;
|
||||
LOCATE COMP "fclk" SITE "63" ;
|
||||
LOCATE COMP "q3" SITE "70" ;
|
||||
LOCATE COMP "rw" SITE "71" ;
|
||||
LOCATE COMP "_iostrobe" SITE "74" ;
|
||||
LOCATE COMP "_iosel" SITE "53" ;
|
||||
LOCATE COMP "_devsel" SITE "34" ;
|
||||
LOCATE COMP "_reset" SITE "75" ;
|
||||
LOCATE COMP "sense" SITE "97" ;
|
||||
LOCATE COMP "rddata" SITE "96" ;
|
||||
LOCATE COMP "spi_miso" SITE "32" ;
|
||||
SCHEMATIC END ;
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
PROHIBIT SITE "48" ;
|
||||
PROHIBIT SITE "61" ;
|
||||
COMMERCIAL ;
|
||||
|
||||
// No timing preferences found. TRCE invokes auto-generation of timing preferences
|
||||
// Section Autogen
|
||||
FREQUENCY NET "fclk_c" 149.993 MHz ;
|
||||
// End Section Autogen
|
||||
10
lattice/fpgatop/liron_fpgatop.pt
Normal file
10
lattice/fpgatop/liron_fpgatop.pt
Normal file
@ -0,0 +1,10 @@
|
||||
-v
|
||||
10
|
||||
|
||||
|
||||
|
||||
|
||||
-gt
|
||||
-sethld
|
||||
-sp 4
|
||||
-sphld m
|
||||
5
lattice/fpgatop/liron_fpgatop.t2b
Normal file
5
lattice/fpgatop/liron_fpgatop.t2b
Normal file
@ -0,0 +1,5 @@
|
||||
|
||||
|
||||
-g RamCfg:Reset
|
||||
|
||||
-path "C:/Users/chamberlin/Documents/Liron/lattice"
|
||||
1163
lattice/fpgatop/liron_fpgatop.twr
Normal file
1163
lattice/fpgatop/liron_fpgatop.twr
Normal file
File diff suppressed because it is too large
Load Diff
148
lattice/fpgatop/liron_fpgatop_bgn.html
Normal file
148
lattice/fpgatop/liron_fpgatop_bgn.html
Normal file
@ -0,0 +1,148 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Bitgen Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.9.0.99.2
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path C:/Users/chamberlin/Documents/Liron/lattice -w -jedec -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml liron_fpgatop.ncd liron_fpgatop.prf
|
||||
|
||||
Loading design for application Bitgen from file liron_fpgatop.ncd.
|
||||
Design name: top
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
|
||||
Package Status: Final Version 1.42.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from liron_fpgatop.prf.
|
||||
|
||||
<A name="bgn_ps"></A>
|
||||
<B><U><big>Preference Summary:</big></U></B>
|
||||
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.94.
|
||||
|
||||
Saving bit stream in "liron_fpgatop.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 511 Pages (128*511 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 0 Page.
|
||||
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
44
lattice/fpgatop/liron_fpgatop_lattice.synproj
Normal file
44
lattice/fpgatop/liron_fpgatop_lattice.synproj
Normal file
@ -0,0 +1,44 @@
|
||||
-a "MachXO2"
|
||||
-d LCMXO2-1200HC
|
||||
-t TQFP100
|
||||
-s 4
|
||||
|
||||
-optimization_goal Balanced
|
||||
-bram_utilization 100
|
||||
-ramstyle Auto
|
||||
-romstyle auto
|
||||
-dsp_utilization 100
|
||||
-use_dsp 1
|
||||
-use_carry_chain 1
|
||||
-carry_chain_length 0
|
||||
-force_gsr Auto
|
||||
-resource_sharing 1
|
||||
-propagate_constants 1
|
||||
-remove_duplicate_regs 1
|
||||
-mux_style Auto
|
||||
-max_fanout 1000
|
||||
-fsm_encoding_style Auto
|
||||
-twr_paths 3
|
||||
-fix_gated_clocks 1
|
||||
-loop_limit 1950
|
||||
|
||||
|
||||
|
||||
-use_io_insertion 1
|
||||
-resolve_mixed_drivers 0
|
||||
-use_io_reg auto
|
||||
|
||||
|
||||
-lpf 1
|
||||
-p "C:/Users/chamberlin/Documents/Liron/lattice"
|
||||
-ver "C:/Users/chamberlin/Documents/Liron/lattice/top.v"
|
||||
"C:/Users/chamberlin/Documents/Liron/lattice/addrDecoder.v"
|
||||
"C:/Users/chamberlin/Documents/Liron/lattice/iwm.v"
|
||||
"C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v"
|
||||
-top top
|
||||
|
||||
|
||||
-p "C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data" "C:/Users/chamberlin/Documents/Liron/lattice/fpgatop" "C:/Users/chamberlin/Documents/Liron/lattice"
|
||||
|
||||
-ngd "liron_fpgatop.ngd"
|
||||
|
||||
69
lattice/fpgatop/liron_fpgatop_map.asd
Normal file
69
lattice/fpgatop/liron_fpgatop_map.asd
Normal file
@ -0,0 +1,69 @@
|
||||
[ActiveSupport MAP]
|
||||
Device = LCMXO2-1200HC;
|
||||
Package = TQFP100;
|
||||
Performance = 4;
|
||||
LUTS_avail = 1280;
|
||||
LUTS_used = 113;
|
||||
FF_avail = 1360;
|
||||
FF_used = 43;
|
||||
INPUT_LVCMOS33 = 22;
|
||||
OUTPUT_LVCMOS33 = 22;
|
||||
BIDI_LVCMOS33 = 8;
|
||||
IO_avail = 80;
|
||||
IO_used = 52;
|
||||
EBR_avail = 7;
|
||||
EBR_used = 4;
|
||||
; Begin EBR Section
|
||||
Instance_Name = myROM/codeROM_0_0_3_0;
|
||||
Type = DP8KC;
|
||||
Width_A = 2;
|
||||
Depth_A = 4096;
|
||||
REGMODE_A = OUTREG;
|
||||
REGMODE_B = NOREG;
|
||||
RESETMODE = SYNC;
|
||||
ASYNC_RESET_RELEASE = SYNC;
|
||||
WRITEMODE_A = NORMAL;
|
||||
WRITEMODE_B = NORMAL;
|
||||
GSR = ENABLED;
|
||||
MEM_INIT_FILE = rom-full-4k.mem;
|
||||
MEM_LPC_FILE = codeROM.lpc;
|
||||
Instance_Name = myROM/codeROM_0_0_1_2;
|
||||
Type = DP8KC;
|
||||
Width_A = 2;
|
||||
Depth_A = 4096;
|
||||
REGMODE_A = OUTREG;
|
||||
REGMODE_B = NOREG;
|
||||
RESETMODE = SYNC;
|
||||
ASYNC_RESET_RELEASE = SYNC;
|
||||
WRITEMODE_A = NORMAL;
|
||||
WRITEMODE_B = NORMAL;
|
||||
GSR = ENABLED;
|
||||
MEM_INIT_FILE = rom-full-4k.mem;
|
||||
MEM_LPC_FILE = codeROM.lpc;
|
||||
Instance_Name = myROM/codeROM_0_0_0_3;
|
||||
Type = DP8KC;
|
||||
Width_A = 2;
|
||||
Depth_A = 4096;
|
||||
REGMODE_A = OUTREG;
|
||||
REGMODE_B = NOREG;
|
||||
RESETMODE = SYNC;
|
||||
ASYNC_RESET_RELEASE = SYNC;
|
||||
WRITEMODE_A = NORMAL;
|
||||
WRITEMODE_B = NORMAL;
|
||||
GSR = ENABLED;
|
||||
MEM_INIT_FILE = rom-full-4k.mem;
|
||||
MEM_LPC_FILE = codeROM.lpc;
|
||||
Instance_Name = myROM/codeROM_0_0_2_1;
|
||||
Type = DP8KC;
|
||||
Width_A = 2;
|
||||
Depth_A = 4096;
|
||||
REGMODE_A = OUTREG;
|
||||
REGMODE_B = NOREG;
|
||||
RESETMODE = SYNC;
|
||||
ASYNC_RESET_RELEASE = SYNC;
|
||||
WRITEMODE_A = NORMAL;
|
||||
WRITEMODE_B = NORMAL;
|
||||
GSR = ENABLED;
|
||||
MEM_INIT_FILE = rom-full-4k.mem;
|
||||
MEM_LPC_FILE = codeROM.lpc;
|
||||
; End EBR Section
|
||||
68
lattice/fpgatop/liron_fpgatop_map.cam
Normal file
68
lattice/fpgatop/liron_fpgatop_map.cam
Normal file
@ -0,0 +1,68 @@
|
||||
[ START MERGED ]
|
||||
_devsel_N_40 _devsel_c
|
||||
myIwm/n1873 q7
|
||||
myAddrDecoder/_iosel_N_24 n438_c
|
||||
[ END MERGED ]
|
||||
[ START CLIPPED ]
|
||||
VCC_net
|
||||
n1904
|
||||
[ END CLIPPED ]
|
||||
[ START DESIGN PREFS ]
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.9.0.99.2 -- WARNING: Map write only section -- Thu Feb 22 10:56:39 2018
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "data[7]" SITE "52" ;
|
||||
LOCATE COMP "data[6]" SITE "51" ;
|
||||
LOCATE COMP "data[5]" SITE "47" ;
|
||||
LOCATE COMP "data[4]" SITE "39" ;
|
||||
LOCATE COMP "data[3]" SITE "38" ;
|
||||
LOCATE COMP "data[2]" SITE "37" ;
|
||||
LOCATE COMP "data[1]" SITE "36" ;
|
||||
LOCATE COMP "data[0]" SITE "35" ;
|
||||
LOCATE COMP "wrdata" SITE "83" ;
|
||||
LOCATE COMP "phase[3]" SITE "87" ;
|
||||
LOCATE COMP "phase[2]" SITE "86" ;
|
||||
LOCATE COMP "phase[1]" SITE "85" ;
|
||||
LOCATE COMP "phase[0]" SITE "84" ;
|
||||
LOCATE COMP "_wrreq" SITE "88" ;
|
||||
LOCATE COMP "_enbl1" SITE "82" ;
|
||||
LOCATE COMP "_enbl2" SITE "99" ;
|
||||
LOCATE COMP "select" SITE "78" ;
|
||||
LOCATE COMP "_en35" SITE "98" ;
|
||||
LOCATE COMP "spi_clk" SITE "31" ;
|
||||
LOCATE COMP "spi_mosi" SITE "49" ;
|
||||
LOCATE COMP "spi_cs" SITE "27" ;
|
||||
LOCATE COMP "_en245" SITE "30" ;
|
||||
LOCATE COMP "debugInfo[7]" SITE "25" ;
|
||||
LOCATE COMP "debugInfo[6]" SITE "24" ;
|
||||
LOCATE COMP "debugInfo[5]" SITE "17" ;
|
||||
LOCATE COMP "debugInfo[4]" SITE "16" ;
|
||||
LOCATE COMP "debugInfo[3]" SITE "15" ;
|
||||
LOCATE COMP "debugInfo[2]" SITE "14" ;
|
||||
LOCATE COMP "debugInfo[1]" SITE "13" ;
|
||||
LOCATE COMP "debugInfo[0]" SITE "12" ;
|
||||
LOCATE COMP "addr[11]" SITE "69" ;
|
||||
LOCATE COMP "addr[10]" SITE "68" ;
|
||||
LOCATE COMP "addr[9]" SITE "67" ;
|
||||
LOCATE COMP "addr[8]" SITE "66" ;
|
||||
LOCATE COMP "addr[7]" SITE "65" ;
|
||||
LOCATE COMP "addr[6]" SITE "64" ;
|
||||
LOCATE COMP "addr[5]" SITE "62" ;
|
||||
LOCATE COMP "addr[4]" SITE "60" ;
|
||||
LOCATE COMP "addr[3]" SITE "59" ;
|
||||
LOCATE COMP "addr[2]" SITE "58" ;
|
||||
LOCATE COMP "addr[1]" SITE "57" ;
|
||||
LOCATE COMP "addr[0]" SITE "54" ;
|
||||
LOCATE COMP "fclk" SITE "63" ;
|
||||
LOCATE COMP "q3" SITE "70" ;
|
||||
LOCATE COMP "rw" SITE "71" ;
|
||||
LOCATE COMP "_iostrobe" SITE "74" ;
|
||||
LOCATE COMP "_iosel" SITE "53" ;
|
||||
LOCATE COMP "_devsel" SITE "34" ;
|
||||
LOCATE COMP "_reset" SITE "75" ;
|
||||
LOCATE COMP "sense" SITE "97" ;
|
||||
LOCATE COMP "rddata" SITE "96" ;
|
||||
LOCATE COMP "spi_miso" SITE "32" ;
|
||||
SCHEMATIC END ;
|
||||
[ END DESIGN PREFS ]
|
||||
37
lattice/fpgatop/liron_fpgatop_map.hrr
Normal file
37
lattice/fpgatop/liron_fpgatop_map.hrr
Normal file
@ -0,0 +1,37 @@
|
||||
---------------------------------------------------
|
||||
Report for cell top
|
||||
Instance path: top
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 58.00 100.0
|
||||
LUT4 113.00 100.0
|
||||
IOBUF 52 100.0
|
||||
PFUREG 43 100.0
|
||||
EBR 4 100.0
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
iwm 1 92.2
|
||||
codeROM 1 0.0
|
||||
addrDecoder 1 2.9
|
||||
---------------------------------------------------
|
||||
Report for cell iwm
|
||||
Instance path: top/myIwm
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 53.50 92.2
|
||||
LUT4 102.00 90.3
|
||||
PFUREG 42 97.7
|
||||
---------------------------------------------------
|
||||
Report for cell codeROM
|
||||
Instance path: top/myROM
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EBR 4 100.0
|
||||
---------------------------------------------------
|
||||
Report for cell addrDecoder
|
||||
Instance path: top/myAddrDecoder
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 1.67 2.9
|
||||
LUT4 3.00 2.7
|
||||
PFUREG 1 2.3
|
||||
BIN
lattice/fpgatop/liron_fpgatop_map.ncd
Normal file
BIN
lattice/fpgatop/liron_fpgatop_map.ncd
Normal file
Binary file not shown.
489
lattice/fpgatop/liron_fpgatop_mrp.html
Normal file
489
lattice/fpgatop/liron_fpgatop_mrp.html
Normal file
@ -0,0 +1,489 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Mrp"></A>
|
||||
Lattice Mapping Report File for Design Module 'top'
|
||||
|
||||
|
||||
|
||||
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
liron_fpgatop.ngd -o liron_fpgatop_map.ncd -pr liron_fpgatop.prf -mp
|
||||
liron_fpgatop.mrp -lpf
|
||||
C:/Users/chamberlin/Documents/Liron/lattice/fpgatop/liron_fpgatop.lpf -lpf
|
||||
C:/Users/chamberlin/Documents/Liron/lattice/liron.lpf -c 0 -gui -msgset
|
||||
C:/Users/chamberlin/Documents/Liron/lattice/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.9.0.99.2
|
||||
Mapped on: 02/22/18 10:56:38
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 43 out of 1520 (3%)
|
||||
PFU registers: 43 out of 1280 (3%)
|
||||
PIO registers: 0 out of 240 (0%)
|
||||
Number of SLICEs: 58 out of 640 (9%)
|
||||
SLICEs as Logic/ROM: 58 out of 640 (9%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 0 out of 640 (0%)
|
||||
Number of LUT4s: 113 out of 1280 (9%)
|
||||
Number used as logic LUTs: 113
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 0
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 52 + 4(JTAG) out of 80 (70%)
|
||||
Number of block RAMs: 4 out of 7 (57%)
|
||||
Number of GSRs: 1 out of 1 (100%)
|
||||
EFB used : No
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Number of PLLs: 0 out of 1 (0%)
|
||||
Number of DQSDLLs: 0 out of 2 (0%)
|
||||
Number of CLKDIVC: 0 out of 4 (0%)
|
||||
Number of ECLKSYNCA: 0 out of 4 (0%)
|
||||
Number of ECLKBRIDGECS: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 2
|
||||
Net fclk_c: 27 loads, 27 rising, 0 falling (Driver: PIO fclk )
|
||||
Net _devsel_c: 8 loads, 0 rising, 8 falling (Driver: PIO _devsel )
|
||||
|
||||
Number of Clock Enables: 17
|
||||
Net q7: 1 loads, 1 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_1: 1 loads, 1 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_2: 1 loads, 1 LSLICEs
|
||||
Net myIwm/fclk_c_enable_14: 5 loads, 5 LSLICEs
|
||||
Net myIwm/fclk_c_enable_4: 1 loads, 1 LSLICEs
|
||||
Net myIwm/fclk_c_enable_16: 2 loads, 2 LSLICEs
|
||||
Net myIwm/fclk_c_enable_20: 3 loads, 3 LSLICEs
|
||||
Net myIwm/fclk_c_enable_26: 4 loads, 4 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_3: 1 loads, 1 LSLICEs
|
||||
Net myIwm/fclk_c_enable_30: 3 loads, 3 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_4: 1 loads, 1 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_7: 1 loads, 1 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_8: 1 loads, 1 LSLICEs
|
||||
Net myIwm/fclk_c_enable_27: 1 loads, 1 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_5: 1 loads, 1 LSLICEs
|
||||
Net myIwm/_devsel_N_40_enable_6: 1 loads, 1 LSLICEs
|
||||
Net n438_c: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 4
|
||||
Net q7: 1 loads, 1 LSLICEs
|
||||
Net myIwm/n302: 3 loads, 3 LSLICEs
|
||||
Net histrobe: 1 loads, 1 LSLICEs
|
||||
Net myIwm/n648: 2 loads, 2 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net q7: 22 loads
|
||||
Net addr_c_0: 17 loads
|
||||
Net addr_c_1: 13 loads
|
||||
Net addr_c_2: 13 loads
|
||||
Net addr_c_3: 13 loads
|
||||
Net q6: 13 loads
|
||||
Net writeBufferEmpty: 12 loads
|
||||
Net myIwm/n142: 11 loads
|
||||
Net myIwm/n1871: 11 loads
|
||||
Net myIwm/bitTimer_3: 10 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 0
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
|
||||
|
||||
No errors or warnings present.
|
||||
|
||||
|
||||
|
||||
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[7] | BIDIR | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[6] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[5] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[4] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[3] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[2] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[1] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| data[0] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| wrdata | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| phase[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| phase[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| phase[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| phase[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _wrreq | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _enbl1 | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _enbl2 | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| select | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _en35 | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| spi_clk | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| spi_mosi | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| spi_cs | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _en245 | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[1] | OUTPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| debugInfo[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[11] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[10] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[9] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[8] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| addr[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| fclk | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| q3 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| rw | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _iostrobe | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _iosel | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _devsel | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| _reset | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| sense | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| rddata | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| spi_miso | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
|
||||
|
||||
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
|
||||
|
||||
Signal _devsel_N_40 was merged into signal _devsel_c
|
||||
Signal myAddrDecoder/_iosel_N_24 was merged into signal n438_c
|
||||
Signal myIwm/n1873 was merged into signal q7
|
||||
Signal VCC_net undriven or does not drive anything - clipped.
|
||||
Signal n1904 undriven or does not drive anything - clipped.
|
||||
|
||||
Block i1779 was optimized away.
|
||||
Block myAddrDecoder/_iosel_I_0_1_lut was optimized away.
|
||||
Block myIwm/i673_1_lut_rep_31 was optimized away.
|
||||
Block i2 was optimized away.
|
||||
Block m0_lut was optimized away.
|
||||
|
||||
|
||||
|
||||
<A name="mrp_mem"></A><B><U><big>Memory Usage</big></U></B>
|
||||
|
||||
|
||||
|
||||
INFO: Design contains EBR with GSR enabled. The GSR is only applicable for
|
||||
output registers except FIFO.
|
||||
/myROM:
|
||||
EBRs: 4
|
||||
RAM SLICEs: 0
|
||||
Logic SLICEs: 0
|
||||
PFU Registers: 0
|
||||
-Contains EBR codeROM_0_0_3_0: TYPE= DP8KC, Width_A= 2, Depth_A= 4096,
|
||||
REGMODE_A= OUTREG, REGMODE_B= NOREG, RESETMODE= SYNC,
|
||||
ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL,
|
||||
GSR= ENABLED, MEM_INIT_FILE= rom-full-4k.mem, MEM_LPC_FILE=
|
||||
codeROM.lpc
|
||||
-Contains EBR codeROM_0_0_1_2: TYPE= DP8KC, Width_A= 2, Depth_A= 4096,
|
||||
REGMODE_A= OUTREG, REGMODE_B= NOREG, RESETMODE= SYNC,
|
||||
ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL,
|
||||
GSR= ENABLED, MEM_INIT_FILE= rom-full-4k.mem, MEM_LPC_FILE=
|
||||
codeROM.lpc
|
||||
-Contains EBR codeROM_0_0_0_3: TYPE= DP8KC, Width_A= 2, Depth_A= 4096,
|
||||
REGMODE_A= OUTREG, REGMODE_B= NOREG, RESETMODE= SYNC,
|
||||
ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL,
|
||||
GSR= ENABLED, MEM_INIT_FILE= rom-full-4k.mem, MEM_LPC_FILE=
|
||||
codeROM.lpc
|
||||
-Contains EBR codeROM_0_0_2_1: TYPE= DP8KC, Width_A= 2, Depth_A= 4096,
|
||||
REGMODE_A= OUTREG, REGMODE_B= NOREG, RESETMODE= SYNC,
|
||||
ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL,
|
||||
GSR= ENABLED, MEM_INIT_FILE= rom-full-4k.mem, MEM_LPC_FILE=
|
||||
codeROM.lpc
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
|
||||
---------------
|
||||
|
||||
Instance Name: myROM/codeROM_0_0_3_0
|
||||
Type: DP8KC
|
||||
Instance Name: myROM/codeROM_0_0_1_2
|
||||
Type: DP8KC
|
||||
Instance Name: myROM/codeROM_0_0_0_3
|
||||
Type: DP8KC
|
||||
Instance Name: myROM/codeROM_0_0_2_1
|
||||
Type: DP8KC
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_gsr"></A><B><U><big>GSR Usage</big></U></B>
|
||||
---------
|
||||
|
||||
GSR Component:
|
||||
The Global Set Reset (GSR) resource has been used to implement a global reset
|
||||
of the design. The reset signal used for GSR control is 'n440_c'.
|
||||
|
||||
|
||||
GSR Property:
|
||||
The design components with GSR property set to ENABLED will respond to global
|
||||
set reset while the components with GSR property set to DISABLED will
|
||||
not.
|
||||
|
||||
|
||||
Components with disabled GSR Property
|
||||
-------------------------------------
|
||||
|
||||
These components have the GSR property set to DISABLED. The components will
|
||||
not respond to the reset signal 'n440_c' via the GSR component.
|
||||
|
||||
Type and number of components of the type:
|
||||
Register = 17
|
||||
|
||||
Type and instance name of component:
|
||||
Register : myIwm/rddataSync_i0
|
||||
Register : myIwm/shifter_i0_i0
|
||||
Register : myIwm/bitTimer__i0
|
||||
Register : myIwm/rddataSync_i1
|
||||
Register : myIwm/shifter_i0_i1
|
||||
Register : myIwm/shifter_i0_i2
|
||||
Register : myIwm/shifter_i0_i3
|
||||
Register : myIwm/shifter_i0_i4
|
||||
Register : myIwm/shifter_i0_i5
|
||||
Register : myIwm/shifter_i0_i6
|
||||
Register : myIwm/shifter_i0_i7
|
||||
Register : myIwm/bitTimer__i1
|
||||
Register : myIwm/bitTimer__i2
|
||||
Register : myIwm/bitTimer__i3
|
||||
Register : myIwm/bitTimer__i4
|
||||
Register : myIwm/bitTimer__i5
|
||||
Register : myAddrDecoder/romExpansionActive_16
|
||||
|
||||
Components with synchronous local reset also reset by asynchronous GSR
|
||||
----------------------------------------------------------------------
|
||||
|
||||
These components have the GSR property set to ENABLED and the local reset
|
||||
is synchronous. The components will respond to the synchronous local reset
|
||||
and to the unrelated asynchronous reset signal 'n440_c' via the GSR
|
||||
component.
|
||||
|
||||
Type and number of components of the type:
|
||||
Register = 4
|
||||
DP8KC = 4
|
||||
|
||||
Type and instance name of component:
|
||||
Register : myIwm/_underrun_125
|
||||
Register : myIwm/clearBufferTimer_i0_i3
|
||||
Register : myIwm/clearBufferTimer_i0_i2
|
||||
|
||||
Register : myIwm/clearBufferTimer_i0_i1
|
||||
DP8KC : myROM/codeROM_0_0_3_0
|
||||
DP8KC : myROM/codeROM_0_0_1_2
|
||||
DP8KC : myROM/codeROM_0_0_0_3
|
||||
DP8KC : myROM/codeROM_0_0_2_1
|
||||
|
||||
EBR components with enabled GSR
|
||||
-------------------------------
|
||||
|
||||
These EBR components have the GSR property set to ENABLED. The components
|
||||
will respond to the asynchronous reset signal 'n440_c' via the GSR
|
||||
component.
|
||||
|
||||
Type and number of components of the type:
|
||||
DP8KC = 4
|
||||
|
||||
Type and instance name of component:
|
||||
DP8KC : myROM/codeROM_0_0_3_0
|
||||
DP8KC : myROM/codeROM_0_0_1_2
|
||||
DP8KC : myROM/codeROM_0_0_0_3
|
||||
DP8KC : myROM/codeROM_0_0_2_1
|
||||
|
||||
|
||||
|
||||
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 38 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
344
lattice/fpgatop/liron_fpgatop_pad.html
Normal file
344
lattice/fpgatop/liron_fpgatop_pad.html
Normal file
@ -0,0 +1,344 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>PAD Specification File</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Pad"></A>PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-1200HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.42
|
||||
|
||||
Thu Feb 22 10:56:42 2018
|
||||
|
||||
Pinout by Port Name:
|
||||
+--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| _devsel | 34/2 | LVCMOS33_IN | PB9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| _en245 | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| _en35 | 98/0 | LVCMOS33_OUT | PT9B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| _enbl1 | 82/0 | LVCMOS33_OUT | PT15C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| _enbl2 | 99/0 | LVCMOS33_OUT | PT9A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| _iosel | 53/1 | LVCMOS33_IN | PR9D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| _iostrobe | 74/1 | LVCMOS33_IN | PR2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| _reset | 75/1 | LVCMOS33_IN | PR2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| _wrreq | 88/0 | LVCMOS33_OUT | PT12A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| addr[0] | 54/1 | LVCMOS33_IN | PR9C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[10] | 68/1 | LVCMOS33_IN | PR4B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[11] | 69/1 | LVCMOS33_IN | PR4A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[1] | 57/1 | LVCMOS33_IN | PR9B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[2] | 58/1 | LVCMOS33_IN | PR9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[3] | 59/1 | LVCMOS33_IN | PR8D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[4] | 60/1 | LVCMOS33_IN | PR8C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[5] | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[6] | 64/1 | LVCMOS33_IN | PR5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[7] | 65/1 | LVCMOS33_IN | PR5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[8] | 66/1 | LVCMOS33_IN | PR4D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| addr[9] | 67/1 | LVCMOS33_IN | PR4C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| data[0] | 35/2 | LVCMOS33_BIDI | PB9B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[1] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[2] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[3] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[4] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[5] | 47/2 | LVCMOS33_BIDI | PB18D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[6] | 51/1 | LVCMOS33_BIDI | PR10D | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| data[7] | 52/1 | LVCMOS33_BIDI | PR10C | | | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| debugInfo[0] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[1] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[2] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[3] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[4] | 16/3 | LVCMOS33_OUT | PL8A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[5] | 17/3 | LVCMOS33_OUT | PL8B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[6] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| debugInfo[7] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| fclk | 63/1 | LVCMOS33_IN | PR5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| phase[0] | 84/0 | LVCMOS33_OUT | PT15A | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| phase[1] | 85/0 | LVCMOS33_OUT | PT12D | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| phase[2] | 86/0 | LVCMOS33_OUT | PT12C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| phase[3] | 87/0 | LVCMOS33_OUT | PT12B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| q3 | 70/1 | LVCMOS33_IN | PR3B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| rddata | 96/0 | LVCMOS33_IN | PT10B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| rw | 71/1 | LVCMOS33_IN | PR3A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| select | 78/0 | LVCMOS33_OUT | PT16C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| sense | 97/0 | LVCMOS33_IN | PT10A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| spi_clk | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| spi_cs | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| spi_miso | 32/2 | LVCMOS33_IN | PB6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| spi_mosi | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
| wrdata | 83/0 | LVCMOS33_OUT | PT15B | | | DRIVE:8mA PULL:KEEPER SLEW:SLOW |
|
||||
+--------------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
|
||||
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | unused, PULL:DOWN | | | PL2C | L_GPLLT_IN | | |
|
||||
| 2/3 | unused, PULL:DOWN | | | PL2D | L_GPLLC_IN | | |
|
||||
| 3/3 | unused, PULL:DOWN | | | PL3A | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3C | | | |
|
||||
| 8/3 | unused, PULL:DOWN | | | PL3D | | | |
|
||||
| 9/3 | unused, PULL:DOWN | | | PL4A | | | |
|
||||
| 10/3 | unused, PULL:DOWN | | | PL4B | | | |
|
||||
| 12/3 | debugInfo[0] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | debugInfo[1] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | debugInfo[2] | LOCATED | LVCMOS33_OUT | PL5C | | | |
|
||||
| 15/3 | debugInfo[3] | LOCATED | LVCMOS33_OUT | PL5D | | | |
|
||||
| 16/3 | debugInfo[4] | LOCATED | LVCMOS33_OUT | PL8A | | | |
|
||||
| 17/3 | debugInfo[5] | LOCATED | LVCMOS33_OUT | PL8B | | | |
|
||||
| 18/3 | unused, PULL:DOWN | | | PL8C | | | |
|
||||
| 19/3 | unused, PULL:DOWN | | | PL8D | | | |
|
||||
| 20/3 | unused, PULL:DOWN | | | PL9A | PCLKT3_0 | | |
|
||||
| 21/3 | unused, PULL:DOWN | | | PL9B | PCLKC3_0 | | |
|
||||
| 24/3 | debugInfo[6] | LOCATED | LVCMOS33_OUT | PL10C | | | |
|
||||
| 25/3 | debugInfo[7] | LOCATED | LVCMOS33_OUT | PL10D | | | |
|
||||
| 27/2 | spi_cs | LOCATED | LVCMOS33_OUT | PB4C | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB6A | | | |
|
||||
| 30/2 | _en245 | LOCATED | LVCMOS33_OUT | PB6B | | | |
|
||||
| 31/2 | spi_clk | LOCATED | LVCMOS33_OUT | PB6C | MCLK/CCLK | | |
|
||||
| 32/2 | spi_miso | LOCATED | LVCMOS33_IN | PB6D | SO/SPISO | | |
|
||||
| 34/2 | _devsel | LOCATED | LVCMOS33_IN | PB9A | PCLKT2_0 | | |
|
||||
| 35/2 | data[0] | LOCATED | LVCMOS33_BIDI | PB9B | PCLKC2_0 | | |
|
||||
| 36/2 | data[1] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
|
||||
| 37/2 | data[2] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
|
||||
| 38/2 | data[3] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
|
||||
| 39/2 | data[4] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
|
||||
| 40/2 | unused, PULL:DOWN | | | PB15A | | | |
|
||||
| 41/2 | unused, PULL:DOWN | | | PB15B | | | |
|
||||
| 42/2 | unused, PULL:DOWN | | | PB18A | | | |
|
||||
| 43/2 | unused, PULL:DOWN | | | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | data[5] | LOCATED | LVCMOS33_BIDI | PB18D | | | |
|
||||
| 48/2 | Prohibited/Reserved | PROHIBITED | | PB20C | SN | | |
|
||||
| 49/2 | spi_mosi | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | data[6] | LOCATED | LVCMOS33_BIDI | PR10D | DQ1 | | |
|
||||
| 52/1 | data[7] | LOCATED | LVCMOS33_BIDI | PR10C | DQ1 | | |
|
||||
| 53/1 | _iosel | LOCATED | LVCMOS33_IN | PR9D | DQ1 | | |
|
||||
| 54/1 | addr[0] | LOCATED | LVCMOS33_IN | PR9C | DQ1 | | |
|
||||
| 57/1 | addr[1] | LOCATED | LVCMOS33_IN | PR9B | DQ1 | | |
|
||||
| 58/1 | addr[2] | LOCATED | LVCMOS33_IN | PR9A | DQ1 | | |
|
||||
| 59/1 | addr[3] | LOCATED | LVCMOS33_IN | PR8D | DQ1 | | |
|
||||
| 60/1 | addr[4] | LOCATED | LVCMOS33_IN | PR8C | DQ1 | | |
|
||||
| 61/1 | Prohibited/Reserved | PROHIBITED | | PR8A | DQS1 | | |
|
||||
| 62/1 | addr[5] | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | fclk | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | addr[6] | LOCATED | LVCMOS33_IN | PR5B | DQS0N | | |
|
||||
| 65/1 | addr[7] | LOCATED | LVCMOS33_IN | PR5A | DQS0 | | |
|
||||
| 66/1 | addr[8] | LOCATED | LVCMOS33_IN | PR4D | DQ0 | | |
|
||||
| 67/1 | addr[9] | LOCATED | LVCMOS33_IN | PR4C | DQ0 | | |
|
||||
| 68/1 | addr[10] | LOCATED | LVCMOS33_IN | PR4B | DQ0 | | |
|
||||
| 69/1 | addr[11] | LOCATED | LVCMOS33_IN | PR4A | DQ0 | | |
|
||||
| 70/1 | q3 | LOCATED | LVCMOS33_IN | PR3B | DQ0 | | |
|
||||
| 71/1 | rw | LOCATED | LVCMOS33_IN | PR3A | DQ0 | | |
|
||||
| 74/1 | _iostrobe | LOCATED | LVCMOS33_IN | PR2B | DQ0 | | |
|
||||
| 75/1 | _reset | LOCATED | LVCMOS33_IN | PR2A | DQ0 | | |
|
||||
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | select | LOCATED | LVCMOS33_OUT | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | _enbl1 | LOCATED | LVCMOS33_OUT | PT15C | JTAGENB | | |
|
||||
| 83/0 | wrdata | LOCATED | LVCMOS33_OUT | PT15B | | | |
|
||||
| 84/0 | phase[0] | LOCATED | LVCMOS33_OUT | PT15A | | | |
|
||||
| 85/0 | phase[1] | LOCATED | LVCMOS33_OUT | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | phase[2] | LOCATED | LVCMOS33_OUT | PT12C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | phase[3] | LOCATED | LVCMOS33_OUT | PT12B | PCLKC0_1 | | |
|
||||
| 88/0 | _wrreq | LOCATED | LVCMOS33_OUT | PT12A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
|
||||
| 96/0 | rddata | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 97/0 | sense | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 98/0 | _en35 | LOCATED | LVCMOS33_OUT | PT9B | | | |
|
||||
| 99/0 | _enbl2 | LOCATED | LVCMOS33_OUT | PT9A | | | |
|
||||
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
|
||||
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
|
||||
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
|
||||
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
|
||||
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
|
||||
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
|
||||
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
|
||||
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
|
||||
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
|
||||
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
|
||||
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
|
||||
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
|
||||
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
|
||||
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
|
||||
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
|
||||
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
|
||||
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
|
||||
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
|
||||
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
|
||||
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
|
||||
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
|
||||
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
|
||||
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
|
||||
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
|
||||
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "_devsel" SITE "34";
|
||||
LOCATE COMP "_en245" SITE "30";
|
||||
LOCATE COMP "_en35" SITE "98";
|
||||
LOCATE COMP "_enbl1" SITE "82";
|
||||
LOCATE COMP "_enbl2" SITE "99";
|
||||
LOCATE COMP "_iosel" SITE "53";
|
||||
LOCATE COMP "_iostrobe" SITE "74";
|
||||
LOCATE COMP "_reset" SITE "75";
|
||||
LOCATE COMP "_wrreq" SITE "88";
|
||||
LOCATE COMP "addr[0]" SITE "54";
|
||||
LOCATE COMP "addr[10]" SITE "68";
|
||||
LOCATE COMP "addr[11]" SITE "69";
|
||||
LOCATE COMP "addr[1]" SITE "57";
|
||||
LOCATE COMP "addr[2]" SITE "58";
|
||||
LOCATE COMP "addr[3]" SITE "59";
|
||||
LOCATE COMP "addr[4]" SITE "60";
|
||||
LOCATE COMP "addr[5]" SITE "62";
|
||||
LOCATE COMP "addr[6]" SITE "64";
|
||||
LOCATE COMP "addr[7]" SITE "65";
|
||||
LOCATE COMP "addr[8]" SITE "66";
|
||||
LOCATE COMP "addr[9]" SITE "67";
|
||||
LOCATE COMP "data[0]" SITE "35";
|
||||
LOCATE COMP "data[1]" SITE "36";
|
||||
LOCATE COMP "data[2]" SITE "37";
|
||||
LOCATE COMP "data[3]" SITE "38";
|
||||
LOCATE COMP "data[4]" SITE "39";
|
||||
LOCATE COMP "data[5]" SITE "47";
|
||||
LOCATE COMP "data[6]" SITE "51";
|
||||
LOCATE COMP "data[7]" SITE "52";
|
||||
LOCATE COMP "debugInfo[0]" SITE "12";
|
||||
LOCATE COMP "debugInfo[1]" SITE "13";
|
||||
LOCATE COMP "debugInfo[2]" SITE "14";
|
||||
LOCATE COMP "debugInfo[3]" SITE "15";
|
||||
LOCATE COMP "debugInfo[4]" SITE "16";
|
||||
LOCATE COMP "debugInfo[5]" SITE "17";
|
||||
LOCATE COMP "debugInfo[6]" SITE "24";
|
||||
LOCATE COMP "debugInfo[7]" SITE "25";
|
||||
LOCATE COMP "fclk" SITE "63";
|
||||
LOCATE COMP "phase[0]" SITE "84";
|
||||
LOCATE COMP "phase[1]" SITE "85";
|
||||
LOCATE COMP "phase[2]" SITE "86";
|
||||
LOCATE COMP "phase[3]" SITE "87";
|
||||
LOCATE COMP "q3" SITE "70";
|
||||
LOCATE COMP "rddata" SITE "96";
|
||||
LOCATE COMP "rw" SITE "71";
|
||||
LOCATE COMP "select" SITE "78";
|
||||
LOCATE COMP "sense" SITE "97";
|
||||
LOCATE COMP "spi_clk" SITE "31";
|
||||
LOCATE COMP "spi_cs" SITE "27";
|
||||
LOCATE COMP "spi_miso" SITE "32";
|
||||
LOCATE COMP "spi_mosi" SITE "49";
|
||||
LOCATE COMP "wrdata" SITE "83";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Feb 22 10:56:42 2018
|
||||
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
295
lattice/fpgatop/liron_fpgatop_par.html
Normal file
295
lattice/fpgatop/liron_fpgatop_par.html
Normal file
@ -0,0 +1,295 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Place & Route Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Feb 22 10:56:39 2018
|
||||
|
||||
C:/lscc/diamond/3.9_x64/ispfpga\bin\nt64\par -f liron_fpgatop.p2t
|
||||
liron_fpgatop_map.ncd liron_fpgatop.dir liron_fpgatop.prf -gui -msgset
|
||||
C:/Users/chamberlin/Documents/Liron/lattice/promote.xml
|
||||
|
||||
|
||||
Preference file: liron_fpgatop.prf.
|
||||
|
||||
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 - - - - 05 Complete
|
||||
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 5 secs
|
||||
|
||||
par done!
|
||||
|
||||
Lattice Place and Route Report for Design "liron_fpgatop_map.ncd"
|
||||
Thu Feb 22 10:56:39 2018
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.9.0.99.2.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF liron_fpgatop_map.ncd liron_fpgatop.dir/5_1.ncd liron_fpgatop.prf
|
||||
Preference file: liron_fpgatop.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file liron_fpgatop_map.ncd.
|
||||
Design name: top
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
|
||||
Package Status: Final Version 1.42.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
|
||||
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
|
||||
|
||||
PIO (prelim) 52+4(JTAG)/108 52% used
|
||||
52+4(JTAG)/80 70% bonded
|
||||
|
||||
SLICE 58/640 9% used
|
||||
|
||||
GSR 1/1 100% used
|
||||
EBR 4/7 57% used
|
||||
|
||||
|
||||
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
|
||||
Number of Signals: 193
|
||||
Number of Connections: 582
|
||||
|
||||
Pin Constraint Summary:
|
||||
52 out of 52 pins locked (100% locked).
|
||||
|
||||
The following 1 signal is selected to use the primary clock routing resources:
|
||||
fclk_c (driver: fclk, clk load #: 27)
|
||||
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
_devsel_c (driver: _devsel, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
|
||||
Signal n440_c is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
.........
|
||||
Finished Placer Phase 0. REAL time: 2 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 43211.
|
||||
Finished Placer Phase 1. REAL time: 3 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 43211
|
||||
Finished Placer Phase 2. REAL time: 3 secs
|
||||
|
||||
|
||||
|
||||
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 2 out of 8 (25%)
|
||||
PLL : 0 out of 1 (0%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Quadrants All (TL, TR, BL, BR) - Global Clocks:
|
||||
PRIMARY "fclk_c" from comp "fclk" on CLK_PIN site "63 (PR5C)", clk load = 27
|
||||
SECONDARY "_devsel_c" from comp "_devsel" on CLK_PIN site "34 (PB9A)", clk load = 8, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 1 out of 8 (12%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
Edge Clocks:
|
||||
No edge clock selected.
|
||||
|
||||
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
52 + 4(JTAG) out of 108 (51.9%) PIO sites used.
|
||||
52 + 4(JTAG) out of 80 (70.0%) bonded PIO sites used.
|
||||
Number of PIO comps: 52; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 12 / 19 ( 63%) | 3.3V | - |
|
||||
| 1 | 20 / 21 ( 95%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 3 | 8 / 20 ( 40%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 2 secs
|
||||
|
||||
Dumping design to file liron_fpgatop.dir/5_1.ncd.
|
||||
|
||||
|
||||
-----------------------------------------------------------------
|
||||
INFO - par: ASE feature is off due to non timing-driven settings.
|
||||
-----------------------------------------------------------------
|
||||
|
||||
0 connections routed; 582 unrouted.
|
||||
Starting router resource preassignment
|
||||
|
||||
Completed router resource preassignment. Real time: 4 secs
|
||||
|
||||
Start NBR router at 10:56:43 02/22/18
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 10:56:43 02/22/18
|
||||
|
||||
Start NBR section for initial routing at 10:56:43 02/22/18
|
||||
Level 4, iteration 1
|
||||
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 10:56:43 02/22/18
|
||||
Level 4, iteration 1
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
Level 4, iteration 2
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
|
||||
Start NBR section for re-routing at 10:56:43 02/22/18
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 4 secs
|
||||
|
||||
Start NBR section for post-routing at 10:56:43 02/22/18
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : <n/a>
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 3 secs
|
||||
Total REAL time: 4 secs
|
||||
Completely routed.
|
||||
End of route. 582 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file liron_fpgatop.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a>
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a>
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 3 secs
|
||||
Total REAL time to completion: 5 secs
|
||||
|
||||
par done!
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
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Reference in New Issue
Block a user