268 lines
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268 lines
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<HEAD><TITLE>Synthesis and Ngdbuild Report</TITLE>
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<PRE><A name="Syn"></A><B><U><big>Synthesis and Ngdbuild Report</big></U></B>
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synthesis: version Diamond (64-bit) 3.9.0.99.2
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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Thu Feb 22 10:56:36 2018
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Command Line: synthesis -f liron_fpgatop_lattice.synproj -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml
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Synthesis options:
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The -a option is MachXO2.
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The -s option is 4.
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The -t option is TQFP100.
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The -d option is LCMXO2-1200HC.
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Using package TQFP100.
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Using performance grade 4.
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##########################################################
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### Lattice Family : MachXO2
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### Device : LCMXO2-1200HC
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### Package : TQFP100
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### Speed : 4
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##########################################################
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INFO - synthesis: User-Selected Strategy Settings
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Optimization goal = Balanced
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Top-level module name = top.
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Target frequency = 1.000000 MHz.
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Maximum fanout = 1000.
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Timing path count = 3
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BRAM utilization = 100.000000 %
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DSP usage = true
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DSP utilization = 100.000000 %
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fsm_encoding_style = auto
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resolve_mixed_drivers = 0
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fix_gated_clocks = 1
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Mux style = Auto
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Use Carry Chain = true
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carry_chain_length = 0
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Loop Limit = 1950.
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Use IO Insertion = TRUE
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Use IO Reg = AUTO
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Resource Sharing = TRUE
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Propagate Constants = TRUE
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Remove Duplicate Registers = TRUE
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force_gsr = auto
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ROM style = auto
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RAM style = auto
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The -comp option is FALSE.
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The -syn option is FALSE.
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-p C:/Users/chamberlin/Documents/Liron/lattice (searchpath added)
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-p C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data (searchpath added)
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-p C:/Users/chamberlin/Documents/Liron/lattice/fpgatop (searchpath added)
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-p C:/Users/chamberlin/Documents/Liron/lattice (searchpath added)
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Verilog design file = C:/Users/chamberlin/Documents/Liron/lattice/top.v
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Verilog design file = C:/Users/chamberlin/Documents/Liron/lattice/addrDecoder.v
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Verilog design file = C:/Users/chamberlin/Documents/Liron/lattice/iwm.v
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Verilog design file = C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v
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NGD file = liron_fpgatop.ngd
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-sdc option: SDC file input not used.
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-lpf option: Output file option is ON.
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Hardtimer checking is enabled (default). The -dt option is not used.
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The -r option is OFF. [ Remove LOC Properties is OFF. ]
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Technology check ok...
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Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
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Compile design.
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Compile Design Begin
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Analyzing Verilog file c:/users/chamberlin/documents/liron/lattice/top.v. VERI-1482
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Analyzing Verilog file c:/users/chamberlin/documents/liron/lattice/addrdecoder.v. VERI-1482
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Analyzing Verilog file c:/users/chamberlin/documents/liron/lattice/iwm.v. VERI-1482
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Analyzing Verilog file c:/users/chamberlin/documents/liron/lattice/coderom.v. VERI-1482
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Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
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Top module name (Verilog): top
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INFO - synthesis: c:/users/chamberlin/documents/liron/lattice/top.v(2): compiling module top. VERI-1018
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INFO - synthesis: c:/users/chamberlin/documents/liron/lattice/addrdecoder.v(2): compiling module addrDecoder. VERI-1018
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INFO - synthesis: c:/users/chamberlin/documents/liron/lattice/iwm.v(2): compiling module iwm. VERI-1018
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INFO - synthesis: c:/users/chamberlin/documents/liron/lattice/coderom.v(8): compiling module codeROM. VERI-1018
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INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_1. VERI-1018
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INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_2. VERI-1018
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INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_3. VERI-1018
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INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120): compiling module VHI. VERI-1018
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INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124): compiling module VLO. VERI-1018
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INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_4. VERI-1018
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'...
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Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
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Package Status: Final Version 1.42.
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Top-level module name = top.
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######## Converting I/O port _enbl2 to output.
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######## Converting I/O port select to output.
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######## Converting I/O port _en35 to output.
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######## Missing driver on net spi_clk. Patching with GND.
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######## Missing driver on net spi_mosi. Patching with GND.
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######## Missing driver on net spi_cs. Patching with GND.
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GSR instance connected to net n440_c.
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Applying 1.000000 MHz constraint to all clocks
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WARNING - synthesis: No user .sdc file.
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Results of NGD DRC are available in top_drc.log.
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'...
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All blocks are expanded and NGD expansion is successful.
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Writing NGD file liron_fpgatop.ngd.
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################### Begin Area Report (top)######################
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Number of register bits => 43 of 1520 (2 % )
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BB => 8
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DP8KC => 4
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FD1P3AX => 29
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FD1P3IX => 10
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FD1P3JX => 1
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FD1S3AX => 2
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FD1S3AY => 1
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GSR => 1
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IB => 22
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INV => 1
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LUT4 => 115
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OB => 19
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OBZ => 3
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PFUMX => 1
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################### End Area Report ##################
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################### Begin BlackBox Report ######################
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TSALL => 1
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################### End BlackBox Report ##################
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################### Begin Clock Report ######################
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Clock Nets
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Number of Clocks: 2
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Net : fclk_c, loads : 39
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Net : _devsel_c, loads : 6
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Clock Enable Nets
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Number of Clock Enables: 17
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Top 10 highest fanout Clock Enables:
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Net : myIwm/q7, loads : 21
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Net : myIwm/fclk_c_enable_14, loads : 8
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Net : myIwm/fclk_c_enable_26, loads : 7
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Net : myIwm/fclk_c_enable_20, loads : 6
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Net : myIwm/fclk_c_enable_30, loads : 4
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Net : myIwm/fclk_c_enable_16, loads : 3
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Net : myIwm/_devsel_N_40_enable_4, loads : 1
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Net : myIwm/fclk_c_enable_27, loads : 1
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Net : myIwm/_devsel_N_40_enable_5, loads : 1
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Net : myIwm/_devsel_N_40_enable_1, loads : 1
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Highest fanout non-clock nets
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Top 10 highest fanout non-clock nets:
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Net : myIwm/q7, loads : 21
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Net : addr_c_0, loads : 17
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Net : addr_c_3, loads : 13
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Net : addr_c_2, loads : 13
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Net : addr_c_1, loads : 13
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Net : myIwm/q6, loads : 12
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Net : myIwm/writeBufferEmpty, loads : 11
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Net : myIwm/n142, loads : 11
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Net : myIwm/n1871, loads : 11
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Net : myIwm/bitTimer_3, loads : 10
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################### End Clock Report ##################
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<A name="lse_trs"></A><B><U><big>Timing Report Summary</big></U></B>
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--------------
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--------------------------------------------------------------------------------
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Constraint | Constraint| Actual|Levels
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--------------------------------------------------------------------------------
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create_clock -period 1000.000000 -name | | |
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clk1 [get_nets _devsel_c] | -| -| 0
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create_clock -period 1000.000000 -name | | |
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clk0 [get_nets fclk_c] | 1.000 MHz| 99.890 MHz| 5
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--------------------------------------------------------------------------------
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All constraints were met.
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Peak Memory Usage: 53.680 MB
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--------------------------------------------------------------
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Elapsed CPU time for LSE flow : 0.920 secs
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--------------------------------------------------------------
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