8 Commits

Author	SHA1	Message	Date
Steven Hugg	7441196b2e	no more BOM on download files	2018-12-08 10:15:02 -05:00
Steven Hugg	bf2250310b	moved fpga examples to https://github.com/sehugg/fpga-examples; new framebuffer.v	2018-11-12 14:13:17 -05:00
Steven Hugg	4a82d341bc	make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes	2018-08-14 00:05:02 -04:00
Steven Hugg	2fce80bc9d	fixed asmlines in inline asm; reset h/vpaddle on vsync; fixed framebuffer.v	2018-07-17 22:17:01 -05:00
Steven Hugg	b2beb2670c	more Verilog code; inline asm for depends; fixed tank	2018-02-25 10:34:27 -06:00
Steven Hugg	20ddb8a11f	moved around ALU ops, 16-bit cpu, reg/wire	2018-02-21 11:03:38 -06:00
Steven Hugg	f6d320a05b	new inline verilog assembler	2018-02-18 11:14:04 -06:00
Steven Hugg	1790ca1747	updated verilog presets and test makefile	2018-02-16 23:33:29 -06:00