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12 lines
201 B
Verilog
12 lines
201 B
Verilog
module t(y);
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output [3:0] y;
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// bug775
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// verilator lint_off WIDTH
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assign y = ((0/0) ? 1 : 2) % 0;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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