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https://github.com/hoglet67/AtomBusMon.git
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Altera: Use Altera WatchEvents from BeebFPGA (which has fwft set)
Change-Id: I9ad3d0c09099b83c115a405f7837b117581fbeef
This commit is contained in:
David Banks
155
src/altera/WatchEvents_CycloneIV.vhd
Normal file
155
src/altera/WatchEvents_CycloneIV.vhd
Normal file
@@ -0,0 +1,155 @@
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY WatchEvents IS
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PORT
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(
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clk : IN STD_LOGIC;
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srst : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC
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);
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END WatchEvents;
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ARCHITECTURE SYN OF watchevents IS
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SIGNAL sub_wire0 : STD_LOGIC ;
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SIGNAL sub_wire1 : STD_LOGIC ;
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SIGNAL sub_wire2 : STD_LOGIC_VECTOR (71 DOWNTO 0);
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COMPONENT scfifo
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GENERIC (
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add_ram_output_register : STRING;
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intended_device_family : STRING;
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lpm_numwords : NATURAL;
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lpm_showahead : STRING;
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lpm_type : STRING;
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lpm_width : NATURAL;
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lpm_widthu : NATURAL;
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overflow_checking : STRING;
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underflow_checking : STRING;
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use_eab : STRING
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);
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PORT (
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clock : IN STD_LOGIC ;
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data : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
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rdreq : IN STD_LOGIC ;
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sclr : IN STD_LOGIC ;
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empty : OUT STD_LOGIC ;
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full : OUT STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (71 DOWNTO 0);
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wrreq : IN STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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empty <= sub_wire0;
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full <= sub_wire1;
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dout <= sub_wire2(71 DOWNTO 0);
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scfifo_component : scfifo
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GENERIC MAP (
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add_ram_output_register => "OFF",
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intended_device_family => "Cyclone IV",
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lpm_numwords => 512,
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lpm_showahead => "ON",
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lpm_type => "scfifo",
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lpm_width => 72,
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lpm_widthu => 9,
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overflow_checking => "ON",
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underflow_checking => "ON",
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use_eab => "ON"
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)
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PORT MAP (
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clock => clk,
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data => din,
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rdreq => rd_en,
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sclr => srst,
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wrreq => wr_en,
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empty => sub_wire0,
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full => sub_wire1,
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q => sub_wire2
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);
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
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-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
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-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
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-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
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-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
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-- Retrieval info: PRIVATE: Clock NUMERIC "0"
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-- Retrieval info: PRIVATE: Depth NUMERIC "512"
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-- Retrieval info: PRIVATE: Empty NUMERIC "1"
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-- Retrieval info: PRIVATE: Full NUMERIC "1"
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV"
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-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
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-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
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-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
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-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
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-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
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-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
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-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
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-- Retrieval info: PRIVATE: Width NUMERIC "72"
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-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
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-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
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-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
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-- Retrieval info: PRIVATE: output_width NUMERIC "72"
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-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
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-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
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-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
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-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
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-- Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
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-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
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-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
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-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV"
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-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
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-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
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-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "72"
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-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
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-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
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-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
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-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
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-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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-- Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
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-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
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-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
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-- Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
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-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
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-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
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-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
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-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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-- Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
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-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
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-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
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-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
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-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
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-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
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-- Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.bsf FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: altera_mf
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@@ -1,81 +0,0 @@
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY WatchEvents IS
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PORT
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(
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clk : IN STD_LOGIC ;
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din : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
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rd_en : IN STD_LOGIC ;
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wr_en : IN STD_LOGIC ;
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srst : IN STD_LOGIC ;
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empty : OUT STD_LOGIC ;
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full : OUT STD_LOGIC ;
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dout : OUT STD_LOGIC_VECTOR (71 DOWNTO 0);
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usedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
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);
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END WatchEvents;
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ARCHITECTURE SYN OF watchevents IS
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SIGNAL sub_wire0 : STD_LOGIC ;
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SIGNAL sub_wire1 : STD_LOGIC ;
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SIGNAL sub_wire2 : STD_LOGIC_VECTOR (71 DOWNTO 0);
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SIGNAL sub_wire3 : STD_LOGIC_VECTOR (8 DOWNTO 0);
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COMPONENT scfifo
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GENERIC (
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add_ram_output_register : STRING;
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intended_device_family : STRING;
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lpm_numwords : NATURAL;
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lpm_showahead : STRING;
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lpm_type : STRING;
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lpm_width : NATURAL;
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lpm_widthu : NATURAL;
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overflow_checking : STRING;
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underflow_checking : STRING;
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use_eab : STRING
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);
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PORT (
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clock : IN STD_LOGIC ;
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data : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
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rdreq : IN STD_LOGIC ;
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wrreq : IN STD_LOGIC ;
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empty : OUT STD_LOGIC ;
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full : OUT STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (71 DOWNTO 0);
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usedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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scfifo_component : scfifo
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GENERIC MAP (
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add_ram_output_register => "OFF",
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intended_device_family => "Cyclone IV E",
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lpm_numwords => 512,
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lpm_showahead => "OFF",
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lpm_type => "scfifo",
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lpm_width => 72,
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lpm_widthu => 9,
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overflow_checking => "ON",
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underflow_checking => "ON",
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use_eab => "ON"
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)
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PORT MAP (
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clock => clk,
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data => din,
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rdreq => rd_en,
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wrreq => wr_en,
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empty => empty,
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full => full,
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q => dout,
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usedw => open
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);
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END SYN;
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@@ -91,13 +91,13 @@ set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/ExtIRQ_Controller.vhd
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set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/RAMDataReg.vhd
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set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/ResetGenerator.vhd
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set_global_assignment -name VHDL_FILE ../../../src/BusMonCore.vhd
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set_global_assignment -name VHDL_FILE ../../../src/DCM/DCM0Altera.vhd
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set_global_assignment -name VHDL_FILE ../../../src/altera/DCM0.vhd
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set_global_assignment -name VHDL_FILE ../../../src/altera/WatchEvents_CycloneIV.vhd
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set_global_assignment -name VHDL_FILE ../../../src/MC6809CpuMonCycloneIV.vhd
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set_global_assignment -name VHDL_FILE ../../../src/MC6809CpuMon.vhd
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set_global_assignment -name VHDL_FILE ../../../src/oho_dy1/Oho_Dy1.vhd
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set_global_assignment -name VHDL_FILE ../../../src/oho_dy1/OhoPack.vhd
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set_global_assignment -name VHDL_FILE ../../../src/SYS09/cpu09l.vhd
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set_global_assignment -name VHDL_FILE WatchEvents.vhd
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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@@ -112,6 +112,7 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_location_assignment PIN_24 -to clock
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