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Altera: rename to level design to MC6809CpuMonEP4CE6E22C

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Change-Id: Iaa258d08734df98dcd1303938862d698bcde363a
This commit is contained in:
David Banks
2025-11-26 09:18:17 +00:00
parent 9cd63d78aa
commit b617b85c75
2 changed files with 9 additions and 9 deletions
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14
src/MC6809CpuMonCycloneIV.vhd → src/MC6809CpuMonEP4CE6E22C.vhd
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@@ -7,12 +7,12 @@
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MC6809CpuMonCycloneIV.vhd
-- / / Filename : MC6809CpuMonEP4CE6E22C.vhd
-- /___/ /\ Timestamp : 24/10/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MC6809CpuMonALS
--Design Name: MC6809CpuMonEP4CE6E22C
--Device: XC6SLX9
library ieee;
@@ -20,10 +20,10 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC6809CpuMonCycloneIV is
entity MC6809CpuMonEP4CE6E22C is
generic (
num_comparators : integer := 8; -- default value correct for ALS
avr_prog_mem_size : integer := 1024 * 9 -- default value correct for ALS
num_comparators : integer := 8; -- default value correct for EP4CE6E22C
avr_prog_mem_size : integer := 1024 * 9 -- default value correct for EP4CE6E22C
);
port (
clock : in std_logic;
@@ -77,9 +77,9 @@ entity MC6809CpuMonCycloneIV is
led3 : out std_logic
);
end MC6809CpuMonCycloneIV;
end MC6809CpuMonEP4CE6E22C;
architecture behavioral of MC6809CpuMonCycloneIV is
architecture behavioral of MC6809CpuMonEP4CE6E22C is
signal R_W_n_int : std_logic;

4
target/ep4ce6e22c/ice6809/ice6809.qsf
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@@ -39,7 +39,7 @@
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY MC6809CpuMonCycloneIV
set_global_assignment -name TOP_LEVEL_ENTITY MC6809CpuMonEP4CE6E22C
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:44:09 NOVEMBER 25, 2025"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
@@ -93,7 +93,7 @@ set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/ResetGenerator.vhd
set_global_assignment -name VHDL_FILE ../../../src/BusMonCore.vhd
set_global_assignment -name VHDL_FILE ../../../src/altera/DCM0.vhd
set_global_assignment -name VHDL_FILE ../../../src/altera/WatchEvents_CycloneIV.vhd
set_global_assignment -name VHDL_FILE ../../../src/MC6809CpuMonCycloneIV.vhd
set_global_assignment -name VHDL_FILE ../../../src/MC6809CpuMonEP4CE6E22C.vhd
set_global_assignment -name VHDL_FILE ../../../src/MC6809CpuMon.vhd
set_global_assignment -name VHDL_FILE ../../../src/oho_dy1/Oho_Dy1.vhd
set_global_assignment -name VHDL_FILE ../../../src/oho_dy1/OhoPack.vhd