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Switched to Timing-Driven Packing, fixed a bug with instr wait states that meant single stepping executed RST 38 because FF was read off databus; increased comparators to 8; incremented version to 0.43. Works with 100pF capgit add -u!

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Change-Id: Ie6c8c8fc610599516eb1baf957d001079713e462
This commit is contained in:
David Banks
2015-06-27 18:40:12 +01:00
parent 401af8253a
commit e4e0f864df
7 changed files with 64 additions and 30 deletions
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Z80CpuMon.xise
+1 -1
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@@ -440,7 +440,7 @@
<property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
firmware/AtomBusMon.c
+24 -9
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@@ -241,10 +241,17 @@ unsigned char dopaddr[256] =
#define OFFSET_BW_CNTH 14
// Processor registers
#if (CPU == Z80)
#define OFFSET_REG_F 16
#define OFFSET_REG_A 17
#define OFFSET_REG_Fp 18
#define OFFSET_REG_Ap 19
#else
#define OFFSET_REG_A 16
#define OFFSET_REG_X 17
#define OFFSET_REG_Y 18
#define OFFSET_REG_P 19
#endif
#define OFFSET_REG_SPL 20
#define OFFSET_REG_SPH 21
#define OFFSET_REG_PCL 22
@@ -337,7 +344,7 @@ char *triggerStrings[NUM_TRIGGERS] = {
};
#define VERSION "0.42"
#define VERSION "0.43"
#ifdef CPUEMBEDDED
#define NUM_CMDS 22
@@ -345,11 +352,7 @@ char *triggerStrings[NUM_TRIGGERS] = {
#define NUM_CMDS 14
#endif
#if (CPU == Z80)
#define MAXBKPTS 1
#else
#define MAXBKPTS 8
#endif
int numbkpts = 0;
@@ -358,7 +361,11 @@ long instructions = 1;
unsigned int memAddr = 0;
#if (CPU == Z80)
char statusString[8] = "SZIH-P-C";
#else
char statusString[8] = "NV-BDIZC";
#endif
unsigned int breakpoints[MAXBKPTS] = {
#if (CPU != Z80)
@@ -830,16 +837,24 @@ void doCmdReset(char *params) {
#ifdef CPUEMBEDDED
void doCmdRegs(char *params) {
int i;
log0("CPU Registers:\n");
log0(" A=%02X X=%02X Y=%02X SP=%04X PC=%04X\n",
#if (CPU == Z80)
unsigned int p = hwRead16(OFFSET_REG_F);
log0("Z80 Registers:\n AF=%04X AF'=%04X SP=%04X PC=%04X\n",
p,
hwRead16(OFFSET_REG_Fp),
hwRead16(OFFSET_REG_SPL),
hwRead16(OFFSET_REG_PCL));
#else
unsigned int p = hwRead8(OFFSET_REG_P);
log0("6502 Registers:\n A=%02X X=%02X Y=%02X SP=%04X PC=%04X\n",
hwRead8(OFFSET_REG_A),
hwRead8(OFFSET_REG_X),
hwRead8(OFFSET_REG_Y),
hwRead16(OFFSET_REG_SPL),
hwRead16(OFFSET_REG_PCL));
unsigned int p = hwRead8(OFFSET_REG_P);
#endif
char *sp = statusString;
log0(" P=%02X ", p);
log0(" Status: ");
for (i = 0; i <= 7; i++) {
log0("%c", ((p & 128) ? (*sp) : '-'));
p <<= 1;
src/T80/T80.vhd
+5 -3
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@@ -247,11 +247,12 @@ architecture rtl of T80 is
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
signal RegFileData : std_logic_vector(127 downto 0);
begin
Regs(31 downto 0) <= (others => '0');
Regs(31 downto 0) <= Ap & Fp & ACC & F;
-- Regs(31 downto 0) <= RegFileData(31 downto 0);
Regs(47 downto 32) <= std_logic_vector(SP);
Regs(63 downto 48) <= std_logic_vector(PC);
@@ -866,7 +867,8 @@ begin
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
DOCL => RegBusC(7 downto 0),
RegFileData => RegFileData);
---------------------------------------------------------------------------
--
src/T80/T80_Pack.vhd
+2 -1
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@@ -125,7 +125,8 @@ package T80_Pack is
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
DOCL : out std_logic_vector(7 downto 0);
RegFileData : out std_logic_vector(127 downto 0)
);
end component;
src/T80/T80_Reg.vhd
+22 -3
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@@ -78,8 +78,9 @@ entity T80_Reg is
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
DOCL : out std_logic_vector(7 downto 0);
RegFileData : out std_logic_vector(127 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
@@ -89,7 +90,25 @@ architecture rtl of T80_Reg is
signal RegsL : Register_Image(0 to 7);
begin
RegFileData( 7 downto 0) <= RegsL(0);
RegFileData( 15 downto 8) <= RegsL(1);
RegFileData( 23 downto 16) <= RegsL(2);
RegFileData( 31 downto 24) <= RegsL(3);
RegFileData( 39 downto 32) <= RegsL(4);
RegFileData( 47 downto 40) <= RegsL(5);
RegFileData( 55 downto 48) <= RegsL(6);
RegFileData( 63 downto 56) <= RegsL(7);
RegFileData( 71 downto 64) <= RegsH(0);
RegFileData( 79 downto 72) <= RegsH(1);
RegFileData( 87 downto 80) <= RegsH(2);
RegFileData( 95 downto 88) <= RegsH(3);
RegFileData(103 downto 96) <= RegsH(4);
RegFileData(111 downto 104) <= RegsH(5);
RegFileData(119 downto 112) <= RegsH(6);
RegFileData(127 downto 120) <= RegsH(7);
process (Clk)
begin
if Clk'event and Clk = '1' then
src/T80/T80a.vhd
+1 -5
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@@ -80,9 +80,7 @@ entity T80a is
port(
-- Additions
TS : out std_logic_vector(2 downto 0);
WAIT_s_out : out std_logic;
Regs : out std_logic_vector(63 downto 0);
Write_out : out std_logic;
-- Original Signals
RESET_n : in std_logic;
CLK_n : in std_logic;
@@ -222,7 +220,7 @@ begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
if MCycle = "001" and TState = "010" and Wait_s = '1' then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
@@ -281,6 +279,4 @@ begin
end process;
TS <= TState;
WAIT_s_out <= WAIT_s;
Write_out <= Write;
end;
src/Z80CpuMon.vhd
+9 -8
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@@ -89,7 +89,6 @@ signal MREQ_n_int : std_logic;
signal IORQ_n_int : std_logic;
signal M1_n_int : std_logic;
signal WAIT_n_int : std_logic;
signal WAIT_s : std_logic;
signal TState : std_logic_vector(2 downto 0);
signal SS_Single : std_logic;
signal SS_Step : std_logic;
@@ -119,7 +118,7 @@ begin
mon : entity work.BusMonCore
generic map (
num_comparators => 1
num_comparators => 8
)
port map (
clock49 => clock49,
@@ -160,9 +159,7 @@ begin
GenT80Core: if UseT80Core generate
inst_t80: entity work.T80a port map (
TS => TState,
WAIT_s_out => WAIT_s,
Regs => Regs,
Write_out => Write,
RESET_n => RESET_n_int,
CLK_n => cpu_clk,
WAIT_n => WAIT_n_int,
@@ -206,10 +203,14 @@ begin
end process;
-- Make the monitoring decision in the middle of T2, but only if WAIT_n is '1'
Sync0 <= (WAIT_n_int and (not Write) and (not MREQ_n_int) and (not M1_n_int)) when TState = "010" else '0';
Read_n0 <= not (WAIT_n_int and (not Write) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
Write_n0 <= not (WAIT_n_int and ( Write) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
-- Make the monitoring decision in the middle of T2, but only if WAIT_n is '1'
Sync0 <= (WAIT_n_int and (not RD_n_int) and (not MREQ_n_int) and (not M1_n_int)) when TState = "010" else '0';
Read_n0 <= not (WAIT_n_int and (not RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
Write_n0 <= not (WAIT_n_int and (not WR_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
-- These are useful for debugging IO Requests:
-- Read_n0 <= not (WAIT_n_int and (not RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "010" else '1';
-- Write_n0 <= not ( ( RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "011" else '1';
-- Hold the monitoring decision so it is valid on the rising edge of the clock
-- For instruction fetches and writes, the monitor sees these at the start of T3