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Known Issues and Future work

David Banks edited this page 2019-10-23 13:18:09 +01:00

Table of Contents

• Known Issues
• Future Work

Known Issues

• The GODIL contains 1K5 pull-ups to +5V on all pins. This can raise the logic zero threshold of inputs driving the ICE module, and which can result in reduced noise margin. See the ICE-T80 for more information on the type of problem this can cause on real systems. The XC6SLX9 based implementation with the active level shifters overcomes this issue.

Future Work

• Make cycle counter a 32 bit counter, and have some way to set a non-default clock speed, and maybe toggle between cycles and seconds.

• FIFO overrun detection.

Introduction and Overview

GODIL Hardware (now obsolete)

• Purchasing the GODIL
• Programming-Prerequisites
• ICE-T65
• ICE-T80
• ICE-6809

XC6SLX9 Mini Board (eepizza)

• Xilinx-XC6SLX9-Mini-Board
• 6502/65C02 CPU Adapter
• Z80 CPU Adapter
• 6809E CPU Adapter

Tutorials:

• Programming the FPGA Board in iMPACT
• Programming the FPGA Board using OpenOCD on a Pi

User Manual

• Introduction
• Features
• Getting Started
• Command Reference

Hardware design notes

• Block Diagram

Software design notes

• Firmware Overview
• Toolchain
• Compiling firmware
• Building on Windows 7

Links

Known Issues and Future work

Credits and Acknowledgements