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Starts writing and referring to colour RAM for colours.
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0d8af010b6
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@ -442,14 +442,16 @@ void TMS9918::run_for(const HalfCycles cycles) {
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const int column = (pixel_location + c) >> 3;
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const int column = (pixel_location + c) >> 3;
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const int shift = 4 + (((pixel_location + c) & 7) ^ reverses[(master_system_.names[column].flags&2) >> 1]);
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const int shift = 4 + (((pixel_location + c) & 7) ^ reverses[(master_system_.names[column].flags&2) >> 1]);
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int value =
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int value =
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((
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(
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((master_system_.tile_graphics[column][0] << shift) & 0x800) |
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(
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((master_system_.tile_graphics[column][1] << (shift - 1)) & 0x400) |
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((master_system_.tile_graphics[column][3] << shift) & 0x800) |
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((master_system_.tile_graphics[column][2] << (shift - 2)) & 0x200) |
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((master_system_.tile_graphics[column][2] << (shift - 1)) & 0x400) |
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((master_system_.tile_graphics[column][3] << (shift - 3)) & 0x100)
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((master_system_.tile_graphics[column][1] << (shift - 2)) & 0x200) |
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) >> 8) << 4;
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((master_system_.tile_graphics[column][0] << (shift - 3)) & 0x100)
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) >> 8
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) | ((master_system_.names[column].flags&0x08) << 1);
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pixel_target_[c] = static_cast<uint32_t>((value << 24) | (value << 16) | (value << 8) | value);
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pixel_target_[c] = master_system_.colour_ram[value];
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}
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}
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pixel_target_ += pixels_left;
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pixel_target_ += pixels_left;
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}
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}
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@ -684,9 +686,18 @@ void TMS9918::set_register(int address, uint8_t value) {
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if(!(address & 1)) {
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if(!(address & 1)) {
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write_phase_ = false;
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write_phase_ = false;
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if(master_system_.cram_is_selected) {
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master_system_.colour_ram[ram_pointer_ & 0x1f] = palette_pack(
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static_cast<uint8_t>((value & 0x03) << 6),
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static_cast<uint8_t>((value & 0x0c) << 4),
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static_cast<uint8_t>((value & 0x30) << 2));
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++ram_pointer_;
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// TODO: insert a CRAM dot here.
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} else {
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// Enqueue the write to occur at the next available slot.
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// Enqueue the write to occur at the next available slot.
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read_ahead_buffer_ = value;
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read_ahead_buffer_ = value;
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queued_access_ = MemoryAccess::Write;
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queued_access_ = MemoryAccess::Write;
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}
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return;
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return;
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}
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}
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@ -707,7 +718,9 @@ void TMS9918::set_register(int address, uint8_t value) {
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break;
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break;
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case TI::TMS::SMSVDP:
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case TI::TMS::SMSVDP:
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if(value & 0x40) {
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if(value & 0x40) {
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// TODO: CRAM.
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ram_pointer_ = static_cast<uint16_t>(low_write_ | (value << 8));
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master_system_.cram_is_selected = true;
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queued_access_ = MemoryAccess::None;
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return;
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return;
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}
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}
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value &= 0xf;
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value &= 0xf;
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@ -787,6 +800,7 @@ void TMS9918::set_register(int address, uint8_t value) {
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// Officially a 'read' set, so perform lookahead.
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// Officially a 'read' set, so perform lookahead.
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queued_access_ = MemoryAccess::Read;
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queued_access_ = MemoryAccess::Read;
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}
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}
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master_system_.cram_is_selected = false;
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}
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}
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}
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}
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@ -118,7 +118,7 @@ class Base {
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bool shift_sprites_8px_left = false;
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bool shift_sprites_8px_left = false;
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bool mode4_enable = false;
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bool mode4_enable = false;
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uint8_t colour_ram[32];
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uint32_t colour_ram[32];
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struct {
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struct {
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size_t offset;
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size_t offset;
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@ -129,6 +129,7 @@ class Base {
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uint8_t horizontal_scroll = 0;
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uint8_t horizontal_scroll = 0;
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uint8_t vertical_scroll = 0;
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uint8_t vertical_scroll = 0;
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bool cram_is_selected = false;
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} master_system_;
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} master_system_;
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enum class ScreenMode {
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enum class ScreenMode {
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