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Switches CIA A/B byte connections; applies reset to memory map.
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@ -70,6 +70,7 @@ class ConcreteMachine:
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// Check for assertion of reset.
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if(cycle.operation & Microcycle::Reset) {
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memory_.reset();
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LOG("Unhandled Reset; PC is around " << PADHEX(8) << mc68000_.get_state().program_counter);
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}
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@ -104,12 +105,12 @@ class ConcreteMachine:
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if(cycle.operation & Microcycle::Read) {
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uint16_t result = 0xffff;
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if(!(address & 0x1000)) result &= 0x00ff | (cia_a_.read(reg) << 8);
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if(!(address & 0x2000)) result &= 0xff00 | (cia_b_.read(reg) << 0);
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if(!(address & 0x1000)) result &= 0xff00 | (cia_a_.read(reg) << 0);
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if(!(address & 0x2000)) result &= 0x00ff | (cia_b_.read(reg) << 8);
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cycle.set_value16(result);
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} else {
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if(!(address & 0x1000)) cia_a_.write(reg, cycle.value8_high());
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if(!(address & 0x2000)) cia_b_.write(reg, cycle.value8_low());
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if(!(address & 0x1000)) cia_a_.write(reg, cycle.value8_low());
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if(!(address & 0x2000)) cia_b_.write(reg, cycle.value8_high());
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}
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} else if(address >= 0xdf'f000 && address <= 0xdf'f1be) {
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#define RW(address) (address & 0xffe) | ((cycle.operation & Microcycle::Read) << 7)
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@ -256,6 +257,10 @@ class ConcreteMachine:
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// f8'0000 — : 256kb Kickstart if 2.04 or higher.
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// fc'0000 – : 256kb Kickstart otherwise.
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set_region(0xfc'0000, 0x1'00'0000, kickstart_.data(), CPU::MC68000::Microcycle::PermitRead);
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reset();
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}
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void reset() {
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set_overlay(true);
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}
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@ -325,7 +330,11 @@ class ConcreteMachine:
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}
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uint8_t get_port_input(MOS::MOS6526::Port port) {
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(void)port;
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if(port) {
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LOG("TODO: parallel input?");
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} else {
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LOG("TODO: CIA A, port A input — FIR, RDY, TRK0, etc");
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}
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return 0xff;
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}
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