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https://github.com/TomHarte/CLK.git
synced 2026-04-21 02:17:08 +00:00
Eliminate 'addr' side effects.
This commit is contained in:
Thomas Harte
@@ -48,12 +48,12 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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#define restore_point() (__COUNTER__ + int(ResumePoint::Max) + int(AddressingMode::Max))
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#define join(a, b) a##b
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#define attach(a, b) join(a, b)
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#define join(a, b) a##b
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#define attach(a, b) join(a, b)
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#define access_label() attach(repeat, __LINE__)
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// TODO: find a way not to generate a restore point if pause precision and uses_ready_line/model allows it.
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#define access(type, addr, value) { \
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#define access(type, addr, value, ...) { \
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static constexpr int location = restore_point(); \
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[[fallthrough]]; case location: \
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[[maybe_unused]] access_label(): \
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@@ -80,11 +80,12 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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} else { \
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Data::Writeable target; \
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Storage::cycles_ -= Storage::bus_handler_.template perform<type>(addr, target); \
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WriteableReader::assign(value, target); \
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WriteableReader::assign(value, target); \
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} \
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} else { \
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Storage::cycles_ -= Storage::bus_handler_.template perform<type>(addr, value); \
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} \
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__VA_ARGS__; \
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}
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#define access_program(name) int(ResumePoint::Max) + int(AddressingMode::name)
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@@ -110,6 +111,12 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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Storage::decoded_.operation == Operation::SBC
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) && registers.flags.decimal;
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};
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const auto set_interrupt_flag = [&] {
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registers.flags.inverse_interrupt = 0;
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if constexpr (is_65c02(model)) {
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registers.flags.decimal = 0;
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}
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};
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using Literal = Address::Literal;
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using ZeroPage = Address::ZeroPage;
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@@ -207,8 +214,8 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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access_absolute_65c02_decimal:
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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perform_operation();
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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// MARK: - Fetch/decode.
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@@ -226,8 +233,7 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto interrupt;
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}
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access(BusOperation::ReadOpcode, Literal(registers.pc.full), Storage::opcode_);
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++registers.pc.full;
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access(BusOperation::ReadOpcode, Literal(registers.pc.full), Storage::opcode_, ++registers.pc.full);
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Storage::decoded_ = Decoder<model>::decode(Storage::opcode_);
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// 65c02 special case: support single-cycle NOPs.
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@@ -259,9 +265,7 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto fetch_decode;
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immediate_65c02_decimal:
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access(BusOperation::Read, Literal(registers.pc.full), Storage::operand_);
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++registers.pc.full;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::operand_, ++registers.pc.full);
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perform_operation();
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goto fetch_decode;
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@@ -277,14 +281,14 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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// MARK: - Stack.
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case access_program(Pull):
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access(BusOperation::Read, Stack(registers.s), Storage::operand_, ++registers.s);
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access(BusOperation::Read, Stack(registers.s), Storage::operand_);
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access(BusOperation::Read, Stack(registers.inc_s()), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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case access_program(Push):
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perform_operation();
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access(BusOperation::Write, Stack(registers.dec_s()), Storage::operand_);
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access(BusOperation::Write, Stack(registers.s), Storage::operand_, --registers.s);
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goto fetch_decode;
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// MARK: - Relative, and BBR/BBS (for the 65c02).
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@@ -314,9 +318,8 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.low);
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.low, ++registers.pc.full);
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++registers.pc.full;
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if(!test_bbr_bbs(Storage::opcode_, Storage::operand_)) {
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goto fetch_decode;
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}
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@@ -352,7 +355,7 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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// MARK: - Zero indirect (which is exclusive to the 65c02).
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case access_program(ZeroIndirect):
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access(BusOperation::Read, ZeroPage(Storage::operand_++), Storage::address_.halves.low);
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low, ++Storage::operand_);
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.high);
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goto access_absolute;
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@@ -418,17 +421,14 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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case access_program(IndexedIndirect):
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access(BusOperation::Read, ZeroPage(Storage::operand_), throwaway);
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Storage::operand_ += registers.x;
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low);
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++Storage::operand_;
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low, ++Storage::operand_);
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.high);
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goto access_absolute;
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// MARK: - Indirect indexed.
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case access_program(IndirectIndexed):
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low);
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++Storage::operand_;
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low, ++Storage::operand_);
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.high);
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Storage::operand_ = Storage::address_.halves.high;
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@@ -455,10 +455,8 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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case access_program(SHxAbsoluteXY):
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++registers.pc.full;
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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++registers.pc.full;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high, ++registers.pc.full);
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Storage::operand_ = Storage::address_.halves.high;
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Storage::address_.full += (Storage::decoded_.operation == Operation::SHY) ? registers.x : registers.y;
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@@ -490,10 +488,7 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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case access_program(SHxIndirectIndexed):
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++registers.pc.full;
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low);
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++Storage::operand_;
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low, ++Storage::operand_);
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.high);
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Storage::operand_ = Storage::address_.halves.high;
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@@ -534,31 +529,30 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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case access_program(JSR):
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++registers.pc.full;
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access(BusOperation::Read, Stack(registers.s), throwaway);
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access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.high);
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access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.low);
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access(BusOperation::Write, Stack(registers.s), registers.pc.halves.high, --registers.s);
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access(BusOperation::Write, Stack(registers.s), registers.pc.halves.low, --registers.s);
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access(BusOperation::Read, Literal(registers.pc.full), registers.pc.halves.high);
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registers.pc.halves.low = Storage::operand_;
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goto fetch_decode;
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case access_program(RTI):
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access(BusOperation::Read, Stack(registers.s), Storage::operand_);
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access(BusOperation::Read, Stack(registers.s), Storage::operand_, ++registers.s);
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access(BusOperation::Read, Stack(registers.inc_s()), Storage::operand_);
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access(BusOperation::Read, Stack(registers.s), Storage::operand_, ++registers.s);
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registers.flags = Flags(Storage::operand_);
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access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.low);
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access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.high);
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access(BusOperation::Read, Stack(registers.s), registers.pc.halves.low, ++registers.s);
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access(BusOperation::Read, Stack(registers.s), registers.pc.halves.high);
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goto fetch_decode;
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case access_program(RTS):
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access(BusOperation::Read, Stack(registers.s), Storage::operand_);
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access(BusOperation::Read, Stack(registers.s), Storage::operand_, ++registers.s);
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access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.low);
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access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.high);
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access(BusOperation::Read, Literal(registers.pc.full), throwaway);
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++registers.pc.full;
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access(BusOperation::Read, Stack(registers.s), registers.pc.halves.low, ++registers.s);
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access(BusOperation::Read, Stack(registers.s), registers.pc.halves.high);
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access(BusOperation::Read, Literal(registers.pc.full), throwaway, ++registers.pc.full);
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goto fetch_decode;
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@@ -595,7 +589,12 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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access(BusOperation::Read, Literal(registers.pc.full), throwaway);
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Storage::address_.full += registers.x;
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access(BusOperation::Read, Literal(Storage::address_.full++), registers.pc.halves.low);
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access(
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BusOperation::Read,
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Literal(Storage::address_.full),
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registers.pc.halves.low,
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++Storage::address_.full
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);
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access(BusOperation::Read, Literal(Storage::address_.full), registers.pc.halves.high);
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goto fetch_decode;
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@@ -604,19 +603,16 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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case access_program(BRK):
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++registers.pc.full;
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access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.high);
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access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.low);
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access(BusOperation::Write, Stack(registers.s), registers.pc.halves.high, --registers.s);
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access(BusOperation::Write, Stack(registers.s), registers.pc.halves.low, --registers.s);
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access(
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BusOperation::Write,
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Stack(registers.dec_s()),
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static_cast<uint8_t>(registers.flags) | Flag::Break
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Stack(registers.s),
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static_cast<uint8_t>(registers.flags) | Flag::Break,
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--registers.s
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);
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registers.flags.inverse_interrupt = 0;
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if constexpr (is_65c02(model)) {
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registers.flags.decimal = 0;
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}
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set_interrupt_flag();
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access(BusOperation::Read, Vector(0xfe), registers.pc.halves.low);
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access(BusOperation::Read, Vector(0xff), registers.pc.halves.high);
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goto fetch_decode;
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@@ -630,17 +626,16 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto reset;
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}
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access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.high);
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access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.low);
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access(BusOperation::Write, Stack(registers.s), registers.pc.halves.high, --registers.s);
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access(BusOperation::Write, Stack(registers.s), registers.pc.halves.low, --registers.s);
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access(
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BusOperation::Write,
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Stack(registers.dec_s()),
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static_cast<uint8_t>(registers.flags) & ~Flag::Break
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Stack(registers.s),
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static_cast<uint8_t>(registers.flags) & ~Flag::Break,
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--registers.s
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);
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registers.flags.inverse_interrupt = 0;
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if constexpr (is_65c02(model)) registers.flags.decimal = 0;
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set_interrupt_flag();
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if(Storage::captured_interrupt_requests_ & InterruptRequest::NMI) {
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Storage::inputs_.interrupt_requests &= ~InterruptRequest::NMI;
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goto nmi;
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@@ -656,13 +651,11 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto fetch_decode;
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reset:
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access(BusOperation::Read, Stack(registers.dec_s()), Storage::operand_);
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access(BusOperation::Read, Stack(registers.dec_s()), Storage::operand_);
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access(BusOperation::Read, Stack(registers.dec_s()), Storage::operand_);
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registers.flags.inverse_interrupt = 0;
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if constexpr (is_65c02(model)) registers.flags.decimal = 0;
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access(BusOperation::Read, Stack(registers.s), Storage::operand_, --registers.s);
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access(BusOperation::Read, Stack(registers.s), Storage::operand_, --registers.s);
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access(BusOperation::Read, Stack(registers.s), Storage::operand_, --registers.s);
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set_interrupt_flag();
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access(BusOperation::Read, Vector(0xfc), registers.pc.halves.low);
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access(BusOperation::Read, Vector(0xfd), registers.pc.halves.high);
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goto fetch_decode;
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@@ -121,9 +121,6 @@ struct Registers {
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Flags flags;
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auto operator <=> (const Registers &) const = default;
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uint8_t dec_s() { return s--; }
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uint8_t inc_s() { return ++s; }
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};
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}
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