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Ensures that the operand is the only thing failing in decoding of the first instruction.

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This commit is contained in:
Thomas Harte 2021-01-08 23:02:06 -05:00
parent 718f950071
commit 5f807b6e47
2 changed files with 12 additions and 1 deletions
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12
OSBindings/Mac/Clock SignalTests/x86DecoderTests.mm
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@ -15,6 +15,8 @@
namespace {
using Operation = CPU::Decoder::x86::Operation;
using Instruction = CPU::Decoder::x86::Instruction;
using Source = CPU::Decoder::x86::Source;
using Size = CPU::Decoder::x86::Size;
}
@interface x86DecoderTests : XCTestCase
@ -31,7 +33,13 @@ namespace {
// MARK: - Specific instruction asserts.
/* ... TODO ... */
- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size operand:(uint16_t)operand destination:(Source)destination {
XCTAssertEqual(instruction.operation, operation);
XCTAssertEqual(instruction.operation_size(), CPU::Decoder::x86::Size(size));
XCTAssertEqual(instruction.destination(), destination);
XCTAssertEqual(instruction.source(), Source::Immediate);
XCTAssertEqual(instruction.operand(), operand);
}
// MARK: - Decoder
@ -82,6 +90,8 @@ namespace {
// 68 instructions are expected.
XCTAssertEqual(instructions.size(), 63);
[self assert:instructions[0] operation:Operation::SUB size:2 operand:0xea77 destination:Source::AX];
// sub $0xea77,%ax
// jb 0x00000001
// dec %bx

1
Processors/Decoders/x86/x86.cpp
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@ -37,6 +37,7 @@ std::pair<int, Instruction> Decoder::decode(const uint8_t *source, size_t length
/// Handles instructions of the form rr, kk and rr, jjkk, i.e. a destination register plus an operand.
#define RegData(op, dest, size) \
SetOpSrcDestSize(op, DirectAddress, dest, size); \
source_ = Source::Immediate; \
operand_size_ = size; \
phase_ = Phase::AwaitingDisplacementOrOperand