6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-22 12:33:29 +00:00
Code Issues Projects Releases Wiki Activity

Add TRAP, TRAPV.

Browse Source
This commit is contained in:
Thomas Harte 2022-05-24 15:14:20 -04:00
parent 6f048de973
commit 780954f27b
2 changed files with 26 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
View File

@ -17,13 +17,7 @@
namespace CPU {
namespace MC68000Mk2 {
// TODO: BERR, interrupt inputs, etc; and obeying the trace flag.
// Also, from Instruction.hpp:
//
// TRAP, TRAPV
//
// Not provided by a 68000: Bccl, BSRl
// TODO: obeyance of the trace flag, the address/bus error exception.
/// States for the state machine which are named by
/// me for their purpose rather than automatically by file position.
@ -183,6 +177,8 @@ enum ExecutionState: int {
RESET,
NOP,
STOP,
TRAP,
TRAPV,
};
// MARK: - The state machine.
@ -880,6 +876,9 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
SpecialCASE(STOP);
SpecialCASE(TRAP);
SpecialCASE(TRAPV);
default:
assert(false);
}
@ -2274,6 +2273,25 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Prefetch();
MoveToStateSpecific(Decode);
//
// TRAP, TRAPV
//
// TODO: which program counter is appropriate for TRAP? That of the TRAP,
// or that of the instruction after?
BeginState(TRAP):
IdleBus(2);
exception_vector_ = (opcode_ & 15) + InstructionSet::M68k::Exception::TrapBase;
MoveToStateSpecific(StandardException);
BeginState(TRAPV):
Prefetch();
if(!status_.overflow_flag) {
MoveToStateSpecific(Decode);
}
exception_vector_ = InstructionSet::M68k::Exception::TRAPV;
MoveToStateSpecific(StandardException);
//
// Various states TODO.
//

2
Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
View File

@ -150,7 +150,6 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
template <typename IntT> void complete_bcc(bool, IntT);
inline void complete_dbcc(bool, bool, int16_t);
inline void bsr(uint32_t);
inline void stop() {} // TODO
inline void move_to_usp(uint32_t);
inline void move_from_usp(uint32_t &);
inline void tas(Preinstruction, uint32_t);
@ -170,6 +169,7 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
inline void rte() {}
inline void rts() {}
inline void reset() {}
inline void stop() {}
// Some microcycles that will be modified as required and used in the main loop;
// the semantics of a switch statement make in-place declarations awkward and