6502/CLK
1
0 Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2026-10-22 04:02:53 +00:00
Code Issues Projects Releases Wiki Activity

Make access a 6809 norm; expose MO6 to SDL users.

Browse Source
This commit is contained in:
Thomas Harte committed 2026-04-12 19:02:55 -04:00
1 parent 9a19243720
commit 8a765031e1
3 files changed
+31 -31
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Analyser/Static/Thomson/Target.hpp
-8
View File
@@ -33,14 +33,6 @@ private:
DeclareField(floppy);
AnnounceEnum(Model);
DeclareField(model);
// TODO: eliminate this if/when MO6 emulation works.
limit_enum(
&model,
Model::MO5v1,
Model::MO5v11,
-1
);
}
};
Machines/Thomson/MO5/MO5.cpp
+5 -22
View File
@@ -112,27 +112,6 @@ struct ConcreteMachine:
audio_queue_.lock_flush();
}
template <
int address,
CPU::M6809::ReadWrite read_write,
typename ComponentT
>
static void access(ComponentT &component, CPU::M6809::data_t<read_write> value) {
if constexpr (CPU::M6809::is_read(read_write)) {
if constexpr (requires { component.operator->(); }) {
value = component->template read<address>();
} else {
value = component.template read<address>();
}
} else {
if constexpr (requires { component.operator->(); }) {
component->template write<address>(value);
} else {
component.template write<address>(value);
}
}
}
template <
CPU::M6809::BusPhase bus_phase,
CPU::M6809::LIC lic,
@@ -181,6 +160,9 @@ struct ConcreteMachine:
};
switch(address) {
// TODO: Is there a simpler way to use `namespace`?
using namespace CPU::M6809;
case 0xa7c0: access<0xa7c0, read_write>(system_pia_, value); break;
case 0xa7c1: access<0xa7c1, read_write>(system_pia_, value); break;
case 0xa7c2: access<0xa7c2, read_write>(system_pia_, value); break;
@@ -199,6 +181,7 @@ struct ConcreteMachine:
case 0xa7e4: if(is_mo6) access<0xa7e4, read_write>(memory_, value); else unmapped(); break;
// TODO: consolidate below.
case 0xa7e5:
if constexpr (is_mo6) {
if(memory_.access_mode() == AccessMode::System) {
@@ -220,7 +203,7 @@ struct ConcreteMachine:
access<0xa7e6, read_write>(memory_, value);
} else {
if constexpr (CPU::M6809::is_read(read_write)) {
value = video_->horizontal_state();
access<0xa7e6, read_write>(video_, value);
} else {
memory_.template write<0xa7e6>(value);
}
Processors/6809/6809.hpp
+26 -1
View File
@@ -95,7 +95,6 @@ static constexpr Timescale duration([[maybe_unused]] const BusPhase phase) {
}
}
enum class Line {
Halt,
DMABusReq,
@@ -157,6 +156,32 @@ using NoValue = Bus::Data::NoValue<uint8_t>;
template <ReadWrite read_write>
using data_t = Bus::Data::data_t<uint8_t, false, access_type(read_write)>;
// MARK: - Bus-access helper.
/*!
Interprets @c read_write to perform either a `read<address>` or a `write<address>` on `component`.
*/
template <
int address,
ReadWrite read_write,
typename ComponentT
>
static void access(ComponentT &component, CPU::M6809::data_t<read_write> value) {
if constexpr (CPU::M6809::is_read(read_write)) {
if constexpr (requires { component.operator->(); }) {
value = component->template read<address>();
} else {
value = component.template read<address>();
}
} else {
if constexpr (requires { component.operator->(); }) {
component->template write<address>(value);
} else {
component.template write<address>(value);
}
}
}
// MARK: - Code-generation choices.
enum class PausePrecision {