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Add some register switch tests.

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This commit is contained in:
Thomas Harte 2024-03-08 11:34:10 -05:00
parent a46ec4cffb
commit 9406a97141
1 changed files with 67 additions and 0 deletions
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67
OSBindings/Mac/Clock SignalTests/ARMDecoderTests.mm
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@ -210,6 +210,73 @@ struct Memory {
XCTAssertEqual(carry, 0); XCTAssertEqual(carry, 0);
} }
- (void)testRegisterModes {
Registers r;
// Set all user mode registers to their indices.
r.set_mode(Mode::User);
for(int c = 0; c < 15; c++) {
r[c] = c;
}
// Set FIQ registers.
r.set_mode(Mode::FIQ);
for(int c = 8; c < 15; c++) {
r[c] = c | 0x100;
}
// Set IRQ registers.
r.set_mode(Mode::IRQ);
for(int c = 13; c < 15; c++) {
r[c] = c | 0x200;
}
// Set supervisor registers.
r.set_mode(Mode::FIQ);
r.set_mode(Mode::User);
r.set_mode(Mode::Supervisor);
for(int c = 13; c < 15; c++) {
r[c] = c | 0x300;
}
// Check all results.
r.set_mode(Mode::User);
r.set_mode(Mode::FIQ);
for(int c = 0; c < 8; c++) {
XCTAssertEqual(r[c], c);
}
for(int c = 8; c < 15; c++) {
XCTAssertEqual(r[c], c | 0x100);
}
r.set_mode(Mode::FIQ);
r.set_mode(Mode::IRQ);
r.set_mode(Mode::User);
r.set_mode(Mode::FIQ);
r.set_mode(Mode::Supervisor);
for(int c = 0; c < 13; c++) {
XCTAssertEqual(r[c], c);
}
for(int c = 13; c < 15; c++) {
XCTAssertEqual(r[c], c | 0x300);
}
r.set_mode(Mode::FIQ);
r.set_mode(Mode::User);
for(int c = 0; c < 15; c++) {
XCTAssertEqual(r[c], c);
}
r.set_mode(Mode::Supervisor);
r.set_mode(Mode::IRQ);
for(int c = 0; c < 13; c++) {
XCTAssertEqual(r[c], c);
}
for(int c = 13; c < 15; c++) {
XCTAssertEqual(r[c], c | 0x200);
}
}
// TODO: turn the below into a trace-driven test case. // TODO: turn the below into a trace-driven test case.
- (void)testROM319 { - (void)testROM319 {
constexpr ROM::Name rom_name = ROM::Name::AcornRISCOS319; constexpr ROM::Name rom_name = ROM::Name::AcornRISCOS319;