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https://github.com/TomHarte/CLK.git
synced 2025-01-26 15:32:04 +00:00
Edges closer towards proper DMA operation.
Specifically: differentiates the three kinds of DMA operation. Still doesn't act correctly with regard to DACK though, and leaves the bus instantaneously improperly formed. Which I'm tempted to try to fix on the target side by properly obeying delays.
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@ -25,6 +25,14 @@ void NCR5380::write(int address, uint8_t value, bool dma_acknowledge) {
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case 0:
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LOG("[SCSI 0] Set current SCSI bus state to " << PADHEX(2) << int(value));
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data_bus_ = value;
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if(dma_request_ && dma_operation_ == DMAOperation::Send) {
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printf("w %02x\n", value);
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dma_acknowledge_ = true;
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dma_request_ = false;
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update_control_output();
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bus_.set_device_output(device_id_, bus_output_);
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}
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break;
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case 1: {
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@ -89,14 +97,17 @@ void NCR5380::write(int address, uint8_t value, bool dma_acknowledge) {
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case 5:
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LOG("[SCSI 5] Start DMA send: " << PADHEX(2) << int(value));
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dma_operation_ = DMAOperation::Send;
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break;
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case 6:
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LOG("[SCSI 6] Start DMA target receive: " << PADHEX(2) << int(value));
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dma_operation_ = DMAOperation::TargetReceive;
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break;
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case 7:
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LOG("[SCSI 7] Start DMA initiator receive: " << PADHEX(2) << int(value));
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dma_operation_ = DMAOperation::InitiatorReceive;
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break;
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}
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@ -121,7 +132,7 @@ uint8_t NCR5380::read(int address, bool dma_acknowledge) {
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case 0:
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LOG("[SCSI 0] Get current SCSI bus state: " << PADHEX(2) << (bus_.get_state() & 0xff));
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if(dma_request_ && state_ == ExecutionState::PerformingDMA) {
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if(dma_request_ && dma_operation_ == DMAOperation::InitiatorReceive) {
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dma_acknowledge_ = true;
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dma_request_ = false;
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update_control_output();
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@ -76,8 +76,9 @@ class NCR5380 final: public ClockingHint::Source {
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} state_ = ExecutionState::None;
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enum class DMAOperation {
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Ready,
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Reading,
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Writing
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Send,
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TargetReceive,
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InitiatorReceive
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} dma_operation_ = DMAOperation::Ready;
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int time_in_state_ = 0;
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bool lost_arbitration_ = false, arbitration_in_progress_ = false;
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