mirror of
https://github.com/TomHarte/CLK.git
synced 2024-12-26 09:29:45 +00:00
Factors out some boilerplate and introduces second sequence.
This commit is contained in:
Thomas Harte
parent
c934e22cee
commit
eb8d0eefd5
@ -12,6 +12,7 @@
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namespace {
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using Operation = CPU::Decoder::PowerPC::Operation;
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using Instruction = CPU::Decoder::PowerPC::Instruction;
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}
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@interface PowerPCDecoderTests : XCTestCase
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@ -23,9 +24,83 @@ namespace {
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disassembler elsewhere.
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*/
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@implementation PowerPCDecoderTests {
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CPU::Decoder::PowerPC::Instruction instructions[32];
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Instruction instructions[32];
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}
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// MARK: - Specific instruction asserts.
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- (void)assertUndefined:(Instruction &)instruction {
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XCTAssertEqual(instruction.operation, Operation::Undefined);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation rD:(int)rD rA:(int)rA simm:(int)simm {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.rD(), rD);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.simm(), simm);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation rD:(int)rD rA:(int)rA d:(int)d {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.rD(), rD);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.d(), d);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation rA:(int)rA rS:(int)rS uimm:(int)uimm {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.rS(), rS);
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XCTAssertEqual(instruction.uimm(), uimm);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation rS:(int)rS rA:(int)rA d:(int)d {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.rS(), rS);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.d(), d);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation frD:(int)frD rA:(int)rA d:(int)d {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.frD(), frD);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.d(), d);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation frS:(int)frS rA:(int)rA d:(int)d {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.frS(), frS);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.d(), d);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation li:(int)li lk:(BOOL)lk aa:(BOOL)aa {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.li(), li);
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XCTAssertEqual(!!instruction.lk(), lk);
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XCTAssertEqual(!!instruction.aa(), aa);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation rA:(int)rA rS:(int)rS rB:(int)rB mb:(int)mb me:(int)me rc:(BOOL)rc {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.rS(), rS);
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XCTAssertEqual(instruction.rB(), rB);
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XCTAssertEqual(instruction.mb(), mb);
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XCTAssertEqual(instruction.me(), me);
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XCTAssertEqual(!!instruction.rc(), rc);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation to:(int)to rA:(int)rA simm:(int)simm {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.to(), to);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.simm(), simm);
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}
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// MARK: - Decoder
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- (void)decode:(const uint32_t *)stream {
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CPU::Decoder::PowerPC::Decoder decoder(CPU::Decoder::PowerPC::Model::MPC601);
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for(int c = 0; c < 32; c++) {
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@ -33,8 +108,10 @@ namespace {
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}
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}
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- (void)testStream1 {
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const uint32_t stream[] = {
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// MARK: - Tests
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- (void)testSequence1 {
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const uint32_t sequence[] = {
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0x32eeefa5, 0xc2ee0786, 0x80ce552c, 0x88d5f02a,
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0xf8c2e801, 0xe83d5cdf, 0x7fa51fbb, 0xaacea8b0,
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0x7d4d4d21, 0x1314cf89, 0x47e0014b, 0xdf67566d,
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@ -44,160 +121,167 @@ namespace {
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0x1ed4751d, 0x86af76e4, 0x151405a9, 0xca0ac015,
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0x60dd1f9d, 0xecff44f6, 0xf2c1110e, 0x9aa6653b,
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};
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[self decode:stream];
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[self decode:sequence];
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// addic r23,r14,-4187
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XCTAssertEqual(instructions[0].operation, Operation::addic);
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XCTAssertEqual(instructions[0].rD(), 23);
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XCTAssertEqual(instructions[0].rA(), 14);
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XCTAssertEqual(instructions[0].simm(), -4187);
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// lfs f23,1926(r14)
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XCTAssertEqual(instructions[1].operation, Operation::lfs);
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XCTAssertEqual(instructions[1].frD(), 23);
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XCTAssertEqual(instructions[1].rA(), 14);
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XCTAssertEqual(instructions[1].d(), 1926);
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// lwz r6,21804(r14)
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XCTAssertEqual(instructions[2].operation, Operation::lwz);
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XCTAssertEqual(instructions[2].rD(), 6);
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XCTAssertEqual(instructions[2].rA(), 14);
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XCTAssertEqual(instructions[2].d(), 21804);
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// lbz r6,-4054(r21)
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XCTAssertEqual(instructions[3].operation, Operation::lbz);
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XCTAssertEqual(instructions[3].rD(), 6);
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XCTAssertEqual(instructions[3].rA(), 21);
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XCTAssertEqual(instructions[3].d(), -4054);
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[self assert:instructions[0] operation:Operation::addic rD:23 rA:14 simm:-4187];
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[self assert:instructions[1] operation:Operation::lfs frD:23 rA:14 d:1926];
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[self assert:instructions[2] operation:Operation::lwz rD:6 rA:14 d:21804];
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[self assert:instructions[3] operation:Operation::lbz rD:6 rA:21 d:-4054];
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// .long 0xf8c2e801
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// .long 0xe83d5cdf
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// .long 0x7fa51fbb
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XCTAssertEqual(instructions[4].operation, Operation::Undefined);
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XCTAssertEqual(instructions[5].operation, Operation::Undefined);
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XCTAssertEqual(instructions[6].operation, Operation::Undefined);
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// lha r22,-22352(r14)
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XCTAssertEqual(instructions[7].operation, Operation::lha);
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XCTAssertEqual(instructions[7].rD(), 22);
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XCTAssertEqual(instructions[7].rA(), 14);
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XCTAssertEqual(instructions[7].d(), -22352);
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[self assertUndefined:instructions[4]];
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[self assertUndefined:instructions[5]];
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[self assertUndefined:instructions[6]];
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[self assert:instructions[7] operation:Operation::lha rD:22 rA:14 d:-22352];
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// .long 0x7d4d4d21
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// .long 0x1314cf89
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// .long 0x47e0014b
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XCTAssertEqual(instructions[8].operation, Operation::Undefined);
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XCTAssertEqual(instructions[9].operation, Operation::Undefined);
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[self assertUndefined:instructions[8]];
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[self assertUndefined:instructions[9]];
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// CLK decodes this as sc because it ignores reserved bits; the disassembler
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// I used checks the reserved bits. For now: don't test.
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// XCTAssertEqual(instructions[10].operation, Operation::Undefined);
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// stfdu f27,22125(r7)
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XCTAssertEqual(instructions[11].operation, Operation::stfdu);
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XCTAssertEqual(instructions[11].frS(), 27);
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XCTAssertEqual(instructions[11].rA(), 7);
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XCTAssertEqual(instructions[11].d(), 22125);
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// .long 0xfb29a33e
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XCTAssertEqual(instructions[12].operation, Operation::Undefined);
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// addic r9,r12,-16557
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XCTAssertEqual(instructions[13].operation, Operation::addic);
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XCTAssertEqual(instructions[13].rD(), 9);
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XCTAssertEqual(instructions[13].rA(), 12);
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XCTAssertEqual(instructions[13].simm(), -16557);
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// andi. r15,r3,6677
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XCTAssertEqual(instructions[14].operation, Operation::andi_);
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XCTAssertEqual(instructions[14].rA(), 15);
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XCTAssertEqual(instructions[14].rS(), 3);
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XCTAssertEqual(instructions[14].uimm(), 6677);
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[self assert:instructions[11] operation:Operation::stfdu frS:27 rA:7 d:22125];
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[self assertUndefined:instructions[12]];
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[self assert:instructions[13] operation:Operation::addic rD:9 rA:12 simm:-16557];
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[self assert:instructions[14] operation:Operation::andi_ rA:15 rS:3 uimm:6677];
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// lha r3,28689(r27)
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XCTAssertEqual(instructions[15].operation, Operation::lha);
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XCTAssertEqual(instructions[15].rD(), 3);
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XCTAssertEqual(instructions[15].rA(), 27);
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XCTAssertEqual(instructions[15].d(), 28689);
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// subfic r8,r7,2316
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XCTAssertEqual(instructions[16].operation, Operation::subfic);
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XCTAssertEqual(instructions[16].rD(), 8);
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XCTAssertEqual(instructions[16].rA(), 7);
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XCTAssertEqual(instructions[16].simm(), 2316);
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// lfdu f16,-27810(r4)
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XCTAssertEqual(instructions[17].operation, Operation::lfdu);
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XCTAssertEqual(instructions[17].frD(), 16);
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XCTAssertEqual(instructions[17].rA(), 4);
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XCTAssertEqual(instructions[17].d(), -27810);
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// oris r14,r1,17994
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XCTAssertEqual(instructions[18].operation, Operation::oris);
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XCTAssertEqual(instructions[18].rA(), 14);
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XCTAssertEqual(instructions[18].rS(), 1);
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XCTAssertEqual(instructions[18].uimm(), 17994);
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[self assert:instructions[15] operation:Operation::lha rD:3 rA:27 d:28689];
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[self assert:instructions[16] operation:Operation::subfic rD:8 rA:7 simm:2316];
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[self assert:instructions[17] operation:Operation::lfdu frD:16 rA:4 d:-27810];
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[self assert:instructions[18] operation:Operation::oris rA:14 rS:1 uimm:17994];
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// stw r24,-28998(r30)
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XCTAssertEqual(instructions[19].operation, Operation::stw);
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XCTAssertEqual(instructions[19].rS(), 24);
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XCTAssertEqual(instructions[19].rA(), 30);
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XCTAssertEqual(instructions[19].d(), -28998);
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// .long 0xee396d5b
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XCTAssertEqual(instructions[20].operation, Operation::Undefined);
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// bl 0x01011890 [disassmebled at address 0x54]
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XCTAssertEqual(instructions[21].operation, Operation::bx);
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XCTAssertEqual(instructions[21].li() + 0x54, 0x01011890);
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XCTAssertTrue(instructions[21].lk());
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XCTAssertFalse(instructions[21].aa());
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// addic r14,r12,-21862
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XCTAssertEqual(instructions[22].operation, Operation::addic);
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XCTAssertEqual(instructions[22].rD(), 14);
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XCTAssertEqual(instructions[22].rA(), 12);
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XCTAssertEqual(instructions[22].simm(), -21862);
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[self assert:instructions[19] operation:Operation::stw rS:24 rA:30 d:-28998];
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[self assertUndefined:instructions[20]];
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[self assert:instructions[21] operation:Operation::bx li:0x01011890 - 0x54 lk:TRUE aa:FALSE];
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[self assert:instructions[22] operation:Operation::addic rD:14 rA:12 simm:-21862];
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// .long 0x42b61a86 [10101]
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XCTAssertEqual(instructions[23].operation, Operation::Undefined);
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// mulli r22,r20,29981
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XCTAssertEqual(instructions[24].operation, Operation::mulli);
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XCTAssertEqual(instructions[24].rD(), 22);
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XCTAssertEqual(instructions[24].rA(), 20);
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XCTAssertEqual(instructions[24].simm(), 29981);
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// lwzu r21,30436(r15)
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XCTAssertEqual(instructions[25].operation, Operation::lwzu);
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XCTAssertEqual(instructions[25].rD(), 21);
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XCTAssertEqual(instructions[25].rA(), 15);
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XCTAssertEqual(instructions[25].d(), 30436);
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// .long 0x151405a9
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XCTAssertEqual(instructions[26].operation, Operation::Undefined);
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[self assertUndefined:instructions[23]];
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[self assert:instructions[24] operation:Operation::mulli rD:22 rA:20 simm:29981];
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[self assert:instructions[25] operation:Operation::lwzu rD:21 rA:15 d:30436];
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[self assertUndefined:instructions[26]];
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// lfd f16,-16363(r10)
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XCTAssertEqual(instructions[27].operation, Operation::lfd);
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XCTAssertEqual(instructions[27].frD(), 16);
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XCTAssertEqual(instructions[27].rA(), 10);
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XCTAssertEqual(instructions[27].d(), -16363);
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// ori r29,r6,8093
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XCTAssertEqual(instructions[28].operation, Operation::ori);
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XCTAssertEqual(instructions[28].rA(), 29);
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XCTAssertEqual(instructions[28].rS(), 6);
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XCTAssertEqual(instructions[28].uimm(), 8093);
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// .long 0xecff44f6
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// .long 0xf2c1110e
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XCTAssertEqual(instructions[29].operation, Operation::Undefined);
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XCTAssertEqual(instructions[30].operation, Operation::Undefined);
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// stb r21,25915(r6)
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XCTAssertEqual(instructions[31].operation, Operation::stb);
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XCTAssertEqual(instructions[31].rS(), 21);
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XCTAssertEqual(instructions[31].rA(), 6);
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XCTAssertEqual(instructions[31].d(), 25915);
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[self assert:instructions[27] operation:Operation::lfd frD:16 rA:10 d:-16363];
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[self assert:instructions[28] operation:Operation::ori rA:29 rS:6 uimm:8093];
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[self assertUndefined:instructions[29]];
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[self assertUndefined:instructions[30]];
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[self assert:instructions[31] operation:Operation::stb rS:21 rA:6 d:25915];
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}
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- (void)testSequence2 {
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const uint32_t sequence[] = {
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0x90252dae, 0x7429ee14, 0x618935bc, 0xd6c94af0,
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0xba1d295f, 0x649e3869, 0x6def742c, 0x5c64cdce,
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0x762d59ee, 0x565c8189, 0xc7c59f81, 0xce1157fd,
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0xc86aef59, 0x81325882, 0x1336fad6, 0xe1ddfa2b,
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0x18c60357, 0x4c122cb5, 0xccb1f749, 0xdbdcebc3,
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0x0fc60187, 0x117eb911, 0x80334c43, 0xe65371e8,
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0xa047c94d, 0xe671dd0b, 0xe07992bb, 0x6a332fe8,
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0xfc361c6b, 0x5e8b5a28, 0xb2b64a22, 0x045dd156,
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};
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[self decode:sequence];
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// stw r1,11694(r5)
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// andis. r9,r1,60948
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// ori r9,r12,13756
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// stfsu f22,19184(r9)
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[self assert:instructions[0] operation:Operation::stw rS:1 rA:5 d:11694];
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[self assert:instructions[1] operation:Operation::andis_ rA:9 rS:1 uimm:60948];
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[self assert:instructions[2] operation:Operation::ori rA:9 rS:12 uimm:13756];
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[self assert:instructions[3] operation:Operation::stfsu frS:22 rA:9 d:19184];
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// lmw r16,10591(r29)
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// oris r30,r4,14441
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// xoris r15,r15,29740
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// rlwnm r4,r3,r25,23,7
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[self assert:instructions[4] operation:Operation::lmw rD:16 rA:29 d:10591];
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[self assert:instructions[5] operation:Operation::oris rA:30 rS:4 uimm:14441];
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[self assert:instructions[6] operation:Operation::xoris rA:15 rS:15 uimm:29740];
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[self assert:instructions[7] operation:Operation::rlwnmx rA:4 rS:3 rB:25 mb:23 me:7 rc:FALSE];
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// andis. r13,r17,23022
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// rlwinm. r28,r18,16,6,4
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// lfsu f30,-24703(r5)
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// lfdu f16,22525(r17)
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[self assert:instructions[8] operation:Operation::andis_ rA:13 rS:17 uimm:23022];
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[self assert:instructions[9] operation:Operation::rlwinmx rA:28 rS:18 rB:16 mb:6 me:4 rc:TRUE];
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[self assert:instructions[10] operation:Operation::lfsu frD:30 rA:5 d:-24703];
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[self assert:instructions[11] operation:Operation::lfdu frD:16 rA:17 d:22525];
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// lfd f3,-4263(r10)
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// lwz r9,22658(r18)
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// .long 0x1336fad6
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// .long 0xe1ddfa2b
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[self assert:instructions[12] operation:Operation::lfd frD:3 rA:10 d:-4263];
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[self assert:instructions[13] operation:Operation::lwz rD:9 rA:18 d:22658];
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[self assertUndefined:instructions[14]];
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[self assertUndefined:instructions[15]];
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// .long 0x18c60357
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// .long 0x4c122cb5
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// lfdu f5,-2231(r17)
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// stfd f30,-5181(r28)
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[self assertUndefined:instructions[16]];
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[self assertUndefined:instructions[17]];
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[self assert:instructions[18] operation:Operation::lfdu frD:5 rA:17 d:-2231];
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[self assert:instructions[19] operation:Operation::stfd frD:30 rA:28 d:-5181];
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// twi 30,r6,391
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// .long 0x117eb911
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// lwz r1,19523(r19)
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// .long 0xe65371e8
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[self assert:instructions[20] operation:Operation::twi to:30 rA:6 simm:391];
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[self assertUndefined:instructions[21]];
|
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[self assert:instructions[22] operation:Operation::lwz rD:1 rA:19 d:19523];
|
||||
[self assertUndefined:instructions[23]];
|
||||
|
||||
// lhz r2,-14003(r7)
|
||||
// .long 0xe671dd0b
|
||||
// .long 0xe07992bb
|
||||
// xori r19,r17,12264
|
||||
[self assert:instructions[24] operation:Operation::lhz rD:2 rA:7 d:-14003];
|
||||
[self assertUndefined:instructions[25]];
|
||||
[self assertUndefined:instructions[26]];
|
||||
[self assert:instructions[27] operation:Operation::xori rA:19 rS:17 uimm:12264];
|
||||
|
||||
// .long 0xfc361c6b
|
||||
// rlwnm r11,r20,r11,8,20
|
||||
// sth r21,18978(r22)
|
||||
// .long 0x45dd156
|
||||
// [self assertUndefined:instructions[28]]; // Disabled due to reserved field; I'm decoding this as faddx.
|
||||
[self assert:instructions[29] operation:Operation::rlwnmx rA:11 rS:20 rB:11 mb:8 me:20 rc:FALSE];
|
||||
[self assert:instructions[30] operation:Operation::sth rS:21 rA:22 d:18978];
|
||||
[self assertUndefined:instructions[31]];
|
||||
}
|
||||
|
||||
@end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user