Thomas Harte
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034056d0cd
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Adds full 8-bit clock addressing; stubs clock into the IIgs.
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2020-10-29 21:38:36 -04:00 |
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Thomas Harte
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5a8b8478d2
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Corrects unhandled IO assert.
The IIgs proper is actually waiting on communication with the RTC.
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2020-10-28 22:14:02 -04:00 |
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Thomas Harte
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6c54699c44
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Connects up an SCC.
Thereby putting my IIgs into its first perpetual loop. Trying to do something with the SCC I haven't implemented yet perhaps?
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2020-10-28 22:07:34 -04:00 |
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Thomas Harte
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94a6da6b7d
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Exposes much of the auxiliary and language card stuff to the IIgs bus.
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2020-10-28 21:58:20 -04:00 |
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Thomas Harte
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885fae1534
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Stubs in a speed register.
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2020-10-28 21:23:45 -04:00 |
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Thomas Harte
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1e4679ae14
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Corrects JSL and RTL.
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2020-10-28 17:25:40 -04:00 |
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Thomas Harte
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267dd59a59
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Gets as far as seemingly yet another memory-map setting.
Tomorrow, maybe?
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2020-10-27 22:31:58 -04:00 |
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Thomas Harte
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0a91ac5af5
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Adds some extra notes, starts getting into trying to run the IIgs.
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2020-10-27 22:09:45 -04:00 |
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Thomas Harte
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ed510409c4
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Starts memory map test class, already finding a typo.
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2020-10-25 21:31:21 -04:00 |
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Thomas Harte
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7614eba4bf
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Factors out the IIgs memory map logic.
As testing would be rational.
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2020-10-25 21:10:04 -04:00 |
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Thomas Harte
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13c8032465
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ROM isn't writeable. The clue is in the name.
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2020-10-25 18:29:17 -04:00 |
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Thomas Harte
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44fc08cd5b
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Switches to a mapping system that supports non-continuous regions, and is smaller.
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2020-10-25 18:28:32 -04:00 |
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Thomas Harte
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ddd84db510
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Edges towards a functioning IIgs memory map.
Next up: making sure language and auxiliary switches apply. That should get something from the ROM.
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2020-10-23 19:41:10 -04:00 |
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Thomas Harte
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817f93a490
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Edges towards a working memory subsystem. At least structurally.
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2020-10-22 19:25:04 -04:00 |
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Thomas Harte
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43611792ac
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Adds just enough to get a 65816 ticking over.
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2020-10-21 21:19:18 -04:00 |
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Thomas Harte
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5287c57ee0
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Adds the IIgs as a user-selectable machine.
Albeit that there is no underlying machine yet.
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2020-10-20 22:18:11 -04:00 |
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