Thomas Harte
07582cee4a
BusGrant is a further signal I will need.
2019-11-03 21:10:42 -05:00
Thomas Harte
c070f2100c
Attempts to regularise data bus access.
2019-11-01 23:01:06 -04:00
Thomas Harte
9ef1211d53
Adds missing header file.
2019-07-24 22:13:32 -04:00
Thomas Harte
1327de1c82
Slims the Program struct down to 8 bytes total.
2019-07-24 22:02:50 -04:00
Thomas Harte
ed4ddcfda8
Reduces call/return overhead on Microcycle methods.
2019-07-09 19:55:30 -04:00
Thomas Harte
3ec9a1d869
Incorporates JMP tests, fixes JSR (xxx).l timing.
2019-06-24 15:36:33 -04:00
Thomas Harte
faef917cbd
Improves resizeable microcycle test.
2019-06-24 10:55:22 -04:00
Thomas Harte
86fdc75feb
Incorporates RTR test, adding a ProcessorState helper.
2019-06-23 18:37:32 -04:00
Thomas Harte
91ced056d2
Adds tests for ADD. No failures.
2019-06-19 18:56:21 -04:00
Thomas Harte
8182b0363f
Adds enum to help with status decoding.
2019-06-19 17:01:49 -04:00
Thomas Harte
2c9a1f7b16
Restores vector.
2019-05-03 14:50:07 -04:00
Thomas Harte
0ea4c1ac80
Evicts #includes from my namespace.
2019-05-03 14:48:39 -04:00
Thomas Harte
34fe9981e4
Added necessary mea culpas.
2019-05-03 14:25:25 -04:00
Thomas Harte
291e91375f
Takes a shot at the synchronous bus.
2019-05-03 14:20:59 -04:00
Thomas Harte
bb07206c55
Corrects internet response to work as currently implemented.
...
Also makes corrections to the bus error and address error exceptions.
2019-05-01 21:59:06 -04:00
Thomas Harte
f6ac407e4d
Takes further steps towards supporting interrupts.
...
Specifically:
* introduces the necessary bus signalling; and
* adds corresponding functional steps.
Still to figure out: getting into and out of an interrupt cycle.
2019-05-01 15:19:24 -04:00
Thomas Harte
92568c90c8
Adds support for HALT as an input, and puts some effort into how to calculate E.
2019-04-30 22:07:48 -04:00
Thomas Harte
31bb770fdd
Implement STOPpages, waits for DTack, and bus and address error exceptions.
2019-04-30 19:24:22 -04:00
Thomas Harte
3060175ff5
Eliminates constructions of std::tuple for performance reasons.
...
Specifically: reduces 68000 construction time from 10+ seconds to more like 2.8.
2019-04-29 22:43:15 -04:00
Thomas Harte
3da1b3bf9b
Introduces storage for various bus inputs.
2019-04-29 19:22:05 -04:00
Thomas Harte
d9071ee9f1
Starts sketching out the asynchronous bus.
2019-04-29 13:45:53 -04:00
Thomas Harte
033b8e6b36
ADD/SUBQ #, An shouldn't set flags.
...
Also, temporarily at least, adds a new means for observing CPU behaviour.
2019-04-24 09:59:54 -04:00
Thomas Harte
2d97fc1f59
Beefs up documentation and developer support.
2019-04-19 13:29:35 -04:00
Thomas Harte
bc6349f823
Adds RESET, fixes branches and attempts to fix CMPI.
2019-03-29 23:40:54 -04:00
Thomas Harte
0d7bbdad54
Begins a basic get/set state API, allowing some actual unit tests, implying an ABCD fix.
2019-03-17 21:57:00 -04:00
Thomas Harte
d0c5cf0d2d
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-16 21:47:46 -04:00
Thomas Harte
388d808536
Switches to providing UDS and LDS implicitly via address.
...
Also makes sure that the difference between a non-data cycle that starts without the address strobe active and one that starts with it active can be discerned.
2019-03-16 17:54:58 -04:00
Thomas Harte
33b53e7605
Settles upon disassembly as the route in, and begins work in that direction.
2019-03-11 22:47:58 -04:00
Thomas Harte
89c71f9119
Introduces EmuTOS, and starts constructing test cases around it.
2019-03-10 18:40:12 -04:00
Thomas Harte
98aa597510
A theoretical 68000 could now perform its /RESET. That's all though.
2019-03-10 17:42:13 -04:00
Thomas Harte
de56d48b2f
Embraces a more communicative 68000 bus.
2019-03-10 17:27:34 -04:00
Thomas Harte
b9b52b7c8b
Begins some very early sketching out of a 68000.
2019-03-09 00:00:23 -05:00
