Thomas Harte
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da082673d7
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Drives now have a finite number of heads.
The Amstrad volunteers itself to be single sided. Everything else stays as it was.
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2017-09-15 21:18:36 -04:00 |
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Thomas Harte
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d3c385b471
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Separates the 8272's drive selection signalling from actual drive ownership.
Thereby returns working motor control to the CPC.
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2017-09-11 21:25:26 -04:00 |
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Thomas Harte
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96bf133924
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Withdraws requirement for DiskController users to specify a PLL multiplier or to provide rotation speed.
In the latter case because it's no longer of any interest to the controller, and in the former because I'd rather it be picked automatically.
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2017-09-10 22:56:05 -04:00 |
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Thomas Harte
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0622187ddf
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Strips Controller of all capabilities now housed on the Drive.
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2017-09-10 19:23:23 -04:00 |
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Thomas Harte
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57bfec285f
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Makes it optional whether the Z80 supports the wait line. If the wait line isn't in use, runtime costs are decreased because the optional wait cycles need not be iterated over.
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2017-08-26 23:08:57 -04:00 |
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Thomas Harte
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e7ad79c79a
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Breaks apart the CPC's 6845 bus handler to obey phase 1 and phase 2, and now back-dates interrupts when appropriate.
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2017-08-26 14:07:51 -04:00 |
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Thomas Harte
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6e99169348
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Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.
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2017-08-26 12:59:59 -04:00 |
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Thomas Harte
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ee71be0e7e
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Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
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2017-08-21 21:56:42 -04:00 |
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Thomas Harte
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cde29c4bf4
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Added forceinlines and properly declared finals and overrides.
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2017-08-21 21:07:10 -04:00 |
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Thomas Harte
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e1aded0d95
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Allows Z80 users to opt out of support for the bus request line. Which both now do.
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2017-08-21 20:43:12 -04:00 |
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Thomas Harte
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0cbc1753b9
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Quick fixes: the binary tape player now considers talk to the sleep observer only if motor control changes. The Amstrad CPC no longer attempts to use the component argument to identify the caller, since this will often be that of the superclass and not that of the derived class known to the CPC.
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2017-08-20 13:18:46 -04:00 |
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Thomas Harte
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8f5ae4a326
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The CPC now responds to tape-originating sleeper observations.
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2017-08-20 12:21:02 -04:00 |
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Thomas Harte
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e88a51e75e
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Worked logic all the way down to the CPC. If the 8272 announces that it is asleep, it is now no longer clocked. Also very slightly cut down on IRQ line chatter to the Z80.
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2017-08-20 12:05:00 -04:00 |
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Thomas Harte
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85253a5876
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Sought further to reduce the processing footprint of palette changes by updating only those table entries that are affected by a change.
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2017-08-20 10:13:23 -04:00 |
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Thomas Harte
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911ee5a0d3
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At least added a fast return.
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2017-08-19 22:22:51 -04:00 |
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Thomas Harte
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57c5b38a6d
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Step one towards cutting much of this cost: build only the table that's appropriate for the current mode, and at least declare when a more minimal change would be sufficient.
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2017-08-19 22:19:46 -04:00 |
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Thomas Harte
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f68565a33f
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Split the static analyser functionality so that it's possible just to ask for the set of media implied by a particular file. Extended ConfigurationTarget so that media alone can be pushed to a machine.
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2017-08-17 10:48:29 -04:00 |
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Thomas Harte
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b476f06524
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Slowed the typer, having discovered that otherwise it has problems transitioning from a shifted to an unshifted character.
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2017-08-16 22:12:16 -04:00 |
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Thomas Harte
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75208b0762
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Moves the Electron implementation behind a more opaque interface, in line with changes elsewhere.
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2017-08-16 15:33:40 -04:00 |
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Thomas Harte
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903a17ae11
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Corrected typo and removed replication of what's already declared formally.
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2017-08-16 14:53:03 -04:00 |
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Thomas Harte
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3947347d88
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Introduces active input handling for the AY and uses it in the CPC to give proper, active keyboard input, rather than push-on-select, which was only ever a temporary hack. Also maps a few more keys for the Amstrad.
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2017-08-15 22:47:17 -04:00 |
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Thomas Harte
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334872d374
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Clarified, slightly.
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2017-08-14 12:47:11 -04:00 |
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Thomas Harte
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7ea703f150
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Started making provisions for a DMA-compatible implementation. Re: the CPC, it sounds like DMA acknowledge might be permanently wired, causing DMA mode seemingly to work from the 8272's point of view.
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2017-08-14 08:38:00 -04:00 |
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Thomas Harte
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1d8edf58dd
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Ensured that a virtual destructor is declared, so that the various automatically-generated real constructors get in on the action.
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2017-08-11 12:07:48 -04:00 |
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Thomas Harte
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4785e316ff
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Now with exposition.
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2017-08-11 11:36:03 -04:00 |
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Thomas Harte
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44da9de5b0
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Tweaked typing timing expectations.
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2017-08-11 11:35:28 -04:00 |
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Thomas Harte
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570d25214e
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Made an initial attempt at typer support for the CPC.
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2017-08-11 11:21:07 -04:00 |
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Thomas Harte
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cf810d8357
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Minor: ensure the CRT is set to output as a monitor.
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2017-08-10 14:42:47 -04:00 |
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Thomas Harte
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4961fda2a9
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Ensured counter-intuitive CRTC writes get through, taking the opportunity to correct my handling of port IO in general: selecting multiple devices for input results in a logical AND (i.e. open collector mode), and both the CRTC and gate array will receive data from 'input's if applicable.
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2017-08-10 12:39:19 -04:00 |
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Thomas Harte
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6a6e5ae79c
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Forced users of the 6845 to be explicit about which type. So far with no effect.
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2017-08-10 12:28:57 -04:00 |
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Thomas Harte
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484524d781
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Implements RAM paging. The 6128 is now emulated.
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2017-08-08 16:01:56 -04:00 |
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Thomas Harte
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a7103f9333
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Disks are now communicated to the 8272. Which is able to handle four of them.
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2017-08-06 13:24:14 -04:00 |
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Thomas Harte
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29288b690e
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Switched disk controllers to be instantiated explicitly in terms of cycles, created an Amstrad-specific subclass of the 8272 to record the direct programmatic availability of all disk motors bundled together, and otherwise adjusted to ensure the thing is clocked and that the motor is enabled and disabled appropriately. The 8272 is also now formally a subclass of the incoming MDM controller.
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2017-08-06 09:45:16 -04:00 |
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Thomas Harte
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3e984e75b6
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Strung up an empty shell that eventually should contain the 8272, and added appropriate IO decoding to the Amstrad.
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2017-08-05 19:45:52 -04:00 |
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Thomas Harte
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9e8645ca7a
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Fixed ROM paging port decoding. It should have been fd00 if completely decoded, not df00, but also shouldn't be completely decoded.
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2017-08-05 19:24:03 -04:00 |
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Thomas Harte
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caf3ac0645
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Sought: (i) to instruct the CPC that it should be a 664, not a 464, if given a disk image (at least until I have RAM paging implemented for a 6128); (ii) to support ROM selection within the CPC and allow paging in of AMSDOS.
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2017-08-05 19:20:38 -04:00 |
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Thomas Harte
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4b19cf60df
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Added omitted semicolon.
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2017-08-05 09:18:55 -04:00 |
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Thomas Harte
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b3788fed41
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Fixed AY queuing behaviour as handled by the Amstrad. I think I need to come up with clearer semantics here.
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2017-08-05 09:12:17 -04:00 |
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Thomas Harte
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a63aa80dc9
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Merge branch 'master' of github.com:TomHarte/CLK
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2017-08-04 16:51:52 -04:00 |
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Thomas Harte
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63f57c8c4f
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Adjusted visible portion of frame; completely empirical, as I'm chasing a machine that shipped with a monitor.
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2017-08-04 16:51:46 -04:00 |
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Thomas Harte
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f075fea78c
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Introduces filtering of the CRTC's vsync signal into the gate array.
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2017-08-04 16:36:55 -04:00 |
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Thomas Harte
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c0f0c68f4f
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Corrects quick-hack version of border drawing: the assumption that the colour must be the same over a plotted period. Also corrects my entry for colour 15.
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2017-08-04 12:13:05 -04:00 |
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Thomas Harte
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d9097facf1
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Found documentation that makes more sense, and in practice seems to be more correct: the test after vertical sync is for greater than 32, not less. Also I decided to chance my arm on counter reset also resetting interrupt request. The raster effects of Ghouls 'n' Ghosts is now pretty much correct but one line off. I think probably either something is off in my wait-two logic on the post-vsync timer event, or possibly the vsync bit exposed via the PPI doesn't mean exactly what I think it means.
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2017-08-04 08:56:09 -04:00 |
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Thomas Harte
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b927500487
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Clarified code a little, but this is mostly fiddling in the margins.
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2017-08-03 22:00:30 -04:00 |
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Thomas Harte
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e71eabedf9
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Fixed timer clearing tet.
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2017-08-03 21:30:04 -04:00 |
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Thomas Harte
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33ed27c3ad
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Minor tidiness: included missing headers, and spaced out the ROM type and key lists for readability.
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2017-08-03 12:45:42 -04:00 |
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Thomas Harte
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575b1dba75
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Formally declared the ZX80/81 and Amstrad CPC as keyboard machines in their public interface. Which means not having to repeat the meaning of set_key_state and clear_all_keys. So: a minor DRY improvement.
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2017-08-03 12:38:22 -04:00 |
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Thomas Harte
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42e70ef993
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Adjusted slightly as per Z80 change, and to pull everything internally declared into the Amstrad CPC namespace.
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2017-08-02 22:11:03 -04:00 |
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Thomas Harte
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d3bf8fa53b
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Upped the documentation.
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2017-08-02 20:37:26 -04:00 |
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Thomas Harte
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f5e2dd410e
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Constrained output to the centre 90%.
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2017-08-02 19:55:44 -04:00 |
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Thomas Harte
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e50adf1cc8
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Were my TZX support up to it, this would likely be sufficient for tape emulation.
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2017-08-02 13:50:14 -04:00 |
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Thomas Harte
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dcab10f53e
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Ensured the AY's async queue doesn't just fill and fill.
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2017-08-02 07:38:35 -04:00 |
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Thomas Harte
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f602f9b6ec
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Adds an attempt to clock the AY.
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2017-08-02 07:21:33 -04:00 |
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Thomas Harte
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4d5d5041df
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Attempted to ensure a clean startup.
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2017-08-01 22:18:42 -04:00 |
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Thomas Harte
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587eb3a67c
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Factored interrupt counting out of the CRTCBusHandler.
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2017-08-01 22:15:39 -04:00 |
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Thomas Harte
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8d39a20088
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Added proper output of mode 3, were anything ever to try to use it.
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2017-08-01 21:51:41 -04:00 |
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Thomas Harte
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4b6370eb86
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Realised my colour error: mapping the ROM numbers as though they were the hardware numbers. Having fixed that, spotted that I was deserialising R and B the wrong way around and dividing by too much. Colours now appear to be correct.
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2017-08-01 21:47:52 -04:00 |
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Thomas Harte
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c6e340a8a2
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Wired up the vsync signal. Pen 15 no longer flashes like crazy. Still can't figure out why the palette is so askew; was looking for perhaps some sort of detection of a green screen rather than a colour one, but there's no obvious input for that.
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2017-08-01 21:21:59 -04:00 |
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Thomas Harte
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31c7153301
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Corrected bit to colour mapping for modes 0 and 1. The total palette is still way off but there's consistency between modes now.
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2017-08-01 20:52:42 -04:00 |
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Thomas Harte
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7e04d00cc1
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Fixed key values, causing the new set of keys to work, decreased quantity of output and ensured that pixels appear in modes 0 and 2.
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2017-08-01 20:39:10 -04:00 |
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Thomas Harte
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eca9586a0f
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Fixed: input value is no longer overwritten by 0xff. The '0' key now works.
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2017-08-01 20:19:02 -04:00 |
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Thomas Harte
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2e4577f741
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Made a game attempt at implementing a (sticky) keyboard. No effect yet.
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2017-08-01 17:52:05 -04:00 |
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Thomas Harte
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f5b278d683
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Added enough stuff to put the emulated Amstrad CPC in a state of knowing whether its '0' key is pressed.
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2017-08-01 17:31:56 -04:00 |
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Thomas Harte
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e6854ff8db
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Corrected typo: the input to an AY is BDIR, not BCDIR.
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2017-08-01 17:06:57 -04:00 |
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Thomas Harte
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3b292273c7
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Fixed: BC2 is always implicitly set. The machine is now periodically checking the AY's register 14 (i.e. the first input port), so probably there's enough here now to implement keyboard input.
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2017-08-01 17:05:11 -04:00 |
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Thomas Harte
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cb732e5d5f
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Made an attempt to wire in an [unclocked] AY, in an endeavour to get to keyboard reading.
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2017-08-01 17:01:58 -04:00 |
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Thomas Harte
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08ad35efd9
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It's barely an implementation of the 8255, but ensured that data is bounced into the PortHandler, conveniently assuming the interaction mode used by the CPC.
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2017-08-01 16:34:13 -04:00 |
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Thomas Harte
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58b98267fc
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Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.
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2017-08-01 16:15:19 -04:00 |
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Thomas Harte
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a27946102a
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Took a shot at the interrupt counter. Attempts at keyboard reading now recur so it'll probably do for now. I think that next puts me into the realm of needing to implement the 8255.
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2017-08-01 15:49:16 -04:00 |
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Thomas Harte
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6ac7132799
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Had a quick go at properly outputting Mode 1, adding wiring to communicate palette and mode changes to the CRTC bus handler. Colours are off but it's sufficient for now.
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2017-08-01 15:16:13 -04:00 |
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Thomas Harte
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ca42abab70
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Doubled up to ensure that every byte that should be inspected is represented. This makes it clearer that I'm on the right road. A garbled version of 'Amstrad 64k Microcomputer' can be discerned, in a weird grayscale and with the right-hand column missing and skewed output as a result.
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2017-08-01 07:56:44 -04:00 |
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Thomas Harte
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933d69a256
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Fixed slightly: the CPC wiki has a typo. It's 12 and 13 that move up to 14 and 15.
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2017-08-01 07:51:13 -04:00 |
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Thomas Harte
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10a5581aea
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Made first attempt at offering some sort of pictographic of actual RAM contents.
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2017-08-01 07:34:12 -04:00 |
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Thomas Harte
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3ae699964f
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Ensured an actual pixel stream is supplied for pixel regions. Though it's just a long stream of white pixels for now. So visual output is unchanged.
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2017-08-01 07:24:29 -04:00 |
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Thomas Harte
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42dd27c9b1
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Shunted method bodies inline, given that there's no need for a declaration/definition distinction.
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2017-07-31 22:39:25 -04:00 |
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Thomas Harte
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3df13cddd4
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As per my keenness for cleanliness improvements corresponding to my ever-increasing C++ ability: turned the Amstrad into something that a factory produces, allowing me completely to hide a bunch of implementation details.
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2017-07-31 22:32:04 -04:00 |
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Thomas Harte
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c2253c1e0f
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Fixed multiplier: the dot clock I've used to instantiate the CRT is the pixel clock, not the character clock.
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2017-07-31 22:17:46 -04:00 |
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Thomas Harte
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f742fd5d4a
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Made basic attempt to get something on screen: white where the display is enabled, black for the border.
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2017-07-31 22:13:20 -04:00 |
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Thomas Harte
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69b99fe127
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Transferred ownership of the CRT to the CRTC bus handler, to give it easy access.
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2017-07-31 22:04:52 -04:00 |
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Thomas Harte
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e28829bd1b
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Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
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2017-07-31 20:14:46 -04:00 |
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Thomas Harte
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68ceeab610
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Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
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2017-07-31 19:56:59 -04:00 |
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Thomas Harte
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68dca9d047
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Made a first attempt at ROM paging, with pretty much the same scheme that'll be needed for 128kb support.
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2017-07-31 19:37:28 -04:00 |
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Thomas Harte
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d88ca151f4
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Added a first attempt at output port decoding. Just logging for now.
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2017-07-31 19:25:10 -04:00 |
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Thomas Harte
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3c90218c3d
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With a very basic stab at something a bit like the memory map (sans paging), execution begins.
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2017-07-31 19:15:43 -04:00 |
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Thomas Harte
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afd409c883
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Ensured that ROM images are loaded and passed to the Amstrad CPC.
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2017-07-31 18:44:49 -04:00 |
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Thomas Harte
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9c04d851e4
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Added the basics necessary to get the CPU ticking over, at a nominal 4Mhz but with the wait states that I currently believe to be accurate.
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2017-07-31 07:29:50 -04:00 |
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Thomas Harte
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1d6fe11906
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Added an instance of Outputs::CRT::CRT. So progress is now: select CDT, up comes a blank window.
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2017-07-31 07:16:51 -04:00 |
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Thomas Harte
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c0f1313830
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Performed sufficient wiring to get to the point where attempting to load a CDT creates an instance of the Amstrad CPC and then fails only because the thing vends a nullptr CRT.
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2017-07-30 22:05:29 -04:00 |
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