43 Commits

Author	SHA1	Message	Date
Thomas Harte	5d8666b837	Enable the cursor signal; no blink action yet.	2023-12-03 17:57:19 -05:00
Thomas Harte	2b56b7be0d	Simplify namespace syntax.	2023-05-10 16:02:18 -05:00
Thomas Harte	25996ce180	Further doubles down on construction syntax for type conversions.	2020-05-09 23:00:39 -04:00
Thomas Harte	1c154131f9	Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.	2019-10-29 22:36:29 -04:00
Thomas Harte	5d6b5d9f10	Eliminates all emdashes in cross-platform code.	2018-05-13 15:34:31 -04:00
Thomas Harte	0b771ce61a	Removes all instances of the copyright symbol.	2018-05-13 15:19:52 -04:00
Thomas Harte	3944e734d3	Ensures full 6845 instance state initialisation and uses an unsigned shifter.	2017-10-17 22:10:28 -04:00
Thomas Harte	edb9fd301c	Begins this project's conversion to functional-style casts.	2017-10-03 22:04:15 -04:00
Thomas Harte	b30bb2a234	Adds an initial implementation of display skew, as a completely live property.	2017-08-29 22:16:40 -04:00
Thomas Harte	334afbc710	Removes const from get_status and get_register, as both may now logically mutate the object.	2017-08-27 18:13:55 -04:00
Thomas Harte	17c13624e5	Improved comments.	2017-08-27 18:11:40 -04:00
Thomas Harte	113349d272	Started making some formal admissions that different CRTC models exist. Plenty yet to do.	2017-08-27 18:10:07 -04:00
Thomas Harte	bdda701207	Reverts previous unevidenced change.	2017-08-26 22:58:16 -04:00
Thomas Harte	487fe83dca	Ensures that vertical sync and end-of-visible-lines conditions potentially trigger whenever line_counter_ changes, not only when it increments.	2017-08-26 17:54:54 -04:00
Thomas Harte	6c5a03187b	Relocates the HSYNC start test, in order to pass Arnold's cpctest HSYNC start position conformance test.	2017-08-26 17:22:48 -04:00
Thomas Harte	7d7aa2f5d5	Eliminates repetition of the unpacking of register 3 into a horizontal sync count.	2017-08-26 14:37:03 -04:00
Thomas Harte	28550c0227	Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.	2017-08-26 13:56:23 -04:00
Thomas Harte	6e99169348	Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.	2017-08-26 12:59:59 -04:00
Thomas Harte	3caa4705ca	Limits sync counter size.	2017-08-26 12:31:19 -04:00
Thomas Harte	039aed1bd1	Switches the two sync counters to upward-going rather than downward, as a more likely match to the way the rest of the 6845 implementation.	2017-08-25 21:26:01 -04:00
Thomas Harte	a914eadc85	Ensured that register 6 is checked on every loop.	2017-08-22 22:17:45 -04:00
Thomas Harte	e956740c56	Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.	2017-08-22 21:54:48 -04:00
Thomas Harte	55055c7847	Minor: ensured immediate line comparison works. But I think my problem might be trying to do this as straight line logic?	2017-08-14 19:08:20 -04:00
Thomas Harte	a10389a22c	Factored out the stuff of stuffing the bus.	2017-08-14 12:42:22 -04:00
Thomas Harte	a5593bec79	Threw in support for the light-pen trigger.	2017-08-10 15:00:14 -04:00
Thomas Harte	a1e2646301	Imposed counter size limits.	2017-08-10 14:58:24 -04:00
Thomas Harte	6a6e5ae79c	Forced users of the 6845 to be explicit about which type. So far with no effect.	2017-08-10 12:28:57 -04:00
Thomas Harte	02d792c003	Simplified logic slightly, avoiding repetition.	2017-08-10 11:48:37 -04:00
Thomas Harte	be8e7a4144	Eliminated false register aliasing, restricted register sizes and locked out reading and writing where appropriate.	2017-08-10 11:22:30 -04:00
Thomas Harte	a4c910f1de	This appears to be a more accurate take on 6845 address advancement — it is necessary that character output has finished for the line address to be updated.	2017-08-10 11:12:53 -04:00
Thomas Harte	46278ff297	Experimental: is this meant to be a compare-before-increment?	2017-08-07 23:02:29 -04:00
Thomas Harte	26ce6cdab2	Permitted register 3 to dictate vertical sync length.	2017-08-04 08:56:36 -04:00
Thomas Harte	58b98267fc	Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.	2017-08-01 16:15:19 -04:00
Thomas Harte	1d99c116e7	Actually, this is probably more correct: increment and then compare, but increment the refresh address once more after the final character, to avoid repeating it.	2017-08-01 15:29:37 -04:00
Thomas Harte	ee27e16fb1	Switched to post-tests increment. Seems to give proper screen width, but also eliminates that 'compare to +1' step that felt unlikely.	2017-08-01 15:19:25 -04:00
Thomas Harte	3b1db14817	Made a quick attempt at properly updating the refresh address.	2017-08-01 07:36:03 -04:00
Thomas Harte	e3f677fa37	I was under-counting row lines. Adjusted comparison. The emulator now produces a solid white square of approximately correct proportions. I'm sure that filling in pixels will reveal the next set of bugs.	2017-07-31 22:21:46 -04:00
Thomas Harte	5c68b6cc21	Fixed display enable reset when there's no adjustment area. A practical lesson in failure to factor.	2017-07-31 22:16:08 -04:00
Thomas Harte	ffaa627820	Fixed frame restart when there is no adjustment period.	2017-07-31 22:13:45 -04:00
Thomas Harte	5a396f6787	Added an explicit cast.	2017-07-31 22:04:31 -04:00
Thomas Harte	cb0dc7b434	I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.	2017-07-31 22:01:54 -04:00
Thomas Harte	e28829bd1b	Corrected CRTC timing, gave it someone to talk to and a means with which to talk.	2017-07-31 20:14:46 -04:00
Thomas Harte	68ceeab610	Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.	2017-07-31 19:56:59 -04:00