62 Commits

Author	SHA1	Message	Date
Thomas Harte	2720bcdf18	Retrench to static inline const.	2025-09-19 23:40:30 -04:00
Thomas Harte	57a795df96	Add keyboard LEDs.	2025-09-19 23:34:51 -04:00
Thomas Harte	6bdd9e4543	Add drive activity indicators.	2025-09-19 23:26:50 -04:00
Thomas Harte	ff0ba7d48b	Reduce logging again.	2025-09-19 22:59:58 -04:00
Thomas Harte	3916ba1a42	This intermittently succeeds. Doubling down on investigation.	2025-09-19 20:33:02 -04:00
Thomas Harte	0b3d22b97c	Take a swing and a miss at alternative documentation interpretations.	2025-09-19 19:59:12 -04:00
Thomas Harte	9b8b0f2023	Attempt to introduce a DFS ROM and WD1770.	2025-09-19 10:38:22 -04:00
Thomas Harte	239c485f3c	An underclock will do.	2025-09-18 21:35:08 -04:00
Thomas Harte	5e5fdda0ca	Correct audio.	2025-09-18 21:33:25 -04:00
Thomas Harte	4b2dddf3c6	Remove stale TODO.	2025-09-18 21:21:51 -04:00
Thomas Harte	c99ec745ca	Remove dead logging.	2025-09-18 21:20:27 -04:00
Thomas Harte	1ec2e455ec	Support flash, mixed modes.	2025-09-18 21:19:33 -04:00
Thomas Harte	69304737c6	Switch red and blue.	2025-09-18 17:53:58 -04:00
Thomas Harte	fe91670127	Pull count outside loop, simplify state machine.	2025-09-18 17:50:46 -04:00
Thomas Harte	7a59f94f3d	Install more realistic pixel pipeline.	2025-09-18 17:46:09 -04:00
Thomas Harte	4c49ffe3d1	Attmept full ADC implementation.	2025-09-18 12:21:25 -04:00
Thomas Harte	26b1ef247b	Add calls to ADB.	2025-09-17 23:11:48 -04:00
Thomas Harte	3aafba707a	Use more efficient means for blank lines.	2025-09-17 22:33:59 -04:00
Thomas Harte	ff56dd53cf	Remove dead code.	2025-09-17 21:42:33 -04:00
Thomas Harte	888148d282	Reduce chatter.	2025-09-17 21:35:34 -04:00
Thomas Harte	7bba0b82ef	Correct video address generation.	2025-09-17 21:26:13 -04:00
Thomas Harte	a99ed0e557	Add break key.	2025-09-17 17:26:28 -04:00
Thomas Harte	654981fb03	Clean up.	2025-09-17 17:24:08 -04:00
Thomas Harte	25b15fcdd1	Switch to map-based mapping.	2025-09-17 11:34:55 -04:00
Thomas Harte	1106fbb5ef	Implement circular scan.	2025-09-17 10:44:53 -04:00
Thomas Harte	b3c057f911	Increase logging, play about more.	2025-09-16 23:14:05 -04:00
Thomas Harte	1c33e9ead9	Attempt row scanning.	2025-09-16 23:03:25 -04:00
Thomas Harte	d78f35b940	Take a swing at scanning versus not.	2025-09-16 22:29:00 -04:00
Thomas Harte	18b32dbba3	Attempt keyboard input.	2025-09-16 21:51:25 -04:00
Thomas Harte	26e40564dc	Establish keyboard state.	2025-09-16 21:11:27 -04:00
Thomas Harte	b6e8421a0a	Hard-code Mode 0 but hence get some pixels.	2025-09-16 20:57:21 -04:00
Thomas Harte	a1f33d3fc6	Redisable test code.	2025-09-16 17:54:42 -04:00
Thomas Harte	683fea675e	Add ACIA. ... Probably with incorrect clock, and connected to nothing.	2025-09-16 17:50:54 -04:00
Thomas Harte	811a010a60	Fix: keys are now unpressed. ... Some sort of text is now 'output' (though not yet displayed by the emulator) and then an endless loop on the ACIA begins. So the next PR will need to add that.	2025-09-16 17:25:13 -04:00
Thomas Harte	019526332d	Declare no tube, optimistically watch for characters.	2025-09-16 16:25:41 -04:00
Thomas Harte	84d6bb47ea	Log more.	2025-09-16 15:32:42 -04:00
Thomas Harte	512179d92a	Handle clock-rate change correctly in onward signalling.	2025-09-16 13:04:03 -04:00
Thomas Harte	04344a3723	The OS isn't writeable.	2025-09-16 12:47:55 -04:00
Thomas Harte	d032207473	Made some attempt at 1Mhz CRTC clocking.	2025-09-16 12:46:44 -04:00
Thomas Harte	b33dc2779d	Correct RAM visibility.	2025-09-16 12:24:48 -04:00
Thomas Harte	28699a1af5	Correct clock selection bit.	2025-09-16 09:15:08 -04:00
Thomas Harte	ff3fe135a3	Convince myself that this isn't a case of present but invisible content.	2025-09-16 07:36:59 -04:00
Thomas Harte	34330baaa0	Add comment on keyboard.	2025-09-15 23:42:47 -04:00
Thomas Harte	28d8aab7e5	Forward Port A correctly.	2025-09-15 23:36:07 -04:00
Thomas Harte	6a91c89126	Introduce a colour burst.	2025-09-15 23:32:20 -04:00
Thomas Harte	c350f6fe5e	Fix interrupting sync.	2025-09-15 23:28:38 -04:00
Thomas Harte	493bf0a666	Proceed to a solid blank display.	2025-09-15 23:27:04 -04:00
Thomas Harte	0305203e61	Wire up vertical sync interrupt.	2025-09-15 23:21:06 -04:00
Thomas Harte	71d7b1dfad	Add a ticking-but-diconnected CRTC.	2025-09-15 23:16:42 -04:00
Thomas Harte	39c2db38b7	Improve logged IO detail.	2025-09-15 22:29:22 -04:00