1083 Commits

Author	SHA1	Message	Date
Thomas Harte	55af6681af	Avoid unnecessary get_port_input calls.	2021-11-24 17:15:48 -05:00
Thomas Harte	2a7a42ff8f	Add header for assert.	2021-11-24 16:28:18 -05:00
Thomas Harte	0ad1529f3f	Retain delegate bit length for non-self-clocked data.	2021-11-24 16:15:27 -05:00
Thomas Harte	0df8173536	Merge branch 'master' into Amiga	2021-11-24 08:58:03 -05:00
Thomas Harte	f5d3d6bcea	Splits the lowpass filter into push and pull variants.	2021-11-21 15:37:29 -05:00
Thomas Harte	4fc25fb798	Adds basic shift input.	2021-11-07 05:18:54 -08:00
Thomas Harte	941d9a46a2	Makes a better effort at exposition; better implements clocked line.	2021-11-07 05:18:40 -08:00
Thomas Harte	ecfe68d70f	Introduce the principle that a Serial::Line can be two-wire — clock + data.	2021-11-06 16:54:20 -07:00
Thomas Harte	f102d8a4b4	Extend to allow full-[byte/word/dword] writes, in LSB or MSB order.	2021-11-06 12:01:32 -07:00
Thomas Harte	6d34432988	Starts to build in a serial line for input.	2021-11-04 18:54:28 -07:00
Thomas Harte	b827b9e33e	Add necessary shift storage.	2021-11-03 19:26:45 -07:00
Thomas Harte	29e5ecc282	Add TODOs rather than complete stop on shift register acccesses.	2021-11-02 18:19:31 -07:00
Thomas Harte	9ecd43238f	Correct 8520 TOD setting and getting.	2021-10-30 12:02:43 -07:00
Thomas Harte	5ffe71346c	Eliminate interrupt magic constants.	2021-10-29 19:04:06 -07:00
Thomas Harte	d9d20d9d30	Walk back slightly.	2021-10-14 18:02:58 -07:00
Thomas Harte	689bfbbdb3	Be overt in initialiser list.	2021-10-14 16:57:26 -07:00
Thomas Harte	eb157f15f3	Adds index hole interrupt.	2021-10-09 04:08:59 -07:00
Thomas Harte	73e45511dc	Add missing #include.	2021-10-04 05:26:38 -07:00
Thomas Harte	e47eab1d40	Merge branch 'master' into Amiga	2021-09-14 20:27:59 -04:00
Thomas Harte	dfcd1508c9	Establishes valid initial BRAM.	2021-09-10 19:56:20 -04:00
Thomas Harte	0ca4631279	Switch to zero-initialised state; be more careful about resetting data.	2021-09-09 23:08:13 -04:00
Thomas Harte	a6221ca322	Reload data only if an output is found.	2021-09-09 22:07:03 -04:00
Thomas Harte	f8380d2d4c	Add 8250 feature of 'count, regardless'.	2021-08-08 22:32:41 -04:00
Thomas Harte	1f9e41e9cb	Ensure TOD isn't firing from power-on.	2021-08-08 18:51:58 -04:00
Thomas Harte	98bd6fc240	Adds a further logging hint.	2021-08-06 23:16:06 -04:00
Thomas Harte	b9f78f5d33	Fix final timer B test.	2021-08-03 22:27:23 -04:00
Thomas Harte	b4ec9d70da	Adds the CNT input.	2021-08-03 22:19:41 -04:00
Thomas Harte	dd91d793d9	Correct typo.	2021-08-03 21:45:44 -04:00
Thomas Harte	8e51e8eb77	Does just a touch of 6526 TOD work.	2021-08-03 21:13:08 -04:00
Thomas Harte	6210605bc7	Transfers full TOD responsibility onto the chip-specific templates.	2021-08-03 19:10:09 -04:00
Thomas Harte	0245b040b0	Splits TOD storage by model. ... TOD storage will probably end up being a full-on class.	2021-08-03 18:50:58 -04:00
Thomas Harte	8795719c18	This counts reloads, most accurately.	2021-08-03 17:12:08 -04:00
Thomas Harte	6bbbf43341	At least attempts to chain correctly.	2021-08-03 17:03:58 -04:00
Thomas Harte	ee6039bfa5	Writes to a timer _during reload_ now have effect. ... Net: one CIA test passed.	2021-08-03 16:57:05 -04:00
Thomas Harte	ef58ce6277	Gets a bit more rigorous about the clocking stage. ... Albeit without advancing relative to the test.	2021-08-02 21:04:00 -04:00
Thomas Harte	15de5e98c4	Adds [partial] test for whether counters are linked.	2021-08-02 20:17:37 -04:00
Thomas Harte	38848ca2db	Rationalises reload logic and cuts storage. ... Failure point is now chaining, I think.	2021-08-02 20:14:01 -04:00
Thomas Harte	77c627e822	Ensure that reading the interrupt flags really clears the master bit. ... Also makes some guesses on one-shot and reload timing. Alas the test isn't in itself specific enough to be more systematic here.	2021-08-02 07:47:08 -04:00
Thomas Harte	c640132699	Reinstates clocking.	2021-08-01 21:35:08 -04:00
Thomas Harte	57dd38aef2	Reintroduces reload-on-off, adds interrupt delay.	2021-08-01 21:09:02 -04:00
Thomas Harte	460a6cb6fe	Attempts a more literal implementation.	2021-08-01 18:14:10 -04:00
Thomas Harte	3d160ce85f	Add another potential warning.	2021-07-30 18:21:38 -04:00
Thomas Harte	759007ffc1	Attempts to route CIA interrupts.	2021-07-28 19:36:30 -04:00
Thomas Harte	37a55c3a77	Corrects 6526 interrupt control write. ... This seems to imply that the 6526 should be interrupting too.	2021-07-28 19:26:02 -04:00
Thomas Harte	bcb7bb5cce	Improves logging further. ... To investigate the new perpetual loop.	2021-07-26 17:02:30 -04:00
Thomas Harte	34d4420e8c	Correct reading of top byte of counter 2.	2021-07-25 20:41:15 -04:00
Thomas Harte	fcd6b7b0ea	Takes further aim at the conters. ... I think test cases are needed, probably.	2021-07-24 16:06:49 -04:00
Thomas Harte	ceca32ceb3	Takes a guess at one-shot mode.	2021-07-24 15:53:18 -04:00
Thomas Harte	77a8ddb95c	Edges towards working counters.	2021-07-23 22:43:47 -04:00
Thomas Harte	c733a4dbf8	Beefs up interrupt awareness.	2021-07-23 21:58:52 -04:00