6502/CLK
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mirror of https://github.com/TomHarte/CLK.git synced 2026-10-24 18:02:22 +00:00
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14,104 Commits 6 Branches 152 Tags
3d22fe0d1b9aa6d1663217b2eabdf38ecbbc7f03
Commit Graph
1482 Commits
Author SHA1 Message Date
Thomas Harte 3d22fe0d1b Attempt FIRQ, IRQ and NMI responses. 2026-03-17 11:35:41 -04:00
Thomas Harte 1f6f103346 Implement HALT. 2026-03-17 11:17:40 -04:00
Thomas Harte 14ed0e0ec7 Implement RESET. 2026-03-17 00:06:58 -04:00
Thomas Harte fbb24e04e0 Generalise extended addressing; get as much as possible from tests. 2026-03-16 23:58:41 -04:00
Thomas Harte 5e07672fa4 Start testing and simplify indexed address decoder. 2026-03-16 18:27:50 -04:00
Thomas Harte 873f10a0d8 Disambiguate PostincrementBy1 and Offset8bit. 2026-03-16 18:09:49 -04:00
Thomas Harte 948e49312b Attempt MRDY version of write. 2026-03-16 17:49:45 -04:00
Thomas Harte d787af89c5 Write ADDD result back. 2026-03-16 15:03:48 -04:00
Thomas Harte d4f89888c9 Fix ADC flags. 2026-03-16 14:48:23 -04:00
Thomas Harte 69823ac117 Correct various subtraction flags. 2026-03-16 14:43:11 -04:00
Thomas Harte da2f9aab1c Fix MUL flags. 2026-03-16 14:30:14 -04:00
Thomas Harte 38b00373c2 LEA operates differently than LD with regard to flags. 2026-03-16 12:28:11 -04:00
Thomas Harte 216d947e64 Add assert, continue filtering test set for sanity. 2026-03-16 12:13:09 -04:00
Thomas Harte 4aad105c54 Limit CC testing where helpful. 2026-03-16 11:29:02 -04:00
Thomas Harte e1b5c5b8da Ensure low DAA addition rolls over into high. 2026-03-16 11:18:37 -04:00
Thomas Harte 299d6bc562 Fix LBSR test. 2026-03-16 11:04:47 -04:00
Thomas Harte 84b5292f0a Don't let a JMP target set flags. 2026-03-16 11:00:22 -04:00
Thomas Harte ec1595a55c Fix LSL overflow. 2026-03-16 10:56:26 -04:00
Thomas Harte fb17692826 Test everything except illegal opcodes. 2026-03-16 10:49:20 -04:00
Thomas Harte 7c3211a835 Correct carry after NEG. 2026-03-16 10:40:06 -04:00
Thomas Harte 3d911e3439 Attempt to use precomputed test case. 2026-03-16 10:37:16 -04:00
Thomas Harte a0198b6f41 Implement RTI. 2026-03-15 23:01:22 -04:00
Thomas Harte bbaa7d74d4 Implement push, fix post-increment by 1. 2026-03-15 22:46:05 -04:00
Thomas Harte ff58307b2b Avoid accidental increment and decrements in 5-bit offset mode. 2026-03-15 21:04:04 -04:00
Thomas Harte 34751ba04c Lock in pre- versus post- behaviour. 2026-03-15 13:41:23 -04:00
Thomas Harte 5c39a924d7 Implement SWI. Making me suspect an error in indexed decrementing. 2026-03-15 13:03:17 -04:00
Thomas Harte aec2a1b65a Implement BSR and LBSR. 2026-03-15 12:46:26 -04:00
Thomas Harte cefd67be57 Correct JMP, implement extended indirect addressing. 2026-03-15 12:40:54 -04:00
Thomas Harte a5268c4372 Take a shot at RTS. 2026-03-15 00:00:12 -04:00
Thomas Harte 91d844dba0 Correct written values, JSR. 2026-03-14 23:54:43 -04:00
Thomas Harte df9ff6085c Introduce category for irregular operations; implement PUL. 2026-03-14 23:36:18 -04:00
Thomas Harte 91a9c90f9c Fix immediate 8 -> 16 mapping step. 2026-03-14 16:33:28 -04:00
Thomas Harte 4dc330e0f2 Add further debugging aids. 2026-03-14 12:50:03 -04:00
Thomas Harte 59ff1a5731 Swallow an extra dynamic dispatch for clarity. 2026-03-14 12:24:21 -04:00
Thomas Harte cd9fcd667d Implement enough 6809 to go off the rails. 2026-03-14 12:06:50 -04:00
Thomas Harte d82abaeeb3 Expand definition to include operand size. 2026-03-14 11:50:05 -04:00
Thomas Harte 1df4c1cf1d Attempt a rush through direct and extended addressing. 
... realising that I've omitted operand size as another complicating factor.
 2026-03-14 11:37:28 -04:00
Thomas Harte cfb77d26ce Correct FormSuffixs, check for indirection. 2026-03-13 17:55:47 -04:00
Thomas Harte ae353fb366 Start to capture indexed addressing logic. 2026-03-13 14:24:42 -04:00
Thomas Harte d15fbe91bb Implements SUBs and CMPs. 2026-03-12 23:09:49 -04:00
Thomas Harte 8a95da16e2 Implement DAA, ST, ROL/ROR. 2026-03-12 22:53:22 -04:00
Thomas Harte fe00e76d23 Add NEG, COM. 2026-03-12 22:34:22 -04:00
Thomas Harte b35b1b7dca Expand bitwise, basic arithmetic. 2026-03-12 22:26:16 -04:00
Thomas Harte 1b7fa8b053 Make sense of the task ahead. 2026-03-12 15:30:18 -04:00
Thomas Harte f242aacf05 Implement BIT, CLR and NOP. 2026-03-12 15:22:12 -04:00
Thomas Harte 70a4860f04 Implement MUL. 2026-03-11 21:47:21 -04:00
Thomas Harte 3704f008c6 Implement branching logic. 
I'm still sweeping timing under the rug for now.
 2026-03-11 17:26:22 -04:00
Thomas Harte 61bf62005c Implement shifts. 2026-03-11 15:45:00 -04:00
Thomas Harte a9358d3039 Start to flesh out operations. 2026-03-11 15:09:46 -04:00
Thomas Harte 21d2ab9179 Flesh out condition codes. 2026-03-11 10:06:05 -04:00