 Thomas Harte
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8a765031e1
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Make access a 6809 norm; expose MO6 to SDL users.
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2026-04-12 19:02:55 -04:00 |
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Thomas Harte
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2f68d38879
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Rationalise JMP as an LEA.
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2026-04-12 08:59:40 -04:00 |
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Thomas Harte
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116ed6f497
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Correct LEAx length, and hence normalise CD90-640 disk RPM.
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2026-04-06 14:32:59 -04:00 |
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Thomas Harte
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ba042610af
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Add missing header, adjust LEAx timing.
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2026-04-06 12:24:48 -04:00 |
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Thomas Harte
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609b2ac7d1
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Implement get analogue of set.
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2026-03-27 14:29:50 -04:00 |
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Thomas Harte
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46a3dd41a7
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Further reduce repetition, and hence chance of error.
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2026-03-26 09:57:47 -04:00 |
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Thomas Harte
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f9c7278e9e
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Add LICs to indexed addressing.
All tests now passing.
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2026-03-26 09:46:38 -04:00 |
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Thomas Harte
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cc52f9a3d8
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Fix JMP and JSR, and test expectations of SYNC and CWAI.
38 failures left, all in indexed addressing.
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2026-03-26 09:36:30 -04:00 |
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Thomas Harte
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283999fbf5
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Add LIC to immediate16.
54 failures.
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2026-03-26 09:22:02 -04:00 |
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Thomas Harte
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83612bf193
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Differentiate "zero-cost" (i.e. no internal cycles) operations.
64 failures outstanding.
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2026-03-26 09:16:19 -04:00 |
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Thomas Harte
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311f2eb74c
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Add TODO on pending issue, as reminder for tomorrow.
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2026-03-25 21:55:26 -04:00 |
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Thomas Harte
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c699b8899a
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Fix modifies. 254 failures.
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2026-03-25 21:52:26 -04:00 |
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Thomas Harte
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f1146f3c41
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Signal LIC during PSH. 290 failures remaining.
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2026-03-25 21:42:50 -04:00 |
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Thomas Harte
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edba0d94eb
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Reduce 446 failures to 296.
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2026-03-25 21:35:06 -04:00 |
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Thomas Harte
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9a527b1025
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Test, widely fail LIC tests.
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2026-03-25 21:19:56 -04:00 |
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Thomas Harte
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b140323ebf
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Add LIC to template parameters; incorrectly valued at present.
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2026-03-25 21:03:30 -04:00 |
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Thomas Harte
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7b8b2fc0cb
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Extend definition of LIC.
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2026-03-25 17:39:29 -04:00 |
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Thomas Harte
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05a85b6ba9
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Resolve various compiler warnings: primarily ~'s promotion to int.
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2026-03-25 13:57:32 -04:00 |
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Thomas Harte
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372893a05a
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Add support for passive NOP observation.
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2026-03-25 09:44:15 -04:00 |
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Thomas Harte
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8926a669a8
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Make duration freestanding, to guarantee its constant.
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2026-03-23 12:42:42 -04:00 |
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Thomas Harte
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94552d7dee
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Lock in exception vector.
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2026-03-22 18:14:37 -04:00 |
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Thomas Harte
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258afa077f
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Further simplify expression of conditions.
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2026-03-21 11:29:08 -04:00 |
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Thomas Harte
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957fbcfa64
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Post interrupt acknowledge on vector fetches.
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2026-03-21 10:37:50 -04:00 |
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Thomas Harte
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0b1ca94aa5
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After an extra cycle of thought, RTI is like the tail of RTS.
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2026-03-21 10:24:10 -04:00 |
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Thomas Harte
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b88269a937
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Regularise condition order.
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2026-03-21 10:23:13 -04:00 |
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Thomas Harte
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2a1d9bc8e4
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Try: storage is in control register, but is not writeable.
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2026-03-20 16:41:03 -04:00 |
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Thomas Harte
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3913a2c9d3
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Switch comprehension of what combines to make IRQA and B.
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2026-03-20 14:45:56 -04:00 |
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Thomas Harte
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ed481cce90
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Ensure all macros are undefined.
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2026-03-19 18:23:24 -04:00 |
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Thomas Harte
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4f24bee12b
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Make fallthroughs explicit.
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2026-03-19 12:32:01 -04:00 |
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Thomas Harte
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b925783251
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Round out indexed address calculation tests.
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2026-03-19 10:00:01 -04:00 |
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Thomas Harte
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1a385810f7
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Test interrupt timing.
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2026-03-18 23:50:07 -04:00 |
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Thomas Harte
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ab070e3bee
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Test/correct CWAI and SYNC.
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2026-03-18 23:24:23 -04:00 |
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Thomas Harte
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76eb696baa
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Test and correct SWI[2/3] and RESET.
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2026-03-18 23:07:02 -04:00 |
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Thomas Harte
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6481f50c53
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Test and correct RTS and RTI.
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2026-03-18 22:46:34 -04:00 |
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Thomas Harte
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990a90928f
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Test various inherents that don't touch the stack.
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2026-03-18 22:28:39 -04:00 |
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Thomas Harte
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6e08bd7aa3
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Test, fix BSRs.
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2026-03-18 17:39:54 -04:00 |
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Thomas Harte
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333c50f5b1
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Test and correct branches.
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2026-03-18 17:35:55 -04:00 |
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Thomas Harte
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0c55aa53e9
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Extended tests and corrections as far as JSR.
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2026-03-18 17:16:55 -04:00 |
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Thomas Harte
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0ec7aa3280
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Test pushes and pulls.
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2026-03-18 11:57:17 -04:00 |
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Thomas Harte
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2489129e97
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Test and verify first piece of timing: EXG.
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2026-03-18 11:40:07 -04:00 |
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Thomas Harte
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6487e10e22
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Fill in extension counts.
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2026-03-18 11:31:09 -04:00 |
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Thomas Harte
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814b50ccbf
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Start to introduce costed performances.
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2026-03-18 11:11:30 -04:00 |
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Thomas Harte
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3c6ba3ae9f
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Implement CWAI.
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2026-03-17 17:58:41 -04:00 |
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Thomas Harte
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f90910ea63
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Implement SYNC.
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2026-03-17 12:19:29 -04:00 |
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Thomas Harte
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3d22fe0d1b
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Attempt FIRQ, IRQ and NMI responses.
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2026-03-17 11:35:41 -04:00 |
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Thomas Harte
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1f6f103346
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Implement HALT.
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2026-03-17 11:17:40 -04:00 |
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Thomas Harte
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14ed0e0ec7
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Implement RESET.
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2026-03-17 00:06:58 -04:00 |
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Thomas Harte
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fbb24e04e0
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Generalise extended addressing; get as much as possible from tests.
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2026-03-16 23:58:41 -04:00 |
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Thomas Harte
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5e07672fa4
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Start testing and simplify indexed address decoder.
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2026-03-16 18:27:50 -04:00 |
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Thomas Harte
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873f10a0d8
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Disambiguate PostincrementBy1 and Offset8bit.
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2026-03-16 18:09:49 -04:00 |
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