Thomas Harte
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6a93d2d006
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Corrects some minor spaces-instead-of-tabs errors.
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2019-01-24 22:59:03 -05:00 |
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Thomas Harte
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ee89be6730
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Removes many stray spaces.
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2018-11-23 22:32:32 -05:00 |
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Thomas Harte
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a8645f80bf
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Introduces 'non-exclusive' emulator-space keyboards.
i.e. sets of keys that don't amount to an entire keyboard in the modern sense. Experimentally used by the Master System for its reset key.
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2018-10-24 21:59:30 -04:00 |
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Thomas Harte
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c07f9fed99
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Corrects test and implementation to pass the exhaustive VDP interrupt prediction test.
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2018-10-21 18:42:49 -04:00 |
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Thomas Harte
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616777517d
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Makes the failing test more communicative, in the hope of more easily debugging errors.
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2018-10-21 14:35:44 -04:00 |
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Thomas Harte
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b3f1677da5
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Introduces new failing test for rational continuous interrupt prediction.
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2018-10-21 13:59:14 -04:00 |
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Thomas Harte
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725b364bbc
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Improves testing; now tests for time to the first interrupt.
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2018-10-20 18:25:55 -04:00 |
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Thomas Harte
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acdc84e08c
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Improves test slightly, and fixes line interrupt reload value setting.
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2018-10-09 22:14:35 -04:00 |
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Thomas Harte
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c128ddb549
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Introduces a first unit test for line interrupts and corrects backup behaviour.
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2018-10-09 21:49:21 -04:00 |
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Thomas Harte
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fc84ae611e
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Resolves various instances of spaces in place of tabs.
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2018-09-09 20:33:56 -04:00 |
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Thomas Harte
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ddf45a0010
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Ensures NMI and RST reset D on 65C02s.
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2018-08-14 19:49:14 -04:00 |
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Thomas Harte
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261fb3d4f8
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Implements proper test for ADC/SBC 65C02 NZ, though not yet the proper timing.
This gets Klaus Dorman's test to pass.
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2018-08-10 22:42:35 -04:00 |
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Thomas Harte
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b63e0cff72
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Improves has-completed test.
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2018-08-10 22:27:01 -04:00 |
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Thomas Harte
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5d6e479338
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Implements RMB and SMB, and fixes SBC (zero).
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2018-08-10 22:13:51 -04:00 |
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Thomas Harte
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90094529a5
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Implements TSB and TRB, and adds the extra BIT instructions.
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2018-08-10 22:04:45 -04:00 |
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Thomas Harte
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aed4c0539e
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Implements STZ.
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2018-08-10 21:17:02 -04:00 |
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Thomas Harte
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95164b79c9
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Attempted implementation of (zp) addressing mode.
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2018-08-09 21:51:14 -04:00 |
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Thomas Harte
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bb680b40d8
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Implements the 65C02's JMPs.
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2018-08-08 22:26:57 -04:00 |
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Thomas Harte
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e3f6da6994
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Implements the 65C02 NOPs.
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2018-08-08 20:00:14 -04:00 |
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Thomas Harte
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32338bea4d
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Implements BRA.
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2018-08-06 22:37:30 -04:00 |
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Thomas Harte
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1a44ef0469
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Introduces Klaus Dorman's 65C02 tests. All failing.
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2018-08-06 21:48:43 -04:00 |
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Thomas Harte
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ebce9a2e51
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Fixes test target.
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2018-08-06 21:15:13 -04:00 |
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Thomas Harte
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abca38a548
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Makes an initial removal of PCMPatchedTrack. Farewell, old friend.
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2018-07-01 22:49:57 -04:00 |
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Thomas Harte
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853261364e
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Generalised CRC generation and created specific subclasses for the CCITT CRC16 and CRC32.
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2018-05-23 22:21:57 -04:00 |
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Thomas Harte
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0b771ce61a
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Removes all instances of the copyright symbol.
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2018-05-13 15:19:52 -04:00 |
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Thomas Harte
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05e31d7594
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Mutates testComplicatedTrackSeek into an actual test.
Which frustratingly passes.
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2018-05-01 19:52:12 -04:00 |
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Thomas Harte
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f4097290c2
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Made various corrections following a quick for-loop constness audit.
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2018-04-30 22:23:57 -04:00 |
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Thomas Harte
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b32538f3c8
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Adds an additional test.
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2018-04-30 22:05:44 -04:00 |
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Thomas Harte
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e7618bb32e
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Corrects types (/chickens out).
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2018-04-30 22:04:05 -04:00 |
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Thomas Harte
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e599e65087
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Switches to use of the TargetList typedef wherever possible.
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2018-04-14 19:46:38 -04:00 |
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Thomas Harte
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389979923e
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Performs update to and satisfaction of Xcode 9.3's preferred warnings.
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2018-03-30 10:25:01 -04:00 |
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Thomas Harte
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f0f9d5a6af
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Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour.
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2018-03-08 20:30:22 -05:00 |
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Thomas Harte
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fdef914137
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Corrects test target regression.
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2018-03-06 18:32:21 -05:00 |
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Thomas Harte
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66faed4008
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Gives MachineForTargets complete responsibility for initial machine state.
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2018-01-25 18:28:19 -05:00 |
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Thomas Harte
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21efb32b6f
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Integrates the static and nascent dynamic analyser namespaces.
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2018-01-24 21:48:44 -05:00 |
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Thomas Harte
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ed564cb810
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Implements the main four cartridge banking schemes.
Slightly proof of concept for now.
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2018-01-04 22:18:18 -05:00 |
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Thomas Harte
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c8367a017f
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Cleans up test and makes attempt to factor in cartridge type popularity.
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2018-01-01 21:21:05 -05:00 |
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Thomas Harte
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344a12566b
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Tweaks a couple of expected cartridge types.
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2018-01-01 20:14:56 -05:00 |
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Thomas Harte
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c07113ea95
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Ensures no illegal accesses while testing MSX ROM type detection.
Specifically: the static analyser doesn't even correctly identify everything that is an MSX ROM yet, let alone then properly determine type.
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2018-01-01 17:38:26 -05:00 |
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Thomas Harte
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bc2879c412
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Corrects the MSX ROM unit test.
I.e. the test is correct now, for those SHAs I could find. The static analyser is still wrong just slightly less than half the time.
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2018-01-01 17:35:13 -05:00 |
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Thomas Harte
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db25b4554b
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Introduces failing tests of the MSX static analyser.
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2018-01-01 16:38:26 -05:00 |
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Thomas Harte
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05b95ea2e0
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Corrects Xcode tests.
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2018-01-01 16:04:13 -05:00 |
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Thomas Harte
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6e1d69581c
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Eliminates a variety of end-of-line spaces.
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2017-11-07 22:54:22 -05:00 |
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Thomas Harte
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f95515ae81
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Eliminates a large number of instance of end-of-line tabs.
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2017-11-07 22:51:06 -05:00 |
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Thomas Harte
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064f1dfdbc
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Removes usages of deprecated initialiser.
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2017-10-05 18:10:47 -04:00 |
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Thomas Harte
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ff24e1de31
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Corrects 6522 bridge per has-a-not-is-a template switch.
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2017-09-04 21:56:21 -04:00 |
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Thomas Harte
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7af3de010e
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Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
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2017-08-23 22:25:31 -04:00 |
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Thomas Harte
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ee71be0e7e
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Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
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2017-08-21 21:56:42 -04:00 |
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Thomas Harte
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761afad118
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Corrected timestamp return, and its testing by the 6502 timing tests.
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2017-07-27 21:19:16 -04:00 |
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Thomas Harte
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37950143fc
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Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
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2017-07-27 20:17:13 -04:00 |
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