Thomas Harte
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610c85a354
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Correct test logic.
All tests now pass.
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2021-11-25 04:11:20 -05:00 |
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Thomas Harte
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012084b37b
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Fix exclusive fill, sizing, eliminate ECS call-ins.
The clock test now proceeds further, but still doesn't seem to pass.
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2021-11-24 17:25:32 -05:00 |
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Thomas Harte
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8ef9a932aa
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Adds inclusive fill test; fixes inclusive fills.
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2021-11-07 14:26:13 -08:00 |
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Thomas Harte
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2c1f2edcf2
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Introduce failing 'clock' test case.
i.e. a few seconds of the Workbench 1.0 clock application.
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2021-10-31 16:12:51 -07:00 |
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Thomas Harte
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9e6ffaad7d
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Introduce test case for fill mode.
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2021-10-31 14:12:26 -07:00 |
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Thomas Harte
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edb75e69cb
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Implement bitplane modulos.
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2021-10-29 11:29:22 -07:00 |
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Thomas Harte
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5ebc59dd1f
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Introduce additional test cases.
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2021-10-26 20:58:38 -07:00 |
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Thomas Harte
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4d7ce3792f
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Use additional test cases.
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2021-10-25 21:48:43 -07:00 |
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Thomas Harte
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dc8701a929
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Introduce some additional Blitter test cases.
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2021-10-25 21:40:20 -07:00 |
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Thomas Harte
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15ed4a0d09
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Introduce failing test case for sector decoding.
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2021-10-16 10:48:32 -07:00 |
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Thomas Harte
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aa6b0f07b7
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Correct filename.
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2021-10-16 05:37:46 -07:00 |
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Thomas Harte
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6b0dd19442
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Name file appropriately: the logo comes from Kickstart.
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2021-10-09 08:02:15 -07:00 |
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Thomas Harte
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da286d5ae8
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Switch spaces to tabs.
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2021-10-04 05:27:25 -07:00 |
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Thomas Harte
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ad90c6b6ce
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Now that this is getting close, don't stop at the first error.
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2021-09-29 22:19:34 -04:00 |
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Thomas Harte
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0c998d60cb
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Correct test logic for line draws that repeatedly write to the same address.
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2021-09-28 21:45:55 -04:00 |
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Thomas Harte
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1dfc36f311
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Flip loop, add modulo mappings.
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2021-09-26 18:15:32 -04:00 |
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Thomas Harte
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1c03ff1d37
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Fix bltdptl to bltbptl misstatement; remove pre-DMA writes.
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2021-09-26 18:14:50 -04:00 |
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Thomas Harte
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19dd2f92bd
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Implements test case. Failing at present, naturally.
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2021-09-25 21:52:41 -04:00 |
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Thomas Harte
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acfaa016a0
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Adds a capture of traffic leading up to the Workbench boot logo.
Around which to construct a test case.
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2021-09-25 18:10:07 -04:00 |
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Thomas Harte
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fa800bb809
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Introduces code for minterm application.
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2021-09-20 19:13:23 -04:00 |
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Thomas Harte
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e402e690b0
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Assume and test that divide-by-zero posts the PC of the offending instruction.
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2021-08-07 17:51:00 -04:00 |
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Thomas Harte
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b4ec9d70da
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Adds the CNT input.
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2021-08-03 22:19:41 -04:00 |
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Thomas Harte
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738999a8b7
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Further expands list of applied tests.
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2021-08-03 22:08:50 -04:00 |
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Thomas Harte
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34c1cc5693
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Adds entry points for all remaining tests.
Failing now: the TB123s, which are TOD related, both CIA2 tests, and CIA1TAB (which I think needs me to implement Port B output toggling).
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2021-08-03 17:19:35 -04:00 |
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Thomas Harte
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f0ef45f0ca
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Introduces two further tests.
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2021-08-03 16:58:51 -04:00 |
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Thomas Harte
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f576baf214
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I'm not yet sure this is the best approach, but starts trying to make use of Lorenz's 6526 tests.
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2021-07-30 21:21:16 -04:00 |
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Thomas Harte
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94907b51aa
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Remove redundant parameter.
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2021-07-06 20:47:49 -04:00 |
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Thomas Harte
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0085265d13
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Test for a longer period; fix expected tone 1 count.
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2021-07-06 20:46:22 -04:00 |
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Thomas Harte
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8e0893bd42
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Clarifies control flow.
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2021-07-06 20:28:32 -04:00 |
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Thomas Harte
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704dc9bdcb
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Improves test, to assert that state toggles happen at interrupts.
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2021-07-06 20:25:32 -04:00 |
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Thomas Harte
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3e6b804896
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Switches to linked 1/50/1000 Hz timers, and per-interrupt state toggling.
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2021-07-06 20:12:44 -04:00 |
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Thomas Harte
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f371221dba
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Add a quick test of tone generator 1.
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2021-07-02 23:57:11 -04:00 |
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Thomas Harte
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27b0579ec6
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Avoid stack-error test case.
Also test that the interrupt is generated on the downward stroke.
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2021-07-02 23:55:43 -04:00 |
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Thomas Harte
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283092cfbc
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With a unit test in aid, corrects some lingering TimedInterruptSource issues.
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2021-07-02 23:41:19 -04:00 |
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Thomas Harte
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fbf1adef05
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Introduces unit test and thereby seemingly fixes get_next_sequence_point.
There's still improper output in the actual machine though, so maybe something else is afoot?
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2021-06-18 17:44:17 -04:00 |
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Thomas Harte
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f27e331462
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Updates autotests to new RomFetcher world.
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2021-06-06 20:34:55 -04:00 |
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Thomas Harte
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37dcf61130
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Add timing tests, fix +3 discrepancy.
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2021-04-23 22:29:57 -04:00 |
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Thomas Harte
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a1511f9600
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Establishes that the 48/128kb contention patterns can be derived from my partial machine cycles alone.
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2021-04-14 20:15:40 -04:00 |
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Thomas Harte
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68a04f4e6a
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Adds IN/OUT I/D [R] to complete tests.
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2021-04-13 22:00:24 -04:00 |
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Thomas Harte
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0d61902b10
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Adds CP[I/D/IR/DR] tests.
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2021-04-13 20:03:11 -04:00 |
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Thomas Harte
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3eec210b30
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Adds LDI/LDD/LDIR/LDDR tests.
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2021-04-13 20:00:29 -04:00 |
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Thomas Harte
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2e70b5eb9f
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Advances to EX (SP), HL, leaving only [LD/CP/IN/OT][I/D]{R}.
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2021-04-13 19:45:29 -04:00 |
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Thomas Harte
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8a3bfb8672
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Adds an IN/OUT test.
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2021-04-13 17:55:51 -04:00 |
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Thomas Harte
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06f1e64177
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Advances to IO.
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2021-04-12 21:41:20 -04:00 |
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Thomas Harte
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b42780173a
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Establishes that there really is no Read4 and Read4Pre distinction.
Will finish these unit tests, then clean up.
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2021-04-12 20:54:10 -04:00 |
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Thomas Harte
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36c8821c4c
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Reaches the halfway point in tests.
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2021-04-12 17:29:03 -04:00 |
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Thomas Harte
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9347fe5f44
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Advances to next failing test: LD (ii+n), n.
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2021-04-12 17:11:58 -04:00 |
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Thomas Harte
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e82367def3
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Switches to test-conformant behaviour for (IX/IY+n) opcode fetches.
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2021-04-11 23:01:00 -04:00 |
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Thomas Harte
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47c5a243aa
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Restructures, the better to explore errors.
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2021-04-10 21:32:42 -04:00 |
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Thomas Harte
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070e359d82
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Introduces failing test for BIT b, (ii+n).
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2021-04-10 18:00:23 -04:00 |
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