6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 08:49:37 +00:00
Code Issues Projects Releases Wiki Activity
9,733 Commits 8 Branches 121 Tags 496 MiB
83b9fc3318
Commit Graph

9733 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Thomas Harte
94231ca3e3 Put word-sizing responsibility on the caller. 2022-08-10 16:41:45 -04:00
Thomas Harte
e2a8b26b57 Display properly from greater RAM sizes. 2022-08-10 16:36:11 -04:00
Thomas Harte
b6f45d9a90 Fix struct/class confusion. 2022-08-10 15:40:46 -04:00
Thomas Harte
69f92963f9 Add Atari ST RAM size to Qt UI. 2022-08-10 15:39:55 -04:00
Thomas Harte
6b001e3106 Add ST RAM size selection to the macOS UI. 2022-08-10 14:58:19 -04:00
Thomas Harte
6d1c954623 Make ST RAM size selectable, default to 1MB. 2022-08-10 12:00:06 -04:00
Thomas Harte
bdb35b6191 Add an easier hook for debugging. 2022-08-08 21:00:28 -04:00
Thomas Harte
892580c183 Clarify test. 2022-08-08 15:57:36 -04:00
Thomas Harte
4c90a4ec93 Remove 'Faulty peek' JSON breakages. 2022-08-08 15:22:18 -04:00
Thomas Harte
f58f7102f7 Provide more context when JSON decoding fails. 2022-08-08 15:18:03 -04:00
Thomas Harte
adf3405e6b Be overt about performance side effect. 2022-08-08 15:17:04 -04:00
Thomas Harte
8d34d9a06a Add missing paramter. 2022-08-08 11:01:07 -04:00
Thomas Harte
0d540fd211 Merge branch 'SerialisedBlitter' of github.com:TomHarte/CLK into SerialisedBlitter 2022-08-08 10:59:50 -04:00
Thomas Harte
025c79ca65 Factor out GZip shenanigans. 2022-08-08 10:52:55 -04:00
Thomas Harte
868d179132 Compress all Blitter logs. 2022-08-07 21:55:33 -04:00
Thomas Harte
cfccfd48e5 Allow for GZipped tests. 2022-08-07 21:53:19 -04:00
Thomas Harte
2f3dfdcc67 Add Spindizzy test. 2022-08-07 21:27:11 -04:00
Thomas Harte
d4b7d73fc4 Further reduces lines to one access per slot, max. 2022-08-07 19:19:00 -04:00
Thomas Harte
867769f6e7 Reduces line drawing to two accesses per slot. 
Still a fiction, but a better one.
 2022-08-07 19:15:03 -04:00
Thomas Harte
7f423e39ed Resolve type warning. 2022-08-07 19:03:56 -04:00
Thomas Harte
e6505dc985 Recognise that some of these traces don't capture all bus transactions. 2022-08-07 19:03:14 -04:00
Thomas Harte
bcdb2d135d Remove partially-captured head. 2022-08-06 22:35:18 -04:00
Thomas Harte
c5d1cffad2 Include bus activity. 2022-08-06 22:21:02 -04:00
Thomas Harte
54b4a0771d Provide better exposition. 2022-08-06 21:52:26 -04:00
Thomas Harte
85f75ab1f3 Introduce Addams Family test case. 2022-08-06 21:47:36 -04:00
Thomas Harte
668332f6c7 Any one failure will do. 2022-08-06 14:59:13 -04:00
Thomas Harte
021ddb3565 Ensure pipeline is fully flushed before registers are accessed. 2022-08-06 14:55:31 -04:00
Thomas Harte
6981bc8a82 Add yet more context. 2022-08-06 14:47:24 -04:00
Thomas Harte
7030646671 Avoid infinite loop. 2022-08-06 14:42:09 -04:00
Thomas Harte
3781b5eb0e Provide further context. 2022-08-06 14:40:12 -04:00
Thomas Harte
e897cd99f9 Fix transcription of write. 2022-08-06 10:11:26 -04:00
Thomas Harte
cc9b6bbc61 Stop after a first mismatch. 2022-08-06 10:10:19 -04:00
Thomas Harte
318cea4ccd Attempt a full bus-transaction comparison. 2022-08-06 10:06:49 -04:00
Thomas Harte
45892f3584 Add optional transaction records to the Blitter. 2022-08-06 09:51:20 -04:00
Thomas Harte
612413cb1c Remove redundant state. 2022-08-04 10:06:14 -04:00
Thomas Harte
511ec5a736 Apply modulos at end of final line. 
Possibly I need to rethink the sequence logic?
 2022-07-30 21:35:26 -04:00
Thomas Harte
4fb9dec381 Fix use of bool. 2022-07-30 21:02:44 -04:00
Thomas Harte
82476bdabe Avoid 'complete' repetition. 2022-07-30 21:02:04 -04:00
Thomas Harte
58ee8e2460 Minor tidy-up. No fixes. 2022-07-30 21:00:50 -04:00
Thomas Harte
94a90b7a89 Attempt a real slot-by-slot blit. 2022-07-30 20:34:37 -04:00
Thomas Harte
5d992758f8 Ensure blitter with all flags disabled terminates. 2022-07-30 20:13:37 -04:00
Thomas Harte
27b8c29096 Apply modulos at end of line, not beginning. 2022-07-30 10:27:53 -04:00
Thomas Harte
93d2a612ee Add an explicit flush-pipeline step; some tests now pass. 2022-07-29 16:33:46 -04:00
Thomas Harte
03d4960a03 Begin a full-synchronous usage of the sequencer, at least exposing poor handling of the pipeline. 2022-07-29 16:15:18 -04:00
Thomas Harte
1ac0a4e924 Provide a loop count directly from the sequencer. 
This avoids the caller having to take a guess at iterations.
 2022-07-29 12:14:59 -04:00
Thomas Harte
d85d70a133 Add documentation, formal begin function. 2022-07-26 22:01:43 -04:00
Thomas Harte
76979c8059 Add missing tests. 2022-07-26 21:47:02 -04:00
Thomas Harte
86246e4f45 Introduce partial Blitter sequencer test. 2022-07-26 21:28:12 -04:00
Thomas Harte
2c95dea4db Introduce putative blitter sequencer. 2022-07-26 17:05:05 -04:00
Thomas Harte
804c12034c Apply blitter priority bit. 2022-07-26 16:07:26 -04:00