 Thomas Harte
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088bc14b11
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Begin a reformatting of components.
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2024-11-29 22:43:54 -05:00 |
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Thomas Harte
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a3d37640aa
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Switch include guards to #pragma once.
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2024-01-16 23:34:46 -05:00 |
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Thomas Harte
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2b56b7be0d
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Simplify namespace syntax.
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2023-05-10 16:02:18 -05:00 |
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Thomas Harte
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ecfe68d70f
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Introduce the principle that a Serial::Line can be two-wire — clock + data.
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2021-11-06 16:54:20 -07:00 |
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Thomas Harte
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73c8157197
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Retain 6850 time tracking at all times.
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2021-04-20 22:26:43 -04:00 |
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Thomas Harte
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48afc54af6
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Cuts down unused parameter warnings to just a few that may well indicate implementation errors.
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2020-05-30 01:06:43 -04:00 |
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Thomas Harte
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31c6faf3c8
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Adds a bunch of consts.
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2020-05-09 21:23:52 -04:00 |
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Thomas Harte
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274867579b
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Deploys constexpr as a stricter const.
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2019-12-22 00:22:17 -05:00 |
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Thomas Harte
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7cd11ecb7f
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Adds necessary #include for assert.
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2019-12-08 22:43:39 -05:00 |
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Thomas Harte
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acfe2c63b8
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Adds an assert to verify the interrupt line is clear after a full reset.
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2019-12-08 22:34:19 -05:00 |
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Thomas Harte
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b192381928
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Implements a fuller reset, takes a run at the overran flag.
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2019-12-08 21:20:06 -05:00 |
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Thomas Harte
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d6edfa5c6d
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Removes the redundant state encased within interrupt_causes_.
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2019-11-11 21:49:02 -05:00 |
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Thomas Harte
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072b0266af
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It seems status reads are not required to clear the interrupt line.
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2019-11-09 20:12:09 -05:00 |
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Thomas Harte
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e3abbc9966
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Renames what didn't end up being a whole SerialPort.
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2019-11-09 15:21:51 -05:00 |
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Thomas Harte
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8c736a639a
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Eliminates unexpected bottleneck created by ACIA.
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2019-11-09 15:00:12 -05:00 |
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Thomas Harte
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14e790746b
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Fixes return value when reading received data.
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2019-11-02 21:25:00 -04:00 |
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Thomas Harte
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1c154131f9
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Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.
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2019-10-29 22:36:29 -04:00 |
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Thomas Harte
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7cb82fccc0
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Attempts properly to maintain interrupt flag; adds delegate.
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2019-10-21 22:40:38 -04:00 |
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Thomas Harte
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ed9a5b0430
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Adds receipt interrupt.
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2019-10-21 21:27:57 -04:00 |
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Thomas Harte
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8f59a73425
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Corrects incoming data capture.
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2019-10-21 20:18:52 -04:00 |
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Thomas Harte
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83f5f0e2ad
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Begins trying to receive ACIA data.
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2019-10-21 20:10:19 -04:00 |
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Thomas Harte
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4134463094
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The ACIA now receives bits.
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2019-10-20 23:34:30 -04:00 |
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Thomas Harte
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cf07982a9b
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Ensures good serial line and ACIA behaviour.
Next stop: having the intelligent keyboard react.
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2019-10-20 22:10:05 -04:00 |
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Thomas Harte
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696af5c3a6
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Starts to transfer serial line decoding logic into the line itself.
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2019-10-20 20:38:56 -04:00 |
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Thomas Harte
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9a8352282d
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Mostly but not quite fixes serial work.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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34075a7674
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Attempts to tie an intelligent keyboard to the other end of its serial line.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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c10b64e1c0
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Adds a received_data_ register, that presently can never fill.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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5d5fe52144
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Corrects transmission logic — exactly hitting write_data_time_remaining now works properly.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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ff62eb6dce
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The ACIA actually has two clocks, though on an ST they're both 500,000 Hz.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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374439693e
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Ensures serial lines know their writer's clock rate.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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c4ef33b23f
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JustInTimeActors can now specify a clock divider.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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a7ed357569
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Attempts to implement transmission interrupts and ClockingHint::Source.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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4e5b440145
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Attempts mostly to implement 6850 output.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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2bd7be13b5
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Decodes the 6850 control register, and starts working on standardised serial ports.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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4b09d7c41d
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Nudges 6850 towards coherence.
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2019-10-20 20:38:55 -04:00 |
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Thomas Harte
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4ead905c3c
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Adds an empty shell for the ACIA.
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2019-10-20 20:38:55 -04:00 |
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