Thomas Harte
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f576baf214
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I'm not yet sure this is the best approach, but starts trying to make use of Lorenz's 6526 tests.
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2021-07-30 21:21:16 -04:00 |
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Thomas Harte
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f27e331462
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Updates autotests to new RomFetcher world.
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2021-06-06 20:34:55 -04:00 |
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Thomas Harte
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3889646d6b
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Takes a swing at incorporating krom's 65816 test suite. At least as far as ADC.
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2020-11-02 21:09:32 -05:00 |
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Thomas Harte
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b22aa5d699
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Starts transcribing the addressing examples I have into tests.
Correspondingly extends the exposed register set and test-machine addressing range.
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2020-10-13 21:38:30 -04:00 |
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Thomas Harte
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0418f51ef2
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Takes a shot at emulation-mode 'exceptions'.
It's just RTI and correct decimal SBC left of the official 6502s now, I think.
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2020-10-08 17:52:13 -04:00 |
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Thomas Harte
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ef1a514785
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Introduces 6502Selector, for picking either a 6502 or a 65816 based on a single template parameter.
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2020-09-28 21:35:46 -04:00 |
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Thomas Harte
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5449e90b34
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Edges towards offering the 65816 as another type of 6502 for testing.
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2020-09-26 22:31:50 -04:00 |
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Thomas Harte
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b13b0d9311
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Starts towards implementing some OPL test cases.
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2020-04-14 23:51:45 -04:00 |
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Thomas Harte
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7959d243f6
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Adds single-stepping. Of a kind.
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2020-02-24 23:31:42 -05:00 |
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Thomas Harte
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79dd402bc8
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Consolidates different test port input selection.
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2020-02-23 16:12:28 -05:00 |
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Thomas Harte
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189122ab84
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Fixes test units.
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2020-01-27 20:35:58 -05:00 |
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Thomas Harte
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f42655a0fc
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Promote DigitalPhaseLockedLoop to a template, simplify to O(1) add_pulse.
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2020-01-12 17:25:21 -05:00 |
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Thomas Harte
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c1bae49a92
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Standardises on read and write for bus accesses.
Logic being: name these things for the bus action they model, not the effect they have.
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2020-01-05 13:40:02 -05:00 |
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Thomas Harte
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ed831e5912
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Fixes test syntax errors.
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2019-12-23 22:13:25 -05:00 |
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Thomas Harte
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0dae608da5
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Embraces std::make_[unique/shared] in place of .reset(new .
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2019-12-23 21:31:46 -05:00 |
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Thomas Harte
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1c154131f9
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Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.
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2019-10-29 22:36:29 -04:00 |
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Thomas Harte
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210bcaa56d
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Introduces an initial shift unit test, and makes it pass.
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2019-07-07 22:13:36 -04:00 |
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Thomas Harte
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ddf45a0010
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Ensures NMI and RST reset D on 65C02s.
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2018-08-14 19:49:14 -04:00 |
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Thomas Harte
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1a44ef0469
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Introduces Klaus Dorman's 65C02 tests. All failing.
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2018-08-06 21:48:43 -04:00 |
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Thomas Harte
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ebce9a2e51
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Fixes test target.
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2018-08-06 21:15:13 -04:00 |
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Thomas Harte
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0b771ce61a
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Removes all instances of the copyright symbol.
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2018-05-13 15:19:52 -04:00 |
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Thomas Harte
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66faed4008
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Gives MachineForTargets complete responsibility for initial machine state.
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2018-01-25 18:28:19 -05:00 |
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Thomas Harte
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05b95ea2e0
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Corrects Xcode tests.
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2018-01-01 16:04:13 -05:00 |
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Thomas Harte
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ff24e1de31
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Corrects 6522 bridge per has-a-not-is-a template switch.
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2017-09-04 21:56:21 -04:00 |
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Thomas Harte
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ee71be0e7e
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Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
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2017-08-21 21:56:42 -04:00 |
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Thomas Harte
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761afad118
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Corrected timestamp return, and its testing by the 6502 timing tests.
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2017-07-27 21:19:16 -04:00 |
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Thomas Harte
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37950143fc
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Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
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2017-07-27 20:17:13 -04:00 |
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Thomas Harte
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6ec4e4e3d7
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Merge branch 'master' into Memptr
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2017-07-25 23:01:34 -04:00 |
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Thomas Harte
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3ca51bedc6
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Discovered legitimate uses of the jam opcode so reinstated it. Corrected illegitimate uses.
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2017-07-25 22:48:44 -04:00 |
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Thomas Harte
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36076b7ea5
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Eliminated final vestige of professed jam handling. This should make it clear which tests still think they can capture jams.
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2017-07-25 22:38:26 -04:00 |
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Thomas Harte
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df4732be2e
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Corrected test.
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2017-07-24 22:33:49 -04:00 |
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Thomas Harte
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9435c1e12a
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The 1540 is now a ClockReceiver.
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2017-07-24 22:32:41 -04:00 |
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Thomas Harte
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2912d7055b
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The 6532 is now a ClockReceiver.
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2017-07-24 21:57:24 -04:00 |
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Thomas Harte
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b3ae920746
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Converted the DPLL and disk controller classes to be ClockReceivers.
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2017-07-24 21:04:47 -04:00 |
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Thomas Harte
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e6578defcd
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It turns out that quite a few tests still rely on CSTestMachine6502JamOpcode. Though since it no longer works, that'll need to be fixed. In the meantime, fixed the test build process at least, as it's not really what this branch is meant to be invested in.
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2017-07-23 22:22:50 -04:00 |
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Thomas Harte
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ace8e30818
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Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
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2017-07-23 22:21:39 -04:00 |
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Thomas Harte
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b0c2325adc
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Corrected run call, and accepted that jam handling is gone forever.
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2017-07-22 22:21:26 -04:00 |
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Thomas Harte
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660f0e4c40
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Added Objective-C through wiring and a Swift test class for Memptr modifications. So far with a single test, that fails.
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2017-07-21 22:52:25 -04:00 |
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Thomas Harte
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7b5f93510b
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Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.
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2017-07-16 20:55:57 -04:00 |
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Thomas Harte
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8ddd686049
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Removed redundant variable.
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2017-07-16 19:04:03 -04:00 |
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Thomas Harte
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2fb0aea990
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Updated the C1540 test vessel to the new world.
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2017-07-16 17:00:39 -04:00 |
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Thomas Harte
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95a6b0f85c
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Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
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2017-06-22 21:09:26 -04:00 |
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Thomas Harte
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0e0ce379b4
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Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
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2017-06-21 20:38:08 -04:00 |
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Thomas Harte
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36e8a11505
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Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
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2017-06-21 20:32:08 -04:00 |
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Thomas Harte
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d668879ba6
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Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
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2017-06-18 22:03:13 -04:00 |
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Thomas Harte
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e1a2580b2a
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Renamed BusOperation to MachineCycle::Operation.
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2017-06-17 21:53:45 -04:00 |
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Thomas Harte
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b6f51474ff
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Ensured that -description can handle the newly-captured bus actions.
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2017-06-17 18:20:30 -04:00 |
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Thomas Harte
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cf795562bf
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Continued filling in tests, fleshing out what the test machine captures as a result.
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2017-06-15 20:59:59 -04:00 |
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Thomas Harte
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aed2827e7b
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Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
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2017-06-12 22:22:00 -04:00 |
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Thomas Harte
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fd6623b5a5
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Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
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2017-06-03 21:22:16 -04:00 |
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