6502/CLK
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mirror of https://github.com/TomHarte/CLK.git synced 2024-12-27 16:31:31 +00:00
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11,614 Commits 7 Branches 121 Tags 500 MiB
8e64a854fc
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916 Commits

Author SHA1 Message Date
Thomas Harte
8e64a854fc Ensure all routes return; mildly decrease conditionals. 2024-04-22 21:56:53 -04:00
Thomas Harte
ea3eef3817 Put interrupts into pipeline, without delay. 2024-04-19 22:21:23 -04:00
Thomas Harte
83eac172c9 Revoke in-pipeline interrupts. 
I'm unclear on what timing should apply here really.
 2024-04-19 21:46:09 -04:00
Thomas Harte
5b13d3e893 Attempt the prefetch portion of a pipeline. 2024-04-19 21:30:15 -04:00
Thomas Harte
4bf02122ee Fix disassembler. 2024-04-18 23:17:44 -04:00
Thomas Harte
e6c4454059 Provide a means for SWI interception. 2024-04-18 22:13:58 -04:00
Thomas Harte
d464ce831a Add did_set_pc. 2024-04-18 19:30:07 -04:00
Thomas Harte
da520de9ef Further appease GCC. 2024-04-17 22:38:32 -04:00
Thomas Harte
e680a973b0 Appease GCC with a 'default'. 2024-04-17 22:17:24 -04:00
Thomas Harte
07984a2f8b Resolve various warnings. 2024-04-17 22:15:05 -04:00
Thomas Harte
4f58664f97 Catch interrupt enables. 2024-04-07 22:08:12 -04:00
Thomas Harte
7d8a364658 Reimplement LDM and STM. 2024-04-04 21:59:18 -04:00
Thomas Harte
41c471ca52 Add a force-user-aware accessor. 2024-04-04 20:17:44 -04:00
Thomas Harte
dd127f64fe Simplify range. 2024-04-03 07:23:14 -04:00
Thomas Harte
b19dcfd6dc Take another run at shifts. 2024-04-02 21:57:46 -04:00
Thomas Harte
7c9715f00c Change mind about carry behaviour. 2024-04-01 21:38:44 -04:00
Thomas Harte
7de92a9457 Slightly clean up shift code. 2024-04-01 21:24:49 -04:00
Thomas Harte
2e7c1acb88 Add note on confusion. 2024-03-28 10:34:46 -04:00
Thomas Harte
4fcb85d132 Cleave off most remaining reasons for failure. 2024-03-28 10:32:27 -04:00
Thomas Harte
0e17f382a1 Capture further detail. 2024-03-27 22:36:03 -04:00
Thomas Harte
72a645ec1e Fix trans; take further crack at MEMC permissions. 2024-03-25 15:50:59 -04:00
Thomas Harte
521fca6089 Expose full bus to IOC dependents; add notes. 2024-03-25 11:07:44 -04:00
Thomas Harte
55f92e2411 Adjust data abort address. 2024-03-23 20:31:47 -04:00
Thomas Harte
9ea3e547ee Fix IRQ/FIQ return addresses. 2024-03-22 21:42:34 -04:00
Thomas Harte
ae6cf69449 Move responsibility for clock division; reinstate vsync interrupt. 2024-03-22 10:01:34 -04:00
Thomas Harte
85a738acff Get rigorous on exception addresses. 2024-03-19 15:03:31 -04:00
Thomas Harte
9d084782ae Document. 2024-03-19 12:22:19 -04:00
Thomas Harte
106937b679 Run into the shifts wall with LDR/STR. 2024-03-19 12:19:49 -04:00
Thomas Harte
623eda7162 Output branches and nops correctly. 2024-03-19 11:42:41 -04:00
Thomas Harte
2ad6bb099b Begin foray into disassembly. 2024-03-19 11:34:10 -04:00
Thomas Harte
9d858bc61b IRQ and FIQ should also store PC+4. 2024-03-18 14:08:08 -04:00
Thomas Harte
1c1d2891c7 Adjust IRQ/FIQ return addresses. 2024-03-15 21:59:38 -04:00
Thomas Harte
1979d2e5ba Don't set interrupt flags before capture. 2024-03-15 21:34:39 -04:00
Thomas Harte
c25d0e8843 Correctly capture mode upon exception. 2024-03-15 18:39:56 -04:00
Thomas Harte
bc27e3998d Fix downward block data transfers. 2024-03-14 21:09:51 -04:00
Thomas Harte
4987bdfec9 Throw less. 2024-03-14 10:43:51 -04:00
Thomas Harte
5d6bb11eb7 Add return. 2024-03-12 11:37:15 -04:00
Thomas Harte
c6b91559e1 Attempt to wire up timer interrupts. 2024-03-12 11:34:31 -04:00
Thomas Harte
6efc41ded7 Come to conclusion on R15; fix link values. 2024-03-12 10:42:09 -04:00
Thomas Harte
e9c5582fe1 Add note on ambiguity to be resolved. 2024-03-12 10:04:02 -04:00
Thomas Harte
8b3c0abe93 Take another swing at R15 as a destination. 2024-03-12 09:13:05 -04:00
Thomas Harte
971bfb2ecb Unify subtractions. 2024-03-11 14:52:48 -04:00
Thomas Harte
e8c1e8fd3f Fix RSB carry; unify set_pc. 2024-03-11 14:48:43 -04:00
Thomas Harte
830d70d3aa Trust tests on immediate-opcode ROR 0; limit shift by register. 2024-03-10 23:38:31 -04:00
Thomas Harte
336292bc49 Further correct R15 as a destination. 2024-03-10 22:56:02 -04:00
Thomas Harte
bd62228cc6 The test set doesn't seem to do word rotation. 2024-03-10 22:40:37 -04:00
Thomas Harte
e9e1db7a05 Change LDR writeback to destination. 2024-03-10 22:29:19 -04:00
Thomas Harte
fbc273f114 Add invented model for tests. 2024-03-10 21:45:56 -04:00
Thomas Harte
a4cf86268e Provide full access to stored registers. 2024-03-09 15:11:04 -05:00
Thomas Harte
d059e7c5d8 Disallow copying. 2024-03-09 15:10:55 -05:00