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Author	SHA1	Message	Date
Thomas Harte	93f768af9b	Bump control codes up in the roster.	2025-09-25 22:18:52 -04:00
Thomas Harte	f8c11bf217	Rejig to ensure SAA output ends.	2025-09-25 21:31:21 -04:00
Thomas Harte	26ccd930c3	Begin tidying.	2025-09-25 17:53:54 -04:00
Thomas Harte	82211c7312	Add some 'graphics' support.	2025-09-25 17:50:26 -04:00
Thomas Harte	2015c154fe	Correctly clear double-height flags.	2025-09-25 13:28:22 -04:00
Thomas Harte	ef17d116a8	Don't permit single-height text on a lower double-height row.	2025-09-25 13:22:25 -04:00
Thomas Harte	46fddc44bf	Support double-height text.	2025-09-25 13:21:49 -04:00
Thomas Harte	0214a77cd7	Add TODO.	2025-09-25 13:10:52 -04:00
Thomas Harte	425ed658f1	Support colour control codes, clarify SAA5050 signalling.	2025-09-25 13:03:55 -04:00
Thomas Harte	a53adb561e	Erase TODO, continue to update state without target.	2025-09-25 09:25:46 -04:00
Thomas Harte	3c3c55090a	Port forward ElectrEm's font smoothing.	2025-09-25 09:22:16 -04:00
Thomas Harte	ebc04c6520	Eliminate warning.	2025-09-24 22:58:50 -04:00
Thomas Harte	8b0e8f5b13	Move all work [near] definitively into the SAA5050.	2025-09-24 22:55:49 -04:00
Thomas Harte	16132a007e	Remove silly call.	2025-09-24 22:26:37 -04:00
Thomas Harte	b6e41ceea7	Hack in low-resolution Mode 7.	2025-09-24 22:25:43 -04:00
Thomas Harte	7015e46227	Put together enough of an interface to expect to see some pixels.	2025-09-24 22:08:04 -04:00
Thomas Harte	cce2607c80	Add file for SAA5050 logic.	2025-09-24 21:43:25 -04:00
Thomas Harte	9dd2ec8bda	Merge pull request #1573 from TomHarte/New6845 ... Improve 6845.	2025-09-24 21:36:16 -04:00
Thomas Harte	068726e0ab	Add TODO.	2025-09-24 21:26:04 -04:00
Thomas Harte	89e86ad9bd	Delay publication of the refresh address.	2025-09-24 21:20:20 -04:00
Thomas Harte	2e49bc2044	Add teletext pixel route, albeit without proper selection.	2025-09-24 20:33:07 -04:00
Thomas Harte	174c8dafbf	Resolve potential out-of-phase line counter.	2025-09-24 17:26:40 -04:00
Thomas Harte	90a96293de	Implement interlace-dependent row addressing.	2025-09-24 17:20:04 -04:00
Thomas Harte	84877c4fec	Reenable the cursor; good enough for now.	2025-09-24 14:37:52 -04:00
Thomas Harte	a7cceb5fa9	Avoid circular state dependency.	2025-09-24 14:30:37 -04:00
Thomas Harte	ca6359a597	Reintroduce pixels, proving myself to be off-by-one.	2025-09-24 14:29:25 -04:00
Thomas Harte	b7c3667be1	Work out inadvertent discrepancies.	2025-09-24 14:11:06 -04:00
Thomas Harte	b6dea59db3	This tests lines, not rows.	2025-09-24 13:56:16 -04:00
Thomas Harte	aa51f13743	Reorder to avoid dependencies upon values that mutate.	2025-09-24 13:54:09 -04:00
Thomas Harte	f34ec03ff0	Attempt to fix off-by-one; adopt fixed pixel pattern.	2025-09-24 13:42:17 -04:00
Thomas Harte	1363be59b7	Formalise field size.	2025-09-24 11:17:47 -04:00
Thomas Harte	622c24ef24	This indicates a line, not a row.	2025-09-23 22:36:56 -04:00
Thomas Harte	539b0e49d4	Start in mode 7, reallow interlaced modes.	2025-09-23 14:45:32 -04:00
Thomas Harte	0c42976312	Add notes to self.	2025-09-23 14:42:16 -04:00
Thomas Harte	3f6b3a4fa0	Don't allow a state to be permanently accumulated.	2025-09-23 14:41:59 -04:00
Thomas Harte	67e1773495	This flag covers rows, not lines.	2025-09-23 14:29:00 -04:00
Thomas Harte	a199b64aa0	Clarify naming, attempt better to conform to FPGA precedent.	2025-09-23 14:27:21 -04:00
Thomas Harte	ebf09aceb2	Further extend. This is becoming more of a SizedInt.	2025-09-23 14:26:58 -04:00
Thomas Harte	ca226e4295	Merge branch 'master' into New6845	2025-09-22 13:28:33 -04:00
Thomas Harte	9261939f62	Switch to working PC for testing.	2025-09-22 13:24:35 -04:00
Thomas Harte	0349931953	Shuffle declare order.	2025-09-22 13:21:48 -04:00
Thomas Harte	d612a385d2	Dig in further on types.	2025-09-22 13:20:10 -04:00
Thomas Harte	ed4f299d55	Start formalising types.	2025-09-22 13:09:30 -04:00
Thomas Harte	7cef789d41	Merge branch 'master' into New6845	2025-09-22 12:47:32 -04:00
Thomas Harte	66bfb86d42	Introduce SizedCounter as start of CRTC reworking.	2025-09-22 12:46:39 -04:00
Thomas Harte	c4a5bc12ef	Merge pull request #1572 from TomHarte/BBCADFS ... Support ADFS, sideways RAM.	2025-09-20 23:27:15 -04:00
Thomas Harte	557631f6ba	Support ADFS, sideways RAM.	2025-09-20 22:33:08 -04:00
Thomas Harte	362ffaff7f	Merge pull request #1571 from TomHarte/RandomPauses ... Correct uPD7002 interrupt wiring and behaviour.	2025-09-20 22:08:13 -04:00
Thomas Harte	fb5ef200fb	Correct uPD7002 interrupt wiring.	2025-09-20 21:51:19 -04:00
Thomas Harte	5e78ac3af5	Adjust keyboard map slightly.	2025-09-20 21:35:01 -04:00