Thomas Harte
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8c41a0f0ed
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Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.
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2017-06-03 17:53:44 -04:00 |
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Thomas Harte
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3e9212aaff
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Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
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2017-06-03 17:41:45 -04:00 |
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Thomas Harte
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a2ec902773
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Made an attempt at implementing all three modes of IRQ.
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2017-06-03 17:07:05 -04:00 |
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Thomas Harte
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1c0130fd02
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Cleaned up with a macro, and decided to make absolutely sure that DecodeOperation is functioning as intended by removing the MoveToNextProgram from fetch-decode-execute.
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2017-06-03 12:19:25 -04:00 |
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Thomas Harte
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3e3d6f97f4
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Edged towards being able to implement interrupt mode 0: created a special-case micro-op for incrementing the PC, and formalised that DecodeOperation is a terminal operation.
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2017-06-03 12:16:21 -04:00 |
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Thomas Harte
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9c3bda0111
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Attempted to round out NMI handling.
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2017-06-03 11:30:12 -04:00 |
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Thomas Harte
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d14902700a
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Minor syntax and wiring fixes.
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2017-06-01 22:33:05 -04:00 |
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Thomas Harte
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c95c32a9fe
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Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.
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2017-06-01 22:31:04 -04:00 |
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Thomas Harte
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35e045d7a7
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Made a first attempt at the correct segue into the three main kinds of interrupt, though the programs aren't written yet. So undefined behaviour would abound were an interrupt to occur. But it lets me figure out what effect the check has on performance. I hope little.
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2017-06-01 22:16:22 -04:00 |
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Thomas Harte
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084e1f3d51
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Added a latching of interrupt status before each bus operation, and reset and power-on inputs.
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2017-06-01 21:40:08 -04:00 |
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Thomas Harte
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5b43cefb85
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Started filling an appropriate mask variable with the interrupt request status right now. Which is step one towards implementing interrupts.
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2017-06-01 20:34:52 -04:00 |
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Thomas Harte
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aab637c9e7
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Made check_address_for_trap inlineable.
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2017-06-01 18:28:34 -04:00 |
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Thomas Harte
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7d9b197383
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Pulled the .get() call for fetch-decode-execute out of the main loop.
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2017-06-01 18:28:04 -04:00 |
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Thomas Harte
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c9dd267ec1
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Sketched an interface for signalling interrupts and pulled out some of the repetition in flag setting from ADD/ADC/SUB/SBC/CP.
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2017-05-31 22:51:32 -04:00 |
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Thomas Harte
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a5254989f8
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Rewired the Z80 not to use the program queue, as it's not proven a useful abstraction in practice and doing so yields an immediate 22% speed increase.
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2017-05-31 20:15:56 -04:00 |
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Thomas Harte
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494ce073b5
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Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging.
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2017-05-31 19:58:57 -04:00 |
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Thomas Harte
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b99e4210ba
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Eliminated pointless abstraction; I ended up going indirect on instruction pages rather than scheduling methods.
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2017-05-31 19:57:03 -04:00 |
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Thomas Harte
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d3b74cbc91
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Set proper initial value for number_of_cycles_.
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2017-05-31 19:55:51 -04:00 |
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Thomas Harte
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5ff73faf48
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Ensured Zexall can pass.
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2017-05-31 19:55:06 -04:00 |
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Thomas Harte
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2f7f11e2e5
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Added diagnosis props.
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2017-05-31 06:54:25 -04:00 |
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Thomas Harte
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5119997122
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Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
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2017-05-30 22:41:23 -04:00 |
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Thomas Harte
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b5c1773d59
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Eliminated another conditional. Albeit a very predictable one.
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2017-05-30 22:15:43 -04:00 |
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Thomas Harte
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dfb5057342
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Moved repetition group conditions explicitly into the switch statement.
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2017-05-30 22:12:10 -04:00 |
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Thomas Harte
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7bddd294c9
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Resolved an unpredictable conditional and temporarily disabled the Zexalltest as part of the default suite, since it takes so long to run.
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2017-05-30 21:03:02 -04:00 |
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Thomas Harte
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01f7394f7f
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Corrected 6502 scheduling when flushing the pipeline.
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2017-05-30 20:58:07 -04:00 |
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Thomas Harte
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5aa8b03349
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Attempted to regularise the 6502 with the Z80 as to scheduling. I think that at least one bug remains.
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2017-05-30 20:36:53 -04:00 |
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Thomas Harte
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b5ad910b81
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Merge branch 'Z80' into StraightPointer
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2017-05-30 19:25:38 -04:00 |
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Thomas Harte
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da65bae86e
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Switched to supplying the bus operation by reference, go guarantee that it isn't null.
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2017-05-30 19:24:58 -04:00 |
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Thomas Harte
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a0189a6fe1
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Switched to following the current program via address.
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2017-05-30 18:49:40 -04:00 |
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Thomas Harte
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244b5ba3c2
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Added a proper termination condition for Zexall and, for now, a Mhz counter.
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2017-05-30 18:32:38 -04:00 |
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Thomas Harte
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960de7bd7b
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Marginally reduced test machine costs based on usage.
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2017-05-30 11:59:07 -04:00 |
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Thomas Harte
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c6185baa99
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Fixed R incrementation and attempted to make the status flags cheaper to write to.
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2017-05-29 22:23:19 -04:00 |
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Thomas Harte
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4d4695032c
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Discovered that Zexall is just really slow. Disabled the address sanitiser, and started working towards a verifiable end.
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2017-05-29 21:46:00 -04:00 |
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Thomas Harte
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9d29cefe75
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Evicted manual memory management.
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2017-05-29 21:44:33 -04:00 |
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Thomas Harte
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35f535b9a3
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Noodled around with initial state.
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2017-05-29 19:25:08 -04:00 |
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Thomas Harte
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6d22f6fcd5
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Having decided the bus operation error on 10 is probably in the test cases, decided to allow myself to skip that one comparison. Back to zero failing cases, and with no more useful information to derive from the FUSE test set for the time being.
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2017-05-29 17:17:17 -04:00 |
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Thomas Harte
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8bfaa487ce
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Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit).
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2017-05-29 17:13:24 -04:00 |
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Thomas Harte
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0d067d2f01
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Adjusted OTI/etc timing; 23 failures outstanding.
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2017-05-29 16:54:45 -04:00 |
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Thomas Harte
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d66755fd1e
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Corrected INI/D[r] timing. Down to 45 failures.
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2017-05-29 16:50:52 -04:00 |
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Thomas Harte
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267b2add9a
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Adjusted for where FUSE nominally places timestamps. Down to 92 failures.
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2017-05-29 16:44:07 -04:00 |
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Thomas Harte
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d290e3d99e
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Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!)
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2017-05-29 16:35:00 -04:00 |
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Thomas Harte
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a6a4c5a936
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Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures.
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2017-05-29 15:57:27 -04:00 |
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Thomas Harte
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8a8f0cef20
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With all intentional opcode entry points now covered, commuted XX into NOP to give proper meaning to otherwise undefined codes.
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2017-05-29 12:25:10 -04:00 |
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Thomas Harte
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91dc0d5f4a
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Adjusted HALT to issue never-ending M1 fetches on the next instruction.
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2017-05-29 12:20:33 -04:00 |
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Thomas Harte
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ed7b07c8b1
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Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct.
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2017-05-29 11:54:27 -04:00 |
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Thomas Harte
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3f880fa769
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Fixed [FD/DD][74/75], which always store H or L, never IXh, IXl, IYh or IYl.
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2017-05-29 11:44:26 -04:00 |
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Thomas Harte
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d83dd17738
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[DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed.
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2017-05-29 11:40:56 -04:00 |
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Thomas Harte
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9ade0dcae3
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One failure was just PUSH AF due to throwing away the 5 & 3 flags at the start. Switched to throwing them away at comparison.
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2017-05-29 11:06:23 -04:00 |
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Thomas Harte
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a329d85697
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Instituted memory value checks, flushing out seven new failures.
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2017-05-29 11:01:45 -04:00 |
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Thomas Harte
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c322410783
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Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation.
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2017-05-29 10:52:54 -04:00 |
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