Thomas Harte
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a246530953
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Supposing the TIA were implemented, this is (more or less) what the Atari 2600 would now look like.
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2017-01-28 21:46:40 -05:00 |
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Thomas Harte
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0ffded72a6
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Created a placeholder class for a factored-out TIA. There's a bit more it'll need to do, like vending (or receiving) a CRT but this is the full hardware stuff, I think.
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2017-01-28 16:19:08 -05:00 |
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Thomas Harte
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6d087ca054
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Restored 2600 audio.
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2017-01-25 21:29:19 -05:00 |
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Thomas Harte
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be1cb2a551
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Fixed NTSC phase.
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2017-01-11 21:31:24 -05:00 |
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Thomas Harte
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6153ada33b
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Fixed Electron's support for automatically booting floppy disks.
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2017-01-08 14:46:19 -05:00 |
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Thomas Harte
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8cd1575891
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Similar fix to that over in Oric land: ensure a known, effective initial value for the Plus 3's control register.
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2016-12-28 18:52:36 -05:00 |
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Thomas Harte
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90151e2094
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Fixed to ensure a known initial control register value, which has taken effect.
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2016-12-28 18:49:32 -05:00 |
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Thomas Harte
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a568172758
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Made steps towards proper CRC generation. Am currently comparing against Oric disk images, as — amongst other things — they include precomputed CRCs.
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2016-12-28 18:29:37 -05:00 |
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Thomas Harte
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4fca30b81f
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Made the Plus 3 less chatty, documented invalidate_track.
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2016-12-25 21:06:58 -05:00 |
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Thomas Harte
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3805e3d17d
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Ensured base address is set properly at construction.
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2016-12-22 22:46:02 -05:00 |
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Thomas Harte
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63107cd492
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Tidied, very slightly.
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2016-12-15 19:49:25 -05:00 |
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Thomas Harte
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a555c5762a
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Rearranged code, hopefully into a more logical grouping.
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2016-12-15 19:47:04 -05:00 |
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Thomas Harte
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4a7ddaf2e9
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Added documentation and a quick note to self.
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2016-12-15 19:43:04 -05:00 |
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Thomas Harte
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f61176cd7d
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Reinstituted something of the don't-do-pixel-work-until-an-affecting-write-occurs optimisation.
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2016-12-15 19:20:14 -05:00 |
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Thomas Harte
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c1c70a767a
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Attempted fully to reinstate proper timing.
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2016-12-15 18:52:16 -05:00 |
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Thomas Harte
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0326316bb8
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Reinstated whole-frame counting. Thereby to reinstate proper interrupts.
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2016-12-15 18:09:49 -05:00 |
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Thomas Harte
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b58b11fc93
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Switched to a table-based dispatch of line-by-line actions, primarily to simplify.
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2016-12-15 18:07:46 -05:00 |
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Thomas Harte
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fd541e1142
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An early draft; dealing with the issue that not all cycles are necessarily consumed in a single call. Incomplete; broken. Committing for cross-machine visibility.
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2016-12-12 08:01:10 -05:00 |
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Thomas Harte
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be7e05e109
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Started attempting to move total responsibility for display-related interrupts and RAM timing into the video.
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2016-12-11 18:34:49 -05:00 |
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Thomas Harte
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c5cf8d9531
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Ensured the video subsystem correctly handles requests to run over a frame boundary.
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2016-12-11 16:17:51 -05:00 |
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Thomas Harte
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52028432e1
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Restored some semblance of output.
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2016-12-10 22:19:10 -05:00 |
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Thomas Harte
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0aae1bd1ef
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Fixed calculation of termination cycle.
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2016-12-10 21:35:41 -05:00 |
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Thomas Harte
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c43e481a33
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Started factoring video out of the Electron.
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2016-12-10 21:07:52 -05:00 |
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Thomas Harte
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e62be03673
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Removed endianness assumption.
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2016-12-10 19:10:33 -05:00 |
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Thomas Harte
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a5683dfb21
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Removed now untrue comment.
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2016-12-10 15:19:48 -05:00 |
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Thomas Harte
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0e71802b92
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Reduced Oric video to single nibble constants. Removed attempt at asynchronous flush as no longer required.
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2016-12-10 14:17:46 -05:00 |
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Thomas Harte
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580f347727
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Fixed Oric SCART mode by having it change what it's giving to the CRT based on which shader it knows will be active.
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2016-12-10 13:55:56 -05:00 |
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Thomas Harte
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a549fd1ecc
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Introduced the ability simply to piggy-back off the CRT's natural phase for the colour burst, thereby eliminating a couple of redundant independent attempts in the Oric and Electron.
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2016-12-10 13:42:34 -05:00 |
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Thomas Harte
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6cdd41e5a9
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Added direct use of the colour ROM, uploading 16 bits per pixel to contain the entire ROM composite wave.
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2016-12-09 22:17:10 -05:00 |
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Thomas Harte
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3b5962b171
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This is an initial attempt at using the actual Oric colour ROM values for composite video generation.
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2016-12-09 20:01:27 -05:00 |
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Thomas Harte
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c304db0f5a
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Deintegrated the busy flag and the interrupt request line, as the latter is reset by status reads. Which also means I can start reporting the WD INTRQ line status directly from the Microdisc. That appears to be correct, rather than honouring the Microdisc IRQ select there.
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2016-12-06 21:16:29 -05:00 |
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Thomas Harte
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ebb62a2d78
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Switched the 2600 to postfix and non-camel-case instance variable names.
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2016-12-03 14:07:38 -05:00 |
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Thomas Harte
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b81c058c0a
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Factored out the Atari 2600's 6532 connection, as a low-hanging fruit.
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2016-12-03 13:41:55 -05:00 |
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Thomas Harte
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3361d6b93a
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Factored out the Atari 2600 speaker and adjusted it to postfix underscores.
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2016-12-03 13:39:46 -05:00 |
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Thomas Harte
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1b1a8d3e52
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Brought the Vic-20 into suffix naming.
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2016-12-03 13:30:27 -05:00 |
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Thomas Harte
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063a62372f
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The Commodore serial bus and C1540 are now postfix underscorers.
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2016-12-03 13:14:03 -05:00 |
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Thomas Harte
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eb3a1fbfb7
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Commuted remaining Electron underscores. It would be nice also to factor out the video, but the time hasn't come yet.
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2016-12-03 13:01:01 -05:00 |
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Thomas Harte
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4fac538a57
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Factored out the Electron's speaker and adjusted instance variable naming.
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2016-12-03 12:41:02 -05:00 |
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Thomas Harte
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d1d93829cf
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Factored out the Tape and switched it to postfix underscores.
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2016-12-03 12:18:08 -05:00 |
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Thomas Harte
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2003b514aa
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Switched the typer to postfix underscores.
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2016-12-03 10:55:50 -05:00 |
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Thomas Harte
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81ee834530
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As well as a bunch of logging, reinstated rotation position preservation across tracks.
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2016-12-02 18:36:47 -05:00 |
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Thomas Harte
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93c573bfa9
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Implemented missing status bits (other than the index hole), and a head loading delay for the Microdisc.
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2016-12-01 21:13:16 -05:00 |
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Thomas Harte
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442986ee2c
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Introduced a head loading path for 1793 machines.
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2016-12-01 20:12:22 -05:00 |
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Thomas Harte
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82899f2f47
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Ensured flag setting is atomic, removed duplication of interrupt request versus busy, found better names for the personality testers, unified delegate protocol.
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2016-12-01 07:41:52 -05:00 |
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Thomas Harte
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9b6c5e814a
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Now that it can be more explicit, this should admit that it's '93-based, not '73.
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2016-11-28 16:22:35 -05:00 |
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Thomas Harte
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2f459690d4
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It would appear the 1770 and 1773 actually differ in relation to the (non-sensical) ability not to spin-up for a Type 2, and whether a side compare can occur. So the WD1770 class now requires a personality to be specified. Which it singly fails to honour.
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2016-11-26 23:29:30 +08:00 |
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Thomas Harte
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e9d6566e9c
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Of course, changing the IRQ enable may immediately change the IRQ line. Signal if so.
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2016-11-26 09:35:44 +08:00 |
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Thomas Harte
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73d30b9c00
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Corrected typo.
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2016-11-25 21:30:45 +08:00 |
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Thomas Harte
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12956901d6
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Filled in some register mirrors.
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2016-11-25 21:28:11 +08:00 |
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Thomas Harte
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54246c8f1a
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Interrupt enabling works the other way around I think, and both registers with only one bit defined should probably return '1' in all other places?
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2016-11-25 21:24:59 +08:00 |
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