Thomas Harte
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ace71280a0
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Removed implementation file; this is only ever going to be a template.
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2017-08-01 16:00:17 -04:00 |
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Thomas Harte
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68ceeab610
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Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
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2017-07-31 19:56:59 -04:00 |
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Thomas Harte
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c0f1313830
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Performed sufficient wiring to get to the point where attempting to load a CDT creates an instance of the Amstrad CPC and then fails only because the thing vends a nullptr CRT.
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2017-07-30 22:05:29 -04:00 |
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Thomas Harte
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5b5720fac0
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Added to the static analyser the most basic through-path for Amstrad CPC content.
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2017-07-30 21:15:20 -04:00 |
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Thomas Harte
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6ec4e4e3d7
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Merge branch 'master' into Memptr
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2017-07-25 23:01:34 -04:00 |
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Thomas Harte
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75d67ee770
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Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
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2017-07-25 20:20:55 -04:00 |
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Thomas Harte
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1ba3f262a2
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Sketched out a template for clock-receiving components to allow them to be implemented in terms of either half or whole cycles.
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2017-07-22 21:46:50 -04:00 |
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Thomas Harte
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660f0e4c40
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Added Objective-C through wiring and a Swift test class for Memptr modifications. So far with a single test, that fails.
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2017-07-21 22:52:25 -04:00 |
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Thomas Harte
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2a7fc86b15
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Enabled stricter warnings.
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2017-07-21 20:44:35 -04:00 |
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Thomas Harte
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8f72fc4a44
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Factored out from the UEF implementation the concept of being a tape that has a queue of pending pulses and manages that queue.
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2017-07-16 22:04:40 -04:00 |
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Thomas Harte
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238348c885
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Performed the initial wiring to announce that this application supports TZX files and to route them to the ZX80/81 static analyser. The TZX class itself does not yet do much beyond basic validation. I think it'll be easiest if it follows in UEF's footsteps in queuing up pulses ahead of time, so some factoring out is now required.
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2017-07-16 21:33:11 -04:00 |
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Thomas Harte
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368bff1a82
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Added a shell class that will one day be able to parse CSW files, plus the logic and metadata to instantiate it when a CSW presents itself.
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2017-07-10 21:43:58 -04:00 |
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Thomas Harte
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3e5c209039
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Added basic Typer support for the ZX80 and '81.
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2017-07-09 22:00:34 -04:00 |
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Thomas Harte
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28412150e6
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Added controls for controlling the tape motor of the ZX80/81, assuming I can find an automatic option.
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2017-07-08 17:59:33 -04:00 |
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Thomas Harte
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ac37424878
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Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.
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2017-06-15 19:06:59 -04:00 |
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Thomas Harte
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77aa3c187e
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Rebranded ZX80O as ZX80O81P, with an eye to making it accept ZX81 .p files. Adjusted the initial selection part of the static analyser appropriately.
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2017-06-11 21:38:32 -04:00 |
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Thomas Harte
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7e10c7f9d8
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Relocated the ZX80/81 concept of a 'file' out from Tape into Data, given that it's an exact duplicate of memory.
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2017-06-08 19:09:51 -04:00 |
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Thomas Harte
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60300851ea
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Started sketching out a tape parser for ZX80 and '81 files. I think this'll help me to verify whether the .O input is working.
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2017-06-07 10:12:13 -04:00 |
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Thomas Harte
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8c66e1d99d
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Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data.
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2017-06-06 17:53:23 -04:00 |
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Thomas Harte
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b0a7c58287
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Fixed project to point to the XIB I actually want to keep; fixed that XIB to have the correct contents.
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2017-06-04 17:57:37 -04:00 |
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Thomas Harte
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d2637123c4
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Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.
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2017-06-04 17:55:19 -04:00 |
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Thomas Harte
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02b7c3d1b0
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Added the necessary wiring to get into a ZX80/81-oriented part of the static analyser, which could in principle post a ZX80 target.
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2017-06-04 17:04:06 -04:00 |
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Thomas Harte
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655809517c
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Ensured that there is a subclass of file that is entrusted to load .O/.80 files, and that the code routes such files to it, noting that it should consider whether a ZX80 is required.
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2017-06-04 16:37:03 -04:00 |
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Thomas Harte
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fd6623b5a5
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Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
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2017-06-03 21:22:16 -04:00 |
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Thomas Harte
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b304c3a4b9
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Eliminated the 6502's reliance on the micro-op scheduler.
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2017-06-03 20:30:07 -04:00 |
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Thomas Harte
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3e9212aaff
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Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
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2017-06-03 17:41:45 -04:00 |
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Thomas Harte
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244b5ba3c2
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Added a proper termination condition for Zexall and, for now, a Mhz counter.
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2017-05-30 18:32:38 -04:00 |
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Thomas Harte
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3c6f63abcc
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Started towards running the FUSE tests. Just need to deal with the memory segments.
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2017-05-25 19:12:59 -04:00 |
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Thomas Harte
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e3e461d7cb
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Added a test class for running the FUSE tests. With nothing much in it.
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2017-05-21 22:49:24 -04:00 |
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Thomas Harte
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11d05fb3b8
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Expanded a little on operations, added an implementation or two.
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2017-05-19 19:18:35 -04:00 |
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Thomas Harte
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58efca835f
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Sought to add a further opcode.
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2017-05-18 22:53:43 -04:00 |
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Thomas Harte
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87a021ec2d
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Made further attempt to get as fas as having the Z80 attempt to do something.
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2017-05-16 22:19:40 -04:00 |
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Thomas Harte
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189317b80c
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Added enough of a Z80 test machine to bridge up into Swift.
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2017-05-16 22:05:42 -04:00 |
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Thomas Harte
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7190f927b7
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Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
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2017-05-16 21:28:17 -04:00 |
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Thomas Harte
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d559d8b901
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Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
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2017-05-16 21:19:17 -04:00 |
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Thomas Harte
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df80c37adb
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Renamed TestMachine to TestMachine6502 since there's going to be multiple of them.
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2017-05-15 08:18:57 -04:00 |
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Thomas Harte
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0808e9b6fb
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Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.
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2017-05-14 22:08:15 -04:00 |
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Thomas Harte
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b81a2cc273
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First tentative steps towards adding a Z80 implementation.
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2017-05-14 17:46:41 -04:00 |
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Thomas Harte
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e01f3f06c8
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Completed curly bracket movement.
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2017-03-26 14:34:47 -04:00 |
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Thomas Harte
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031a68000a
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Added a class to contain the Pitfall 2 pager and a skeleton of initial work.
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2017-03-18 22:08:47 -04:00 |
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Thomas Harte
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c3d82f88a5
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Tidied up and commented on the Activision stack implementation.
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2017-03-18 21:01:58 -04:00 |
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Thomas Harte
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c033bad0b9
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Here's MNetwork!
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2017-03-18 20:51:49 -04:00 |
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Thomas Harte
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c31d85f820
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Re-emplaced the MegaBoy. Also cut detritus from the main Atari header.
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2017-03-18 19:02:34 -04:00 |
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Thomas Harte
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217fbf257e
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CBS RAM Plus returns.
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2017-03-18 18:56:20 -04:00 |
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Thomas Harte
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0b611a14b9
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Tigervision paging returns.
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2017-03-18 18:50:13 -04:00 |
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Thomas Harte
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df6861c9dc
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Parker Bros paging is back.
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2017-03-18 18:21:01 -04:00 |
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Thomas Harte
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a4cd12394e
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Reinstated the Activision stack pager.
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2017-03-18 18:03:48 -04:00 |
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Thomas Harte
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bb3daaa99b
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Sought to reintroduce the Atari 8k paging scheme, at the same time deciding to do away with the copy and paste of holding on to ROM data.
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2017-03-18 15:04:01 -04:00 |
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Thomas Harte
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14a76af0d3
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Started trying to float out bus control to cartridges.
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2017-03-17 20:28:07 -04:00 |
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Thomas Harte
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57ec756f5b
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Started speccing out a unit test for Atari ROM analysis.
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2017-03-11 20:33:58 -05:00 |
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