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Author	SHA1	Message	Date
Thomas Harte	43ac20cbd2	Fix non-interlaced frame length.	2024-10-07 21:50:56 -04:00
Thomas Harte	2d90868f5c	Reinstitute cursor.	2024-10-07 21:13:44 -04:00
Thomas Harte	60987ae4a7	Round out interlaced output.	2024-10-07 20:53:41 -04:00
Thomas Harte	65c1d99120	Add, disable some logging.	2024-10-05 22:30:53 -04:00
Thomas Harte	35acf88847	Take a swing at adding an adjustment period.	2024-10-03 22:07:46 -04:00
Thomas Harte	45549b5fcd	Switch CRTC type.	2024-10-03 22:07:12 -04:00
Thomas Harte	2eb9fb6a08	Add faulty attempt at adjustment period.	2024-09-30 23:47:27 -04:00
Thomas Harte	0d0e1083e6	Fix potential out-of-bounds access.	2024-09-30 13:37:44 -04:00
Thomas Harte	e650f3772a	Limit vertical visibility.	2024-09-30 13:35:28 -04:00
Thomas Harte	e5ff4c65b7	Fix accidental skew, off-by-one end of line.	2024-09-30 13:20:18 -04:00
Thomas Harte	276809f76a	Stabilise image, albeit incorrectly.	2024-09-30 13:16:03 -04:00
Thomas Harte	5e3840c5f1	Attempt to skirt with coherence.	2024-09-29 23:08:39 -04:00
Thomas Harte	6eace2a3ef	Improve address counting.	2024-09-27 21:27:56 -04:00
Thomas Harte	7817b23857	Take a swing at vertical sync.	2024-09-27 21:14:57 -04:00
Thomas Harte	432854aeb5	Restore some form of visuals.	2024-09-26 22:08:22 -04:00
Thomas Harte	433c8f9c3c	Make negligible progress.	2024-09-25 19:30:08 -04:00
Thomas Harte	ea25dbfd1e	Begin CRTC rejig.	2024-09-23 21:11:54 -04:00
Thomas Harte	10f8318e79	Merge pull request #1404 from TomHarte/65816SquareD ... 65816: correct emulation-mode `[d], y`, `PEI` and `PLB`.	2024-09-21 21:46:00 -04:00
Thomas Harte	17ff0c4f65	Fix PLD/PLB sizes.	2024-09-21 21:28:38 -04:00
Thomas Harte	9abd653fb9	Avoid impossible clamps.	2024-09-21 21:25:49 -04:00
Thomas Harte	ff6753fcdf	PEI: don't page wrap.	2024-09-21 21:12:04 -04:00
Thomas Harte	a65551f652	Give PLB the same stack behaviour as PLD.	2024-09-21 21:08:02 -04:00
Thomas Harte	f0d807a0fe	Fix [d], y page-wrapping behaviour.	2024-09-21 20:49:59 -04:00
Thomas Harte	dfcdbe5b6a	Merge pull request #1402 from TomHarte/CPCInterruptTiming ... Pull CPC interrupt to start of hsync.	2024-09-12 21:12:02 -04:00
Thomas Harte	53e73238fd	Merge pull request #1403 from TomHarte/OricVSync ... Extend Oric vsync to four lines.	2024-09-12 21:08:51 -04:00
Thomas Harte	581454db69	Tweak mode latch time too.	2024-09-12 20:47:27 -04:00
Thomas Harte	63d501b629	Pull interrupt to start of hsync.	2024-09-12 20:45:28 -04:00
Thomas Harte	60bd877ed9	Merge pull request #1401 from TomHarte/OricVSync ... Add the Oric's v-sync hardware hack.	2024-09-10 21:18:03 -04:00
Thomas Harte	44574465c5	Extend vsync to four lines.	2024-09-10 21:06:49 -04:00
Thomas Harte	2b7382a014	Loop in vsync as a potential tape input.	2024-09-10 20:59:05 -04:00
Thomas Harte	584b6df40d	Tweak 60Hz period.	2024-09-10 20:43:01 -04:00
Thomas Harte	e55f61deb2	Add vsync getter.	2024-09-10 20:31:35 -04:00
Thomas Harte	a6c6a1c6da	Eliminate macros.	2024-09-10 20:29:34 -04:00
Thomas Harte	bdb5abe47b	Record updated version number.	2024-09-08 21:34:02 -04:00
Thomas Harte	dbe0ebc93e	Merge pull request #1400 from TomHarte/DelegateOrderTest ... Fix order of `if` tests.	2024-09-08 21:30:44 -04:00
Thomas Harte	1c2f66e855	Fix order of if tests.	2024-09-08 21:23:58 -04:00
Thomas Harte	7eee3f9e5e	Merge pull request #1399 from TomHarte/ElectronULARedux ... Replace Electron graphics generation with FPGA transcription.	2024-09-08 21:23:09 -04:00
Thomas Harte	b7f069e1bd	Add a colour burst.	2024-09-08 21:12:45 -04:00
Thomas Harte	51c8396e32	Fix faulty centring.	2024-09-08 21:06:59 -04:00
Thomas Harte	0efe649ca5	Post pixel clock.	2024-09-08 20:57:43 -04:00
Thomas Harte	75db0018bc	Add note on provenance.	2024-09-08 20:20:03 -04:00
Thomas Harte	2a9e1ea045	Use normal member naming convention.	2024-09-08 20:16:43 -04:00
Thomas Harte	8feb8aaadc	Reintroduce cropping, even if faulty.	2024-09-06 22:12:19 -04:00
Thomas Harte	b8f4385501	Fix palette generation.	2024-09-06 21:47:13 -04:00
Thomas Harte	d8b6d87a1c	Attempt colour.	2024-09-06 21:36:05 -04:00
Thomas Harte	f10702b3ca	Edge towards proper serialisation.	2024-09-06 21:01:30 -04:00
Thomas Harte	88248d7062	Fix base address, delays.	2024-09-06 20:55:26 -04:00
Thomas Harte	5ca1659bcc	Do just enough to get 1bpp fixed-palette pixels.	2024-09-06 20:36:27 -04:00
Thomas Harte	59530a12fd	Sub in basic transliteration of hoglet's FPGA.	2024-09-06 20:21:46 -04:00
Thomas Harte	aab2dd68b6	Substitute in a real-time video generator.	2024-09-06 20:18:29 -04:00