43 Commits

Author	SHA1	Message	Date
Thomas Harte	4f58664f97	Catch interrupt enables.	2024-04-07 22:08:12 -04:00
Thomas Harte	7d8a364658	Reimplement LDM and STM.	2024-04-04 21:59:18 -04:00
Thomas Harte	b19dcfd6dc	Take another run at shifts.	2024-04-02 21:57:46 -04:00
Thomas Harte	7c9715f00c	Change mind about carry behaviour.	2024-04-01 21:38:44 -04:00
Thomas Harte	7de92a9457	Slightly clean up shift code.	2024-04-01 21:24:49 -04:00
Thomas Harte	2e7c1acb88	Add note on confusion.	2024-03-28 10:34:46 -04:00
Thomas Harte	4fcb85d132	Cleave off most remaining reasons for failure.	2024-03-28 10:32:27 -04:00
Thomas Harte	72a645ec1e	Fix trans; take further crack at MEMC permissions.	2024-03-25 15:50:59 -04:00
Thomas Harte	521fca6089	Expose full bus to IOC dependents; add notes.	2024-03-25 11:07:44 -04:00
Thomas Harte	9ea3e547ee	Fix IRQ/FIQ return addresses.	2024-03-22 21:42:34 -04:00
Thomas Harte	ae6cf69449	Move responsibility for clock division; reinstate vsync interrupt.	2024-03-22 10:01:34 -04:00
Thomas Harte	bc27e3998d	Fix downward block data transfers.	2024-03-14 21:09:51 -04:00
Thomas Harte	c6b91559e1	Attempt to wire up timer interrupts.	2024-03-12 11:34:31 -04:00
Thomas Harte	6efc41ded7	Come to conclusion on R15; fix link values.	2024-03-12 10:42:09 -04:00
Thomas Harte	e9c5582fe1	Add note on ambiguity to be resolved.	2024-03-12 10:04:02 -04:00
Thomas Harte	8b3c0abe93	Take another swing at R15 as a destination.	2024-03-12 09:13:05 -04:00
Thomas Harte	971bfb2ecb	Unify subtractions.	2024-03-11 14:52:48 -04:00
Thomas Harte	e8c1e8fd3f	Fix RSB carry; unify set_pc.	2024-03-11 14:48:43 -04:00
Thomas Harte	830d70d3aa	Trust tests on immediate-opcode ROR 0; limit shift by register.	2024-03-10 23:38:31 -04:00
Thomas Harte	336292bc49	Further correct R15 as a destination.	2024-03-10 22:56:02 -04:00
Thomas Harte	bd62228cc6	The test set doesn't seem to do word rotation.	2024-03-10 22:40:37 -04:00
Thomas Harte	e9e1db7a05	Change LDR writeback to destination.	2024-03-10 22:29:19 -04:00
Thomas Harte	fbc273f114	Add invented model for tests.	2024-03-10 21:45:56 -04:00
Thomas Harte	a4cf86268e	Provide full access to stored registers.	2024-03-09 15:11:04 -05:00
Thomas Harte	fdef8901ab	Double down on uint32_t.	2024-03-08 14:13:34 -05:00
Thomas Harte	fa8fcd2218	Take another swing at popcount.	2024-03-07 14:28:31 -05:00
Thomas Harte	2a36d0fcbc	Adjust user-mode test.	2024-03-07 14:00:38 -05:00
Thomas Harte	0e92885ed5	Fix ad hoc popcount; ARM does carry 'backwards'.	2024-03-07 13:27:41 -05:00
Thomas Harte	a0f0f73bde	Fix MOV as unconditional branch.	2024-03-07 10:31:26 -05:00
Thomas Harte	108a056f1c	Execution now runs into a prefetch abort loop.	2024-03-06 15:05:24 -05:00
Thomas Harte	ba5f142515	Take further stab at TEQ PC, etc.	2024-03-05 10:55:44 -05:00
Thomas Harte	ed586e80bc	Don't write to the PC with logical operations.	2024-03-05 09:32:35 -05:00
Thomas Harte	230e9c6327	Obscure active.	2024-03-03 21:43:30 -05:00
Thomas Harte	11c4d2f09e	Add further exposition.	2024-03-03 21:38:27 -05:00
Thomas Harte	f2db1b4aae	Merge branch 'TiedDown' into PositiveExpression	2024-03-03 21:31:26 -05:00
Thomas Harte	b42a6e447d	Tie down more corners.	2024-03-03 21:29:53 -05:00
Thomas Harte	9fd7d5c10f	Switch test and meaning.	2024-03-03 14:34:21 -05:00
Thomas Harte	4e7963ee81	Clarify PC semantics; remove faulty underscore.	2024-03-03 14:11:02 -05:00
Thomas Harte	62da0dee7f	Unify reads.	2024-03-02 23:15:17 -05:00
Thomas Harte	1663d3d9d1	Introduce disaster of an attempted test run.	2024-03-02 22:40:12 -05:00
Thomas Harte	37499d493a	Fix model name.	2024-03-02 21:47:09 -05:00
Thomas Harte	e6f77a9b80	Add logical right-shift tests.	2024-03-01 18:06:54 -05:00
Thomas Harte	42ba6d1281	Relocate execution code appropriately.	2024-03-01 15:02:47 -05:00