2248 Commits

Author	SHA1	Message	Date
Thomas Harte	c6c6213460	Bifurcate the fetch-operand flow. ... Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.	2022-05-19 10:27:51 -04:00
Thomas Harte	29f6b02c04	Factor out register setup/testing, generalising the DIVU/DIVS flag check.	2022-05-18 21:13:34 -04:00
Thomas Harte	1bf7c0ae5f	Attempt better to avoid entering a second instruction.	2022-05-18 21:00:34 -04:00
Thomas Harte	44ae084794	Avoid the repeated .fill; reduces debug-build executor test time to 1.5s. ... i.e. eliminates about 95% of costs.	2022-05-18 17:10:23 -04:00
Thomas Harte	13a1809101	Avoid memset.	2022-05-18 17:00:35 -04:00
Thomas Harte	c35200fbd0	Shuffle mildly, primarily to avoid repeated 16mb allocations.	2022-05-18 16:59:37 -04:00
Thomas Harte	4a40581deb	Completes performance of NBCD D0.	2022-05-17 16:10:20 -04:00
Thomas Harte	3db2de7478	Works 68000 mk2 into the comparative tests. ... ... revealing that I've leant a little too hard on __LINE__.	2022-05-16 20:04:13 -04:00
Thomas Harte	b0518040b5	Plants the seek of a 68000 mark 2.	2022-05-16 11:44:16 -04:00
Thomas Harte	20a191f144	Switch to same tests, run through a more modern emulator.	2022-05-15 16:33:08 -04:00
Thomas Harte	f60f1932f2	Restrict DIVU and DIVS tests to those which are well-defined.	2022-05-14 20:28:54 -04:00
Thomas Harte	7f704fdae1	Improve README.	2022-05-13 16:28:56 -04:00
Thomas Harte	dd63a6b61e	Correct all [A/S/N]BCD tests.	2022-05-13 16:18:58 -04:00
Thomas Harte	1935d968c5	Add ability to suggest solutions.	2022-05-13 15:27:11 -04:00
Thomas Harte	84cfbaa0a4	Remove manual test count, now that all are being performed.	2022-05-13 11:00:26 -04:00
Thomas Harte	0d81992f6a	Move object creation.	2022-05-13 10:50:16 -04:00
Thomas Harte	6594b38567	Tidy up, and reduce for now to a summary report.	2022-05-13 08:02:20 -04:00
Thomas Harte	2e796f31d4	Support interrupts; documentation to come.	2022-05-12 20:52:24 -04:00
Thomas Harte	3d8f5d4302	Improve failure logging. ... This confirms that it's only the *BCDs and DIVU/DIVS in which I do not match the tests.	2022-05-12 20:23:32 -04:00
Thomas Harte	2fa6b2301b	Move string logic into Preinstruction.	2022-05-12 19:46:08 -04:00
Thomas Harte	4ba20132b9	Avoid repeated allocations on the new path, reducing total runtime by almost two thirds.	2022-05-12 16:35:41 -04:00
Thomas Harte	192513656a	After much guesswork, fix SBCD and thereby pass flamewing tests.	2022-05-12 11:39:01 -04:00
Thomas Harte	f3c1b1f052	Name flags, remove closing underscores on exposed data fields.	2022-05-12 08:19:41 -04:00
Thomas Harte	56ce1ec6e8	No need to subclass.	2022-05-11 21:25:38 -04:00
Thomas Harte	de168956e4	Fix tested operand order.	2022-05-11 16:44:39 -04:00
Thomas Harte	5b80844d81	Add a sanity test count, temporarily.	2022-05-11 16:34:28 -04:00
Thomas Harte	17add4b585	Introduce and overwhelmingly fail the flamewing BCD tests.	2022-05-11 15:19:39 -04:00
Thomas Harte	943c924382	Add missing: MOVE to/from USP, RESET.	2022-05-11 07:52:23 -04:00
Thomas Harte	ab8e1fdcbf	Take a swing at access faults and address errors.	2022-05-10 16:20:30 -04:00
Thomas Harte	f2a6a12f79	Remove further vestiges of timing.	2022-05-09 20:58:51 -04:00
Thomas Harte	0af8660181	Remove add_pc and decline_branch in favour of operation-specific signals.	2022-05-09 16:19:25 -04:00
Thomas Harte	330ec1b848	TODO is done.	2022-05-09 11:52:33 -04:00
Thomas Harte	8e5650fde9	Clean up Instruction.hpp.	2022-05-09 10:13:42 -04:00
Thomas Harte	539932dc56	Provide function codes. TODO: optionally.	2022-05-09 09:18:02 -04:00
Thomas Harte	5ab5e1270e	Fix test for new MOVEM semantics.	2022-05-09 09:17:48 -04:00
Thomas Harte	98cb9cc1eb	Fix CHK operand size.	2022-05-07 21:16:44 -04:00
Thomas Harte	bf8c97abbb	Permit TRAP, TRAPV and CHK to push the next PC rather than the current.	2022-05-07 20:32:39 -04:00
Thomas Harte	2b3900fd14	Fix LINK A7.	2022-05-07 08:15:26 -04:00
Thomas Harte	1defeca1ad	Implement RTS, RTR, RTE.	2022-05-06 12:30:49 -04:00
Thomas Harte	ac6a9ab631	Fix TAS Dn.	2022-05-06 12:23:04 -04:00
Thomas Harte	8176bb6f79	Expose issues with TST and TAS.	2022-05-06 12:18:56 -04:00
Thomas Harte	9c266d4316	Proceed to unimplemented TST.	2022-05-06 11:33:57 -04:00
Thomas Harte	d478a1b448	Proceed to next failure: PEA.	2022-05-06 10:04:20 -04:00
Thomas Harte	607ddd2f78	Preserve MOVEM order in Operation.	2022-05-06 09:45:06 -04:00
Thomas Harte	06fe320cc0	Correct source counting, but this leaves the operands still being the wrong way around.	2022-05-05 21:06:53 -04:00
Thomas Harte	d7d0a5c15e	Implement MOVEM to memory.	2022-05-05 18:51:29 -04:00
Thomas Harte	47f4bbeec6	Switch to a contiguous block of 16 registers.	2022-05-05 15:31:59 -04:00
Thomas Harte	70cdc2ca9f	Fix MOVEP to register. ... Advance to lack of MOVEM.	2022-05-05 12:37:47 -04:00
Thomas Harte	f63a872387	BTST does not write back.	2022-05-05 12:32:15 -04:00
Thomas Harte	46686b4b9c	Start testing move.	2022-05-04 20:38:56 -04:00