Thomas Harte
5aef81cf24
Commutes cross-platform #pragma marks to //MARK:s.
2017-11-12 15:59:11 -05:00
Thomas Harte
2e15fab651
Doubles down on <cX> over <X.h> for C includes, and usage of the namespace for those types and functions.
2017-11-11 15:28:40 -05:00
Thomas Harte
4cbc87a17d
Corrects out-of-order initialisations for the 1770, Atari 2600 joystick, Pitfall II bus extender, Microdisc and 6502.
2017-11-10 22:20:44 -05:00
Thomas Harte
e983854e71
Converts all uint8_t and uint16_t casts to the functional style.
2017-10-21 21:50:53 -04:00
Thomas Harte
ab2bcb939f
Separates 6502Base into its constituent parts.
2017-09-04 11:08:33 -04:00
Thomas Harte
de218611e4
Corrects possible confusion as documentation recommends Cycles(0) as default, but then gives Cycles(1).
2017-09-01 20:49:24 -04:00
Thomas Harte
b306776ba9
Removes from 6502.hpp all remaining implementation details, making it purely an interface document.
...
Though those details remain visible to files including 6502.hpp through necessity.
2017-09-01 19:46:29 -04:00
Thomas Harte
4af333d5ec
Tidies the 6502 template and folder hierarchy.
...
Specifically: there's now just the one .h file at the top level, giving a clear indication of what a user should read. That separates implementation from interface. It also devolves a lot more to the base class because doing so makes debug builds less of a hassle. The all-RAM 6502 has been shuffled off into a subfolder, to indicate that it's not something you necessarily need know about. Also general documentation improvements have been applied: incorrect citing of the recurring-template pattern has been removed and the meaning of the two BusHandler methods has now accrued at the bus handler.
2017-08-31 22:10:27 -04:00
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
Thomas Harte
42b5b66305
Remove the 6502's use of runtime polymorphism in favour of ordinary templating.
2017-08-16 11:56:52 -04:00
Thomas Harte
4abd62e62b
Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
2017-07-27 22:05:29 -04:00
Thomas Harte
37950143fc
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
Thomas Harte
8361756dc4
Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
2017-07-27 07:40:02 -04:00
Thomas Harte
279c369a1f
Switched to Cycles as the result from the 6502 perform_bus_operation, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.
2017-07-25 22:21:09 -04:00
Thomas Harte
75d67ee770
Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
2017-07-25 20:20:55 -04:00
Thomas Harte
a1e9a54765
Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
2017-07-25 20:09:13 -04:00
Thomas Harte
677ed463f0
Updated comment per new method name.
2017-07-24 21:19:49 -04:00
Thomas Harte
b82bef95f3
Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
2017-07-24 20:10:05 -04:00
Thomas Harte
2ff157cf7a
Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that.
2017-07-22 22:17:29 -04:00
Thomas Harte
83628b285b
Experimentally turned the 6502 into a clock receiver. No problem encountered.
2017-07-22 21:52:21 -04:00
Thomas Harte
1a811b1ab1
Eliminated the function call inherent to every decode, and also moved the fixed table of operations into a non-templated base class.
2017-06-03 22:19:35 -04:00
Thomas Harte
c26349624c
This, of course, should be inline to gain any benefit from the slightly-tortured private implementation.
2017-06-03 22:00:57 -04:00
Thomas Harte
b642d9f712
Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.
2017-06-03 21:54:42 -04:00
Thomas Harte
fd6623b5a5
Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
2017-06-03 21:22:16 -04:00
Thomas Harte
b304c3a4b9
Eliminated the 6502's reliance on the micro-op scheduler.
2017-06-03 20:30:07 -04:00
Thomas Harte
01f7394f7f
Corrected 6502 scheduling when flushing the pipeline.
2017-05-30 20:58:07 -04:00
Thomas Harte
5aa8b03349
Attempted to regularise the 6502 with the Z80 as to scheduling. I think that at least one bug remains.
2017-05-30 20:36:53 -04:00
Thomas Harte
a0189a6fe1
Switched to following the current program via address.
2017-05-30 18:49:40 -04:00
Thomas Harte
21d0602305
Restored the all RAM 6502's lack of power-on reset.
2017-05-17 21:43:40 -04:00
Thomas Harte
7190f927b7
Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
2017-05-16 21:28:17 -04:00
Thomas Harte
d559d8b901
Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
2017-05-16 21:19:17 -04:00
Thomas Harte
eb8a2de5d6
Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.
2017-05-15 07:38:59 -04:00
Thomas Harte
0808e9b6fb
Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.
2017-05-14 22:08:15 -04:00
Thomas Harte
b81a2cc273
First tentative steps towards adding a Z80 implementation.
2017-05-14 17:46:41 -04:00
Thomas Harte
defec2c9b0
Fixed: operation reads now fulfil the promise of seeding the value to be read with 0xff.
2017-03-26 20:56:27 -04:00
Thomas Harte
e01f3f06c8
Completed curly bracket movement.
2017-03-26 14:34:47 -04:00
Thomas Harte
55ce851bb2
Fixed types of the 8k cartridges, ensured the 6502 starts without an IRQ request history.
2017-03-18 17:04:01 -04:00
Thomas Harte
36b58d03b7
Formalised read bus value guarantee from the 6502, fixed missing clock signal wiring on the Atari cartridge class, reintroduced CommaVid support.
2017-03-18 14:46:46 -04:00
Thomas Harte
14a76af0d3
Started trying to float out bus control to cartridges.
2017-03-17 20:28:07 -04:00
Thomas Harte
5be22e2f8d
Switched to suffix underscores and underscores in general for instance variables.
2016-12-03 11:38:53 -05:00
Thomas Harte
7ad44f5152
Flipped order of conditional so as negligibly to improve prediction.
2016-10-31 22:17:18 -04:00
Thomas Harte
2452a3104f
Corrected test: hitting zero is sufficient. No need to cross it.
2016-10-30 20:24:30 -04:00
Thomas Harte
9309be229c
Moved cycle count test down to the only places where it may actually yield a different result.
2016-10-30 20:13:44 -04:00
Thomas Harte
a106018680
Fixed initial state: interrupt flag is initially low.
2016-10-28 21:22:03 -04:00
Thomas Harte
613b5b3f98
Switched to inverse storage of the interrupt flag so as to reduce logical burden when storing IRQ line history.
2016-10-28 20:52:43 -04:00
Thomas Harte
4408c60ef7
This too should continue, not break, since it doesn't schedule a memory access.
2016-10-27 18:32:21 -04:00
Thomas Harte
534b3d085d
Improved test reporting, attempted to resolve timing errors just introduced (i.e. to differentiate break/continue where a cycle may or may not be spent).
2016-10-27 08:41:44 -04:00
Thomas Harte
f84b66a5f4
Made an attempt to fix wake-from-WAIT.
2016-10-25 19:06:46 -04:00
Thomas Harte
4b18c76b84
Introduced a bifurcation between break and continue to signify whether a bus access takes place, necessitating a shift in the location of the bus access but allowing the conditional to be dropped. Need to test.
2016-10-25 18:45:53 -04:00
Thomas Harte
c253a4258f
Made minor restructuring changes, slightly to reduce number of conditionals per operation and to drop a big hint to the optimiser.
2016-10-25 18:34:24 -04:00
