Thomas Harte
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5119997122
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Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
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2017-05-30 22:41:23 -04:00 |
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Thomas Harte
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b5c1773d59
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Eliminated another conditional. Albeit a very predictable one.
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2017-05-30 22:15:43 -04:00 |
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Thomas Harte
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dfb5057342
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Moved repetition group conditions explicitly into the switch statement.
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2017-05-30 22:12:10 -04:00 |
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Thomas Harte
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7bddd294c9
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Resolved an unpredictable conditional and temporarily disabled the Zexalltest as part of the default suite, since it takes so long to run.
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2017-05-30 21:03:02 -04:00 |
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Thomas Harte
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01f7394f7f
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Corrected 6502 scheduling when flushing the pipeline.
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2017-05-30 20:58:07 -04:00 |
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Thomas Harte
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5aa8b03349
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Attempted to regularise the 6502 with the Z80 as to scheduling. I think that at least one bug remains.
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2017-05-30 20:36:53 -04:00 |
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Thomas Harte
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b5ad910b81
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Merge branch 'Z80' into StraightPointer
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2017-05-30 19:25:38 -04:00 |
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Thomas Harte
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da65bae86e
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Switched to supplying the bus operation by reference, go guarantee that it isn't null.
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2017-05-30 19:24:58 -04:00 |
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Thomas Harte
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a0189a6fe1
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Switched to following the current program via address.
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2017-05-30 18:49:40 -04:00 |
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Thomas Harte
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244b5ba3c2
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Added a proper termination condition for Zexall and, for now, a Mhz counter.
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2017-05-30 18:32:38 -04:00 |
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Thomas Harte
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960de7bd7b
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Marginally reduced test machine costs based on usage.
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2017-05-30 11:59:07 -04:00 |
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Thomas Harte
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c6185baa99
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Fixed R incrementation and attempted to make the status flags cheaper to write to.
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2017-05-29 22:23:19 -04:00 |
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Thomas Harte
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4d4695032c
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Discovered that Zexall is just really slow. Disabled the address sanitiser, and started working towards a verifiable end.
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2017-05-29 21:46:00 -04:00 |
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Thomas Harte
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9d29cefe75
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Evicted manual memory management.
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2017-05-29 21:44:33 -04:00 |
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Thomas Harte
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35f535b9a3
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Noodled around with initial state.
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2017-05-29 19:25:08 -04:00 |
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Thomas Harte
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6d22f6fcd5
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Having decided the bus operation error on 10 is probably in the test cases, decided to allow myself to skip that one comparison. Back to zero failing cases, and with no more useful information to derive from the FUSE test set for the time being.
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2017-05-29 17:17:17 -04:00 |
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Thomas Harte
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8bfaa487ce
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Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit).
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2017-05-29 17:13:24 -04:00 |
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Thomas Harte
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0d067d2f01
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Adjusted OTI/etc timing; 23 failures outstanding.
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2017-05-29 16:54:45 -04:00 |
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Thomas Harte
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d66755fd1e
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Corrected INI/D[r] timing. Down to 45 failures.
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2017-05-29 16:50:52 -04:00 |
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Thomas Harte
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267b2add9a
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Adjusted for where FUSE nominally places timestamps. Down to 92 failures.
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2017-05-29 16:44:07 -04:00 |
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Thomas Harte
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d290e3d99e
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Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!)
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2017-05-29 16:35:00 -04:00 |
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Thomas Harte
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a6a4c5a936
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Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures.
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2017-05-29 15:57:27 -04:00 |
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Thomas Harte
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8a8f0cef20
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With all intentional opcode entry points now covered, commuted XX into NOP to give proper meaning to otherwise undefined codes.
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2017-05-29 12:25:10 -04:00 |
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Thomas Harte
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91dc0d5f4a
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Adjusted HALT to issue never-ending M1 fetches on the next instruction.
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2017-05-29 12:20:33 -04:00 |
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Thomas Harte
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ed7b07c8b1
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Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct.
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2017-05-29 11:54:27 -04:00 |
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Thomas Harte
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3f880fa769
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Fixed [FD/DD][74/75], which always store H or L, never IXh, IXl, IYh or IYl.
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2017-05-29 11:44:26 -04:00 |
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Thomas Harte
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d83dd17738
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[DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed.
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2017-05-29 11:40:56 -04:00 |
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Thomas Harte
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9ade0dcae3
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One failure was just PUSH AF due to throwing away the 5 & 3 flags at the start. Switched to throwing them away at comparison.
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2017-05-29 11:06:23 -04:00 |
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Thomas Harte
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a329d85697
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Instituted memory value checks, flushing out seven new failures.
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2017-05-29 11:01:45 -04:00 |
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Thomas Harte
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c322410783
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Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation.
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2017-05-29 10:52:54 -04:00 |
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Thomas Harte
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b67331e018
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Fixing the OUT repetition group reduces the code to one failing test.
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2017-05-29 10:48:53 -04:00 |
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Thomas Harte
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a47b339668
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Made an attempt at OUT[I/D]R. 10 failures remaining. None of which, I guess, are due to unimplemented operations.
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2017-05-29 10:28:04 -04:00 |
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Thomas Harte
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ad56a9215c
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Implemented IN[I/D]x. 18 failures remaining.
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2017-05-29 10:12:33 -04:00 |
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Thomas Harte
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c56a5344b9
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Implemented CP[I/D]x.
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2017-05-29 08:54:00 -04:00 |
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Thomas Harte
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1f62cbe21a
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Reduced LD[I/D}{R} repetition.
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2017-05-29 08:24:10 -04:00 |
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Thomas Harte
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47845f8c19
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Tried to complete the LD[I/D]{R} group. 32 issues remain.
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2017-05-28 23:55:54 -04:00 |
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Thomas Harte
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409c82ce73
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Implemented RLD and RRD. 34 failures remaining.
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2017-05-28 16:46:27 -04:00 |
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Thomas Harte
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dc3f5b6211
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Fixed flag setting for LD A, I and LD A, R, and corrected typo affecting LD DE, (nn).
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2017-05-28 16:32:10 -04:00 |
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Thomas Harte
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fb02b77e63
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Implemented RETI/RETN. 40 warnings remaining.
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2017-05-28 16:07:25 -04:00 |
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Thomas Harte
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f974d54c7a
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Implemented IM. 48 failures remain.
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2017-05-28 15:55:21 -04:00 |
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Thomas Harte
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68978c6e25
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Implemented NEG and filled in the load/store and copy parts of the ED page that roll directly off the tongue. 53 issues outstanding.
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2017-05-28 15:47:48 -04:00 |
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Thomas Harte
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6e83b7d6df
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Attempted to add a proper exit condition for Zexall.
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2017-05-28 15:13:47 -04:00 |
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Thomas Harte
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5a4d448cc1
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Corrected logical flags; now down to 68 failures, all of them on the ED page.
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2017-05-28 15:09:58 -04:00 |
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Thomas Harte
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743eac8c55
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Implemented EXX to complete the base page. 83 failures.
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2017-05-28 14:55:14 -04:00 |
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Thomas Harte
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6b66c8f304
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Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84.
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2017-05-28 14:50:51 -04:00 |
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Thomas Harte
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c976fbfcd5
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Implemented the base-page IN and OUT instructions, bringing FUSE test failures down to 91.
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2017-05-28 14:20:05 -04:00 |
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Thomas Harte
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ed3e38ac31
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Performed some quick tidying.
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2017-05-28 00:12:42 -04:00 |
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Thomas Harte
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76f03900d2
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Implemented EX HL, (SP) so as, allowing for indexed pages, to bring issues below the psychological 100 barrier. To 99.
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2017-05-28 00:02:14 -04:00 |
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Thomas Harte
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035df316aa
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FUSE seems to have inconsistent ideas about where b3 and b5 come from in more-complicated BIT instructions. So I'm not testing them for now. Within that reality, reduced to 102 failures.
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2017-05-27 23:54:53 -04:00 |
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Thomas Harte
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9759a04c7d
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Timing fixes: the fetch-decode-execute pattern is now per-page, since that on [DD/FD]CB not only doesn't increment R but doesn't take four cycles, so is probably a normal read cycle. Adjusted timing all around.
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2017-05-27 23:54:06 -04:00 |
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