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11,820 Commits 8 Branches 121 Tags 496 MiB
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70 Commits

Author SHA1 Message Date
Thomas Harte
6b18d775ab Eliminate unused variables. 2024-03-12 21:53:26 -04:00
Thomas Harte
ca30cf6376 Eliminate surviving uses of old naming convention. 2024-01-16 14:18:29 -05:00
Thomas Harte
980ccbd45b Eliminate repetition macros. 2024-01-16 14:17:31 -05:00
Thomas Harte
cc635fd3ea Eliminate set_decimal_rotate_flags entirely. 2024-01-16 13:59:03 -05:00
Thomas Harte
fe34083ab8 Demacroise set_shift_flags, reduce casting. 2024-01-16 13:51:16 -05:00
Thomas Harte
ea4cc4c9b3 Convert set_rotate_flags and decline_conditional macros. 2024-01-16 13:40:44 -05:00
Thomas Harte
5b5ae69a18 Convert set_logical_flags and set_arithmetic_flags to lambdas. 2024-01-16 10:13:30 -05:00
Thomas Harte
de038fe28f Eliminate easy macros from Z80 implementation. 2024-01-16 09:43:41 -05:00
Thomas Harte
8578dfbf22 Eliminate various other errant spaces. 2023-05-16 16:40:09 -04:00
Thomas Harte
10cd2a36cf Avoid type-in-function-name, Z80 edition. 2023-05-10 18:42:19 -05:00
Thomas Harte
4ddbf095f3 Fully banish flush from the processors. 2022-07-12 10:49:53 -04:00
Thomas Harte
d80f03e369 Corrects longstanding deviation from naming convention. 2021-04-25 14:11:36 -04:00
Thomas Harte
77fcf52d27 Purely style: remove some redundant nullptrs. 2021-04-19 18:53:00 -04:00
Thomas Harte
79c2bc1fd7 Put the program counter on the bus during interrupt acknowledge. 2021-04-19 18:43:50 -04:00
Thomas Harte
7017324d60 r_step is obsolete now that I know that [DD/FD]CB don't have a refresh cycle. 2021-04-13 22:17:30 -04:00
Thomas Harte
deb5d69ac7 Consolidates macros. 2021-04-13 22:11:28 -04:00
Thomas Harte
5998f3b35b Corrects LD[I/D/IR/DR] timing. 
Macro cleanup to come.
 2021-04-13 20:00:18 -04:00
Thomas Harte
869567fdd9 Corrects EX (SP), HL breakdown. 2021-04-13 19:45:48 -04:00
Thomas Harte
b42780173a Establishes that there really is no Read4 and Read4Pre distinction. 
Will finish these unit tests, then clean up.
 2021-04-12 20:54:10 -04:00
Thomas Harte
947de2d54a Switches five-cycle read to a post hoc pause. 2021-04-12 17:17:08 -04:00
Thomas Harte
e82367def3 Switches to test-conformant behaviour for (IX/IY+n) opcode fetches. 2021-04-11 23:01:00 -04:00
Thomas Harte
9cde7c12ba Shifts responsibility for refresh into the fetch-decode-execute sequence. 2021-04-11 22:50:24 -04:00
Thomas Harte
015556cc91 Switch (ii+n) to Read4Pre. 2021-04-11 10:26:14 -04:00
Thomas Harte
b397059d5e Moves read time in Read4Pre. 2021-04-10 17:54:20 -04:00
Thomas Harte
e0736435f8 Makes assumption that the address bus just holds its value during an internal operation. 2021-04-10 12:00:53 -04:00
Thomas Harte
eacffa49f5 Exposes IR during 'internal' operations. 2021-04-08 22:22:26 -04:00
Thomas Harte
945a9da94f Adds further [[fallthrough]]s. 2020-06-19 23:44:20 -04:00
Thomas Harte
2477752fa4 Adds further [[fallthrough]] attributes. 2020-06-19 23:36:51 -04:00
Thomas Harte
267006782f Starts to add Qt target; resolves many build warnings. 2020-05-30 00:37:06 -04:00
Thomas Harte
512a52e88d Increases const correctness, marks some additional constructors as constexpr, switches std::atomic construction style. 2020-05-20 23:34:26 -04:00
Thomas Harte
11d936331d Attempts to preserve scheduled_program_counter_. 2020-05-13 23:58:04 -04:00
Thomas Harte
7c9d9ee048 Adds basic Z80 state. 2020-05-13 20:15:22 -04:00
Thomas Harte
25996ce180 Further doubles down on construction syntax for type conversions. 2020-05-09 23:00:39 -04:00
Thomas Harte
b971e2a42c Adds get_is_resetting to the Z80, eliminating the CPC's custom version. 2020-02-29 19:58:25 -05:00
Thomas Harte
01faffd5bf Corrects memptr behaviour of OTIR/OTDR and INIR/INDR. 
This seemingly perfects memptr.
 2020-02-27 20:55:43 -05:00
Thomas Harte
26de5be07c Corrects memptr behaviour of LDIR/LDDR and CPIR/CPDR. 2020-02-27 20:44:53 -05:00
Thomas Harte
87474d5916 Corrects memptr behaviour of OUT (C), 0. 2020-02-27 20:38:27 -05:00
Thomas Harte
06163165d9 Corrects memptr effect of LD rr, (nn). 2020-02-26 22:22:54 -05:00
Thomas Harte
ec82c075be Fixes memptr for IN C, (C). 2020-02-26 22:19:37 -05:00
Thomas Harte
3b0df172a7 Corrects memptr behaviour of JP nn. 2020-02-26 22:02:15 -05:00
Thomas Harte
7058dbc3cc Corrects memptr for LD HL, (nn). 2020-02-26 21:54:49 -05:00
Thomas Harte
b64de89d2d Corrects JR memptrs. 2020-02-26 21:47:34 -05:00
Thomas Harte
8878396339 Corrects DJNZ memptr behaviour. 2020-02-26 21:42:31 -05:00
Thomas Harte
3097c4ccae Improves MEMPTR testing and some results. 2020-02-24 23:32:18 -05:00
Thomas Harte
7959d243f6 Adds single-stepping. Of a kind. 2020-02-24 23:31:42 -05:00
Thomas Harte
3f3229851b Implements MEMPTR for IN. 2020-02-23 00:32:33 -05:00
Thomas Harte
1c154131f9 Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate. 2019-10-29 22:36:29 -04:00
Thomas Harte
4aeb9a7c56 Genericises RegisterPair. 2019-03-09 21:16:11 -05:00
Thomas Harte
0b14850467 Corrects some comments. 2018-06-24 23:02:36 -04:00
Thomas Harte
9a91ae38c1 Differentiates reasons for a read to be four cycles. 
Specifically, puts the enforced wait either before or after checking the wait line. More research may be required; it feels more likely to me that a forced post wait should complete the read then wait, but would that still count as a single machine cycle?
 2018-06-20 21:34:21 -04:00