Thomas Harte
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0fd8813ddb
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Attempts to tie an intelligent keyboard to the other end of its serial line.
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2019-10-16 23:21:14 -04:00 |
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Thomas Harte
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c352d8ae8c
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Adds a received_data_ register, that presently can never fill.
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2019-10-13 23:04:57 -04:00 |
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Thomas Harte
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530e831064
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Corrects transmission logic — exactly hitting write_data_time_remaining now works properly.
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2019-10-13 21:40:46 -04:00 |
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Thomas Harte
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8d87e9eb1c
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The ACIA actually has two clocks, though on an ST they're both 500,000 Hz.
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2019-10-13 21:32:34 -04:00 |
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Thomas Harte
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f86dc082bb
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Ensures serial lines know their writer's clock rate.
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2019-10-13 20:41:08 -04:00 |
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Thomas Harte
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d7982aa84e
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JustInTimeActors can now specify a clock divider.
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2019-10-13 18:19:39 -04:00 |
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Thomas Harte
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516d78f5a8
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Attempts to implement transmission interrupts and ClockingHint::Source.
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2019-10-12 23:46:57 -04:00 |
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Thomas Harte
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8b50a7d6e3
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Attempts mostly to implement 6850 output.
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2019-10-12 23:14:29 -04:00 |
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Thomas Harte
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4bf81d3b90
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Decodes the 6850 control register, and starts working on standardised serial ports.
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2019-10-12 18:19:55 -04:00 |
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Thomas Harte
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cd75978e4e
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Nudges 6850 towards coherence.
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2019-10-12 00:04:02 -04:00 |
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Thomas Harte
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d7ce2c26e8
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Adds an empty shell for the ACIA.
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2019-10-10 20:54:29 -04:00 |
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