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https://github.com/MoleskiCoder/EightBit.git
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Closer to C# version
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Adrian Conlon committed
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commit
f5d2ee2e0e
2 files changed
+39
-69
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@@ -139,6 +139,8 @@ namespace EightBit {
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[[nodiscard]] uint8_t increment(uint8_t operand);
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[[nodiscard]] uint8_t decrement(uint8_t operand);
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void call(register16_t destination) noexcept final;
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void disableInterrupts() noexcept final;
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void enableInterrupts() noexcept final;
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+37
-69
@@ -42,21 +42,30 @@ void EightBit::Intel8080::memoryWrite() noexcept {
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void EightBit::Intel8080::memoryRead() noexcept {
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ReadingMemory.fire();
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tick(2);
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requestMemory();
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IntelProcessor::memoryRead();
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releaseMemory();
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tick();
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ReadMemory.fire();
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tick();
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}
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void EightBit::Intel8080::memoryUpdate(int ticks) noexcept {
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WritingMemory.fire();
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tick(ticks);
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tick(ticks + 1);
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requestMemory();
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IntelProcessor::memoryWrite();
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releaseMemory();
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tick();
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WrittenMemory.fire();
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}
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void EightBit::Intel8080::call(register16_t destination) noexcept {
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tick();
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Processor::call(destination);
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}
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void EightBit::Intel8080::handleRESET() noexcept {
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IntelProcessor::handleRESET();
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disableInterrupts();
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@@ -303,7 +312,7 @@ void EightBit::Intel8080::xhtl(register16_t& exchange) {
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BUS().DATA() = exchange.low;
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exchange.low = MEMPTR().low;
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memoryUpdate();
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tick(15); // 2(memUpdate) + 1(memUpdate) + 15 = 18 total
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tick(2);
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}
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void EightBit::Intel8080::writePort(const uint8_t port) noexcept {
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@@ -313,9 +322,11 @@ void EightBit::Intel8080::writePort(const uint8_t port) noexcept {
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}
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void EightBit::Intel8080::writePort() noexcept {
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tick(3);
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requestIO();
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busWrite();
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releaseIO();;
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releaseIO();
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tick();
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}
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void EightBit::Intel8080::readPort(const uint8_t port) noexcept {
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@@ -324,21 +335,22 @@ void EightBit::Intel8080::readPort(const uint8_t port) noexcept {
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}
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void EightBit::Intel8080::readPort() noexcept {
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tick(2);
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requestIO();
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busRead();
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releaseIO();
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tick(2);
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}
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void EightBit::Intel8080::poweredStep() noexcept {
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if (UNLIKELY(lowered(RESET()))) {
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handleRESET();
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return;
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} else if (UNLIKELY(lowered(INT()) && m_interruptEnable)) {
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handleINT();
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} else if (UNLIKELY(lowered(HALT()))) {
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IntelProcessor::execute(0); // NOP
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} else {
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IntelProcessor::execute(fetchInstruction());
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return;
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}
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IntelProcessor::execute(fetchInstruction());
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}
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void EightBit::Intel8080::execute() noexcept {
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@@ -362,7 +374,6 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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case 0: // Relative jumps and assorted ops
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switch (y) {
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case 0: // NOP
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tick(4);
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break;
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}
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break;
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@@ -370,11 +381,10 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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switch (q) {
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case 0: // LD rp,nn
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fetchInto(RP(p));
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tick(10);
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break;
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case 1: // ADD HL,rp
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add(RP(p));
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tick(11);
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tick(6);
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break;
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default:
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UNREACHABLE;
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@@ -386,22 +396,18 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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switch (p) {
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case 0: // LD (BC),A
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IntelProcessor::memoryWrite(BC(), A());
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tick(7);
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break;
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case 1: // LD (DE),A
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IntelProcessor::memoryWrite(DE(), A());
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tick(7);
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break;
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case 2: // LD (nn),HL
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fetchShortAddress();
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setShort(HL());
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tick(16);
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break;
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case 3: // LD (nn),A
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fetchInto(MEMPTR());
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BUS().ADDRESS() = MEMPTR();
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IntelProcessor::memoryWrite(A());
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tick(13);
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break;
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default:
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UNREACHABLE;
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@@ -412,24 +418,20 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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case 0: // LD A,(BC)
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readMemoryIndirect(BC());
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A() = BUS().DATA();
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tick(7);
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break;
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case 1: // LD A,(DE)
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readMemoryIndirect(DE());
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A() = BUS().DATA();
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tick(7);
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break;
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case 2: // LD HL,(nn)
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fetchShortAddress();
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getShort();
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HL() = intermediate();
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tick(16);
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break;
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case 3: // LD A,(nn)
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fetchInto(MEMPTR());
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readMemoryIndirect();
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A() = BUS().DATA();
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tick(13);
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break;
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default:
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UNREACHABLE;
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@@ -450,28 +452,21 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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default:
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UNREACHABLE;
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}
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tick(6);
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tick();
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break;
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case 4: { // 8-bit INC
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auto operand = R(y);
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IntelProcessor::R(y, increment(operand));
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tick(5);
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if (UNLIKELY(y == 6)) // INC M: memRead(0) + memUpdate(1) + 5 + 4 = 10
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tick(4);
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IntelProcessor::R(y, increment(operand), 2);
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tick();
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break;
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} case 5: { // 8-bit DEC
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auto operand = R(y);
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IntelProcessor::R(y, decrement(operand));
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tick(5);
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if (UNLIKELY(y == 6)) // DEC M: memRead(0) + memUpdate(1) + 5 + 4 = 10
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tick(4);
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IntelProcessor::R(y, decrement(operand), 2);
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tick();
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break;
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} case 6: // 8-bit load immediate
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fetchByte();
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IntelProcessor::R(y, BUS().DATA());
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tick(7);
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if (UNLIKELY(y == 6)) // LD M,n: memUpdate(1) + 7 + 2 = 10
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tick(2);
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IntelProcessor::R(y, BUS().DATA(), 2);
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break;
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case 7: // Assorted operations on accumulator/flags
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switch (y) {
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@@ -502,7 +497,6 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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default:
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UNREACHABLE;
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}
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tick(4);
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break;
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default:
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UNREACHABLE;
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@@ -511,14 +505,9 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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case 1: // 8-bit loading
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if (UNLIKELY(z == 6 && y == 6)) { // Exception (replaces LD (HL), (HL))
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lowerHALT();
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tick(4);
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} else {
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IntelProcessor::R(y, R(z));
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tick(5);
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if (UNLIKELY(y == 6)) // MOV M,r: memUpdate(1) + 5 + 1 = 7
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tick(1);
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else if (UNLIKELY(z == 6)) // MOV r,M: memRead(0) + 5 + 2 = 7
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tick(2);
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tick();
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}
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break;
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case 2: { // Operate on accumulator and register/memory location
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@@ -551,42 +540,33 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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default:
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UNREACHABLE;
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}
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tick(4);
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if (UNLIKELY(z == 6)) // M operations take 3 extra cycles
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tick(3);
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break;
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}
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case 3:
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switch (z) {
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case 0: { // Conditional return
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const bool condition = convertCondition(y);
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if (condition) {
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tick();
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if (convertCondition(y))
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ret();
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tick(11);
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} else {
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tick(5);
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}
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break;
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}
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case 1: // POP & various ops
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switch (q) {
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case 0: // POP rp2[p]
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popInto(RP2(p));
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tick(10);
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break;
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case 1:
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switch (p) {
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case 0: // RET
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ret();
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tick(10);
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break;
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case 2: // JP HL
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Processor::jump(HL());
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tick(5);
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tick();
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break;
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case 3: // LD SP,HL
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SP() = HL();
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tick(5);
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tick(2);
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break;
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}
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break;
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@@ -596,65 +576,55 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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break;
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case 2: // Conditional jump
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jumpConditionalFlag(y);
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tick(10);
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break;
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case 3: // Assorted operations
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switch (y) {
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case 0: // JP nn
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fetchInto(MEMPTR());
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jump();
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tick(10);
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jumpIndirect();
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break;
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case 2: // OUT (n),A
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fetchByte();
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writePort(BUS().DATA());
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tick(10);
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break;
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case 3: // IN A,(n)
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fetchByte();
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readPort(BUS().DATA());
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A() = BUS().DATA();
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tick(10);
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break;
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case 4: // EX (SP),HL
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xhtl(HL());
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break;
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case 5: // EX DE,HL
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std::swap(DE(), HL());
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tick(5);
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tick();
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break;
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case 6: // DI
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disableInterrupts();
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tick(4);
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break;
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case 7: // EI
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enableInterrupts();
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tick(4);
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break;
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}
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break;
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case 4: { // Conditional call: CALL cc[y], nn
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const bool condition = convertCondition(y);
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fetchInto(MEMPTR());
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if (condition) {
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call();
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tick(17);
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if (convertCondition(y)) {
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IntelProcessor::call();
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} else {
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tick(11);
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tick();
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}
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break;
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}
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case 5: // PUSH & various ops
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switch (q) {
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case 0: // PUSH rp2[p]
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tick();
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pushShort(RP2(p));
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tick(11);
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break;
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case 1:
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switch (p) {
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case 0: // CALL nn
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callIndirect();
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tick(17);
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break;
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}
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break;
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@@ -693,12 +663,10 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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default:
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UNREACHABLE;
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}
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tick(7);
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break;
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}
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case 7: // Restart: RST y * 8
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restart(y << 3);
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tick(11);
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break;
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default:
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UNREACHABLE;
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