Adrian Conlon
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5e9014997a
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Upgraded to VS2019, default SDK.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-08-06 13:16:38 +01:00 |
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Adrian Conlon
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def1c58e9d
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Tidy project settings across the EightBit library to be more consistent.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-07-06 22:45:16 +01:00 |
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Adrian Conlon
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f5582df402
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Add some more M6502 documentation.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-05-05 10:30:33 +01:00 |
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Adrian Conlon
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1a0d3ad77a
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Go through all projects for configuration consistency.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-05-05 10:25:44 +01:00 |
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Adrian Conlon
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f0376fa81e
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Use macros to define our device pins.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-14 23:17:54 +00:00 |
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Adrian Conlon
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7f853ec73f
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Add missing 6502 pin events
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-14 08:26:27 +00:00 |
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Adrian Conlon
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92d23d82d6
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Start big refactor of device/CPU pin usage (to allow pin events throughout).
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-14 02:10:17 +00:00 |
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Adrian Conlon
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68030610d8
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Move to an event driven clock tick event for all CPUs
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-09 23:24:33 +00:00 |
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Adrian Conlon
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8b187e7614
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The clock still has to tick, even while held on RDY low, otherwise cycle timing won't work.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-09 09:05:12 +00:00 |
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Adrian Conlon
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a90ca6ba38
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Move RDY initialisation to the CPU power-on sequence. Not strictly correct, but OK.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-09 00:33:56 +00:00 |
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Adrian Conlon
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87d86bcd84
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Whoops: missed unneeded method declaration.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-09 00:08:03 +00:00 |
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Adrian Conlon
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01175cf9eb
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Add support for emulated SYNC and RDY lines. Untested, but feel close.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-08 23:55:27 +00:00 |
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Adrian Conlon
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047babbe7c
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Rearrange the RESET handler for cycle accuracy. Use more of the general interrupt handler, but with "dummy" stack write access.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-08 23:09:52 +00:00 |
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Adrian Conlon
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25321e78e7
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Now that HALT/RESET/NMI/IRQ and BRK have a unified architecture, I think this wraps up the instruction handler of the 6502.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-08 01:32:43 +00:00 |
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Adrian Conlon
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3faec680b0
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I think this fixes one of my NES issues. The fix-up required for the PC is handled by the fetchByte associated with the BRK instruction.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-07 01:28:23 +00:00 |
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Adrian Conlon
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d7763d8215
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Profile mode no longer exists on the 6502 test program.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-07 01:08:23 +00:00 |
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Adrian Conlon
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06e2a5c947
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Start unifying 6502 interrupt handling. NMI/IRQ/BRK are all doing mostly the same work.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-07 01:06:07 +00:00 |
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Adrian Conlon
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b7b7c93a77
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This tidies the last of 6502 cycle accurate instruction implementations.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 22:34:53 +00:00 |
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Adrian Conlon
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ad644f7013
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Tidy the 6502 instruction switch statement a little to lessen the width a little.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 20:51:13 +00:00 |
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Adrian Conlon
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c3d2ef51d9
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Cycle accuracy for a couple of the indexed write (store) instructions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 20:39:37 +00:00 |
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Adrian Conlon
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4d3be9e756
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Use correct boundary crossing conditional for Read/Modify/Write Absolute,X addressing mode.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 12:58:13 +00:00 |
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Adrian Conlon
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baf32cef89
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Get the memory access more correct for more of boundary crossing indexed addressing modes.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 12:17:43 +00:00 |
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Adrian Conlon
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a13ad5042a
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Correct constructions of register16_t: the structure is "#ifdef"ed for different endian arrangements.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 11:27:43 +00:00 |
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Adrian Conlon
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3749585398
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Cycle accuracy changes for BRK/RTI instructions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-06 11:13:49 +00:00 |
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Adrian Conlon
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3337f57747
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More cycle accuracy changes, concentrating on stack operations.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-05 23:21:43 +00:00 |
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Adrian Conlon
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f5125b2a35
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Add some documentation regarding instruction cycle timings.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-05 23:21:12 +00:00 |
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Adrian Conlon
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143e9a9e68
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More cycle accuracy changes:
1) implied instruction, pointless fetch
2) branch pointless fetch when condition is met
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-05 17:23:50 +00:00 |
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Adrian Conlon
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3b7cec9c69
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Spot a couple more addCycle patterns.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-04 09:17:59 +00:00 |
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Adrian Conlon
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d2e853f101
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Explicitly note implied addressing mode instructions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-04 08:20:23 +00:00 |
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Adrian Conlon
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556e06426e
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Further work on the slow migration to a cycle accurate 6502
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-03 01:04:12 +00:00 |
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Adrian Conlon
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6c582f6349
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Add a working(ish) 6502 ATX implementation.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-30 17:12:45 +00:00 |
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Adrian Conlon
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5ade05a689
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Add a bunch of undocumented 6502 instructions. Abandoned ATX implementation. Too poorly documented.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-30 12:01:23 +00:00 |
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Adrian Conlon
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815c99710a
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Add enough undocumented 6502 instructions to get through "nestest".
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-29 22:22:31 +00:00 |
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Adrian Conlon
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c136b306ab
|
Use the new busRead/Write processor methods to simplify the 6502 cycle counting.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-29 22:18:01 +00:00 |
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Adrian Conlon
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adb60a6e90
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Port the 6502 to the new bus architecture.
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2018-12-29 19:40:02 +00:00 |
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Adrian Conlon
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d6ebf00ccc
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Merge branch 'master' of https://github.com/MoleskiCoder/EightBit
|
2018-12-01 16:46:06 +00:00 |
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Adrian Conlon
|
679275e930
|
Correct Linux build errors.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2018-12-01 16:41:39 +00:00 |
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Adrian Conlon
|
dc477cd050
|
Use explicit enumeration types (improves type safety) where appropriate.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-01 15:24:29 +00:00 |
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Adrian Conlon
|
a940a29283
|
Unify build settings across all the EightBit libraries.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-28 21:24:51 +00:00 |
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Adrian Conlon
|
e156b1ff1a
|
Correct some more compilation warnings (across the whole EightBit project).
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-25 19:02:11 +00:00 |
|
Adrian Conlon
|
2de467dde8
|
Refactor the MOS6502 core:
* Use lambda, rather than std::bind, if reasonable
* Tidy construction
* Remove configuration etc. not needed for running Klaus Dormann 6502 tests
|
2018-11-18 13:52:43 +00:00 |
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Adrian Conlon
|
fdbb28828f
|
Apply the concept of powered components to the "board"
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-11 16:48:44 +00:00 |
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Adrian Conlon
|
003cea0d64
|
Make 6502 symbols code a little more like normal C++
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-04 13:27:43 +00:00 |
|
Adrian Conlon
|
8ef5d97366
|
Update boost from 1.65 -> 1.68
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-04 12:58:01 +00:00 |
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Adrian Conlon
|
68a785ceec
|
Add an address masking to the memory mapping structure.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-01 23:43:29 +00:00 |
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Adrian Conlon
|
7af81018c9
|
Modify rotate and shift instructions to be a little more understandable (6502/6809)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-01 19:47:21 +00:00 |
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Adrian Conlon
|
4dc0becb74
|
Refactor the 6502 implementation to be a lot more like the MC6809. Hopefully show bugs in the latter a little more easily.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-10-31 23:29:13 +00:00 |
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Adrian Conlon
|
fac2da9ac4
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Start refactoring CPU cores to use C++17/14 features. (This commit covers the 6502 and Z80)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-10-27 18:41:55 +01:00 |
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Adrian Conlon
|
8dbb3eafec
|
Switch to C++17 standard in all EightBit projects.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-10-27 14:28:14 +01:00 |
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Adrian Conlon
|
1b2ddd8843
|
Don't expose the bus via the CPU any more: if a component needs the bus, it should be prepared to hold a reference to it.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-10-20 20:52:41 +01:00 |
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