Adrian Conlon
|
79f3e3ac6c
|
Refactor the code to isolate the cycles parsing. Interesting speed up!
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-18 11:54:01 +01:00 |
|
Adrian Conlon
|
50cea1b81a
|
Some JSON C++ library example code "levelling"
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-17 18:36:27 +01:00 |
|
Adrian Conlon
|
500e65b895
|
Tidy up the code a little (including removing some no longer needed code).
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-13 23:33:08 +01:00 |
|
Adrian Conlon
|
4892ea95d3
|
Split load/parse of opcode tests.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-12 17:07:45 +01:00 |
|
Adrian Conlon
|
dcba8efc83
|
All experimentation on the effect of JSON parser reuser.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-12 10:10:45 +01:00 |
|
Adrian Conlon
|
31c3a57485
|
If I've bothered to try and implement the failing test, show the actual and expected events.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-11 23:56:20 +01:00 |
|
Adrian Conlon
|
77a2c08c20
|
Remove some build warnings.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-11 23:23:59 +01:00 |
|
Adrian Conlon
|
91221aa975
|
Try simdjson: bloody hell, that's fast!!
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-11 22:09:03 +01:00 |
|
Adrian Conlon
|
b5074ac48c
|
Create an overtly performance checking build.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-11 19:52:22 +01:00 |
|
Adrian Conlon
|
59d1e2789e
|
Whoops: missed reference to RapidJson
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-11 19:39:37 +01:00 |
|
Adrian Conlon
|
7a7b0046cd
|
Add an implementation that uses JsonCpp (pretty slow!)
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-11 19:13:05 +01:00 |
|
Adrian Conlon
|
f3f6452119
|
Add nlohmann json parser as an option to build.
1/2 speed, compared to boost.json
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-11 14:59:23 +01:00 |
|
Adrian Conlon
|
db106b1719
|
Performance: speed up message handling in TestRunner.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-11 11:41:50 +01:00 |
|
Adrian Conlon
|
5686906583
|
Add nodiscard attributes, where needed
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-11 10:43:33 +01:00 |
|
Adrian Conlon
|
4be61a9d54
|
Separate concerns a little between low level classes and high level classes in terms of report generation.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-11 10:20:18 +01:00 |
|
Adrian Conlon
|
760f5d5aec
|
Correct filler memoryRead accesses to use PC() rather than the last location read.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-10 21:35:26 +01:00 |
|
Adrian Conlon
|
6a59bfbcd8
|
First stab at using the Harte randomised processor tests. Some failures detected in the M6502 run.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-10 21:26:30 +01:00 |
|
Adrian Conlon
|
6c3ef821bf
|
Update for latest boost v1.77
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-10-10 21:25:21 +01:00 |
|
Adrian Conlon
|
22506ea56c
|
Extensive change warning: lots of "noexcept" and "constexpr" changes. Not sure if I'll keep all of them, but interesting...
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-07-18 14:28:40 +01:00 |
|
Adrian Conlon
|
2f76e901f9
|
More tidying of include files for VS2019 compatibility (plus more correct!)
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-05-29 12:18:13 +01:00 |
|
Adrian Conlon
|
cab29e3ce4
|
Tidy some code formatting. No functional changes.
|
2021-04-07 21:37:30 +01:00 |
|
Adrian Conlon
|
2992a0e78a
|
Event fire: use default arguments, where possible.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-04-07 21:36:53 +01:00 |
|
Adrian Conlon
|
2fa9ffd1e3
|
Tidy up some C++ a little
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-04-07 21:36:09 +01:00 |
|
Adrian Conlon
|
b1ca06447f
|
Ensure 6502 uses memory rather than bus read/write mechanism
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2021-03-08 16:44:09 +00:00 |
|
Adrian Conlon
|
6285a397ab
|
Tidy 6502 whitespace
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2020-02-22 09:02:37 +00:00 |
|
Adrian Conlon
|
c8bdabf34f
|
Reflect that the I/O for Intel style processors isn't part of the CPU, but attached to the Bus and access controlled by the CPU.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2020-02-09 11:51:58 +00:00 |
|
Adrian Conlon
|
d9466082ec
|
M-Cycle accurate Z80 modifications.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-12-29 01:18:54 +00:00 |
|
Adrian Conlon
|
d0467421ff
|
Improve compatibility with .net emulator code.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-11-09 18:58:23 +00:00 |
|
Adrian Conlon
|
ee3ecc682d
|
Add R/W pins to the MC6809 and MOS6502 processors. Hoping it'll ease peripheral development.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-09-15 12:49:32 +01:00 |
|
Adrian Conlon
|
254cfbe342
|
Tidied up pin management to be synchronised with the .Net code.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-09-06 23:55:57 +01:00 |
|
Adrian Conlon
|
6940a54355
|
Update all EightBit projects to VS2019 (Latest SDK, C++17)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-08-17 11:04:29 +01:00 |
|
Adrian Conlon
|
5e9014997a
|
Upgraded to VS2019, default SDK.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-08-06 13:16:38 +01:00 |
|
Adrian Conlon
|
def1c58e9d
|
Tidy project settings across the EightBit library to be more consistent.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-07-06 22:45:16 +01:00 |
|
Adrian Conlon
|
f5582df402
|
Add some more M6502 documentation.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-05-05 10:30:33 +01:00 |
|
Adrian Conlon
|
1a0d3ad77a
|
Go through all projects for configuration consistency.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-05-05 10:25:44 +01:00 |
|
Adrian Conlon
|
f0376fa81e
|
Use macros to define our device pins.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-14 23:17:54 +00:00 |
|
Adrian Conlon
|
7f853ec73f
|
Add missing 6502 pin events
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-14 08:26:27 +00:00 |
|
Adrian Conlon
|
92d23d82d6
|
Start big refactor of device/CPU pin usage (to allow pin events throughout).
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-14 02:10:17 +00:00 |
|
Adrian Conlon
|
68030610d8
|
Move to an event driven clock tick event for all CPUs
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-09 23:24:33 +00:00 |
|
Adrian Conlon
|
8b187e7614
|
The clock still has to tick, even while held on RDY low, otherwise cycle timing won't work.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-09 09:05:12 +00:00 |
|
Adrian Conlon
|
a90ca6ba38
|
Move RDY initialisation to the CPU power-on sequence. Not strictly correct, but OK.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-09 00:33:56 +00:00 |
|
Adrian Conlon
|
87d86bcd84
|
Whoops: missed unneeded method declaration.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-09 00:08:03 +00:00 |
|
Adrian Conlon
|
01175cf9eb
|
Add support for emulated SYNC and RDY lines. Untested, but feel close.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-08 23:55:27 +00:00 |
|
Adrian Conlon
|
047babbe7c
|
Rearrange the RESET handler for cycle accuracy. Use more of the general interrupt handler, but with "dummy" stack write access.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-08 23:09:52 +00:00 |
|
Adrian Conlon
|
25321e78e7
|
Now that HALT/RESET/NMI/IRQ and BRK have a unified architecture, I think this wraps up the instruction handler of the 6502.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-08 01:32:43 +00:00 |
|
Adrian Conlon
|
3faec680b0
|
I think this fixes one of my NES issues. The fix-up required for the PC is handled by the fetchByte associated with the BRK instruction.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-07 01:28:23 +00:00 |
|
Adrian Conlon
|
d7763d8215
|
Profile mode no longer exists on the 6502 test program.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-07 01:08:23 +00:00 |
|
Adrian Conlon
|
06e2a5c947
|
Start unifying 6502 interrupt handling. NMI/IRQ/BRK are all doing mostly the same work.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-07 01:06:07 +00:00 |
|
Adrian Conlon
|
b7b7c93a77
|
This tidies the last of 6502 cycle accurate instruction implementations.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 22:34:53 +00:00 |
|
Adrian Conlon
|
ad644f7013
|
Tidy the 6502 instruction switch statement a little to lessen the width a little.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 20:51:13 +00:00 |
|
Adrian Conlon
|
c3d2ef51d9
|
Cycle accuracy for a couple of the indexed write (store) instructions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 20:39:37 +00:00 |
|
Adrian Conlon
|
4d3be9e756
|
Use correct boundary crossing conditional for Read/Modify/Write Absolute,X addressing mode.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 12:58:13 +00:00 |
|
Adrian Conlon
|
baf32cef89
|
Get the memory access more correct for more of boundary crossing indexed addressing modes.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 12:17:43 +00:00 |
|
Adrian Conlon
|
a13ad5042a
|
Correct constructions of register16_t: the structure is "#ifdef"ed for different endian arrangements.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 11:27:43 +00:00 |
|
Adrian Conlon
|
3749585398
|
Cycle accuracy changes for BRK/RTI instructions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 11:13:49 +00:00 |
|
Adrian Conlon
|
3337f57747
|
More cycle accuracy changes, concentrating on stack operations.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-05 23:21:43 +00:00 |
|
Adrian Conlon
|
f5125b2a35
|
Add some documentation regarding instruction cycle timings.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-05 23:21:12 +00:00 |
|
Adrian Conlon
|
143e9a9e68
|
More cycle accuracy changes:
1) implied instruction, pointless fetch
2) branch pointless fetch when condition is met
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-05 17:23:50 +00:00 |
|
Adrian Conlon
|
3b7cec9c69
|
Spot a couple more addCycle patterns.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-04 09:17:59 +00:00 |
|
Adrian Conlon
|
d2e853f101
|
Explicitly note implied addressing mode instructions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-04 08:20:23 +00:00 |
|
Adrian Conlon
|
556e06426e
|
Further work on the slow migration to a cycle accurate 6502
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-03 01:04:12 +00:00 |
|
Adrian Conlon
|
6c582f6349
|
Add a working(ish) 6502 ATX implementation.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-30 17:12:45 +00:00 |
|
Adrian Conlon
|
5ade05a689
|
Add a bunch of undocumented 6502 instructions. Abandoned ATX implementation. Too poorly documented.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-30 12:01:23 +00:00 |
|
Adrian Conlon
|
815c99710a
|
Add enough undocumented 6502 instructions to get through "nestest".
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-29 22:22:31 +00:00 |
|
Adrian Conlon
|
c136b306ab
|
Use the new busRead/Write processor methods to simplify the 6502 cycle counting.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-29 22:18:01 +00:00 |
|
Adrian Conlon
|
adb60a6e90
|
Port the 6502 to the new bus architecture.
|
2018-12-29 19:40:02 +00:00 |
|
Adrian Conlon
|
d6ebf00ccc
|
Merge branch 'master' of https://github.com/MoleskiCoder/EightBit
|
2018-12-01 16:46:06 +00:00 |
|
Adrian Conlon
|
679275e930
|
Correct Linux build errors.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
|
2018-12-01 16:41:39 +00:00 |
|
Adrian Conlon
|
dc477cd050
|
Use explicit enumeration types (improves type safety) where appropriate.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-01 15:24:29 +00:00 |
|
Adrian Conlon
|
a940a29283
|
Unify build settings across all the EightBit libraries.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-28 21:24:51 +00:00 |
|
Adrian Conlon
|
e156b1ff1a
|
Correct some more compilation warnings (across the whole EightBit project).
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-25 19:02:11 +00:00 |
|
Adrian Conlon
|
2de467dde8
|
Refactor the MOS6502 core:
* Use lambda, rather than std::bind, if reasonable
* Tidy construction
* Remove configuration etc. not needed for running Klaus Dormann 6502 tests
|
2018-11-18 13:52:43 +00:00 |
|
Adrian Conlon
|
fdbb28828f
|
Apply the concept of powered components to the "board"
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-11 16:48:44 +00:00 |
|
Adrian Conlon
|
003cea0d64
|
Make 6502 symbols code a little more like normal C++
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-04 13:27:43 +00:00 |
|
Adrian Conlon
|
8ef5d97366
|
Update boost from 1.65 -> 1.68
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-04 12:58:01 +00:00 |
|
Adrian Conlon
|
68a785ceec
|
Add an address masking to the memory mapping structure.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-01 23:43:29 +00:00 |
|
Adrian Conlon
|
7af81018c9
|
Modify rotate and shift instructions to be a little more understandable (6502/6809)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-11-01 19:47:21 +00:00 |
|
Adrian Conlon
|
4dc0becb74
|
Refactor the 6502 implementation to be a lot more like the MC6809. Hopefully show bugs in the latter a little more easily.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-10-31 23:29:13 +00:00 |
|
Adrian Conlon
|
fac2da9ac4
|
Start refactoring CPU cores to use C++17/14 features. (This commit covers the 6502 and Z80)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-10-27 18:41:55 +01:00 |
|
Adrian Conlon
|
8dbb3eafec
|
Switch to C++17 standard in all EightBit projects.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-10-27 14:28:14 +01:00 |
|
Adrian Conlon
|
1b2ddd8843
|
Don't expose the bus via the CPU any more: if a component needs the bus, it should be prepared to hold a reference to it.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-10-20 20:52:41 +01:00 |
|
Adrian Conlon
|
337e35ca1b
|
Use the newly added CPU pokeWord method.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-10-14 20:39:09 +01:00 |
|
Adrian Conlon
|
fe3794e011
|
Simplify register16_t usage a little.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-09-16 12:00:29 +01:00 |
|
Adrian Conlon
|
7d840f1a42
|
Modifying the manner in which memory is mapped, allows a fairly clean mechanism for loading Intel "hex" files.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-09-15 14:35:59 +01:00 |
|
Adrian Conlon
|
97272d650d
|
Simplify processor bus access a little by further allowing register16_t address access.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-08-29 13:52:25 +01:00 |
|
Adrian Conlon
|
a8cc289149
|
Whoops: The "Bus" class *really* isn't allowed to know the "endianness" of the attached processor!
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-08-27 11:27:33 +01:00 |
|
Adrian Conlon
|
735f70e717
|
Remove a couple of unused headers from the 6502 processor.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-08-26 19:06:00 +01:00 |
|
Adrian Conlon
|
3a4235f651
|
Whoops: The NMI line needs to be powered on by individual processors now it's no longer part of the Processor base class.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-08-25 22:50:18 +01:00 |
|
Adrian Conlon
|
1212e8d4f0
|
Tidy some processor virtual specifications.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-08-25 13:35:53 +01:00 |
|
Adrian Conlon
|
535346dede
|
Whoops: missed UNLIKELY specifier on the 6502 processor
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-08-25 13:17:14 +01:00 |
|
Adrian Conlon
|
c105ee37bf
|
Have a stab at sorting out processor pin handling.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-08-25 12:09:26 +01:00 |
|
Adrian Conlon
|
6d4223c368
|
Start moving towards reset being just another style of interrupt.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-08-25 01:34:30 +01:00 |
|
Adrian Conlon
|
b0aacce406
|
Tidy header file usage a little.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-08-18 23:56:16 +01:00 |
|
Adrian Conlon
|
cc64e114a9
|
Start refactoring the processor classes to allow big/little endian processors to be specified.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-08-17 21:53:49 +01:00 |
|
Adrian Conlon
|
ed76038bfa
|
More memptr adjustments
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-08-17 13:59:59 +01:00 |
|
Adrian Conlon
|
70c70af969
|
Sort out some exception and member initialisation rules.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-08-11 21:19:19 +01:00 |
|
Adrian Conlon
|
e40240694f
|
More removal of duplicated code.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-06-24 22:33:02 +01:00 |
|
Adrian Conlon
|
cac871cf2b
|
Remove duplicated code (from const definitions) the performance benefit isn't worth the amount of duplicated code.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-06-24 20:58:20 +01:00 |
|
Adrian Conlon
|
d27b490d4c
|
(Hopefully) fix compilation issue on g++
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-06-16 09:53:44 +01:00 |
|
Adrian Conlon
|
67487b5b6e
|
Simplify the usage of the register16_t union.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-06-16 00:55:32 +01:00 |
|