6502/EightBitNet
1
0
Fork 0
mirror of https://github.com/MoleskiCoder/EightBitNet.git synced 2026-01-27 03:16:19 +00:00
Code Issues Projects Releases Wiki Activity

Share some more common code between Intel style procesors

Browse Source
This commit is contained in:
Adrian Conlon
2025-10-15 19:46:10 +01:00
parent 33fce45cc8
commit 1dfd9621a1
4 changed files with 38 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
EightBit/IntelProcessor.cs
View File

@@ -170,6 +170,35 @@ namespace EightBit
////
protected byte ReadMemoryIndirect(Register16 via)
{
this.MEMPTR.Assign(via);
return this.ReadMemoryIndirect();
}
protected byte ReadMemoryIndirect()
{
this.Bus.Address.Assign(this.MEMPTR);
this.MEMPTR.Increment();
return this.MemoryRead();
}
protected void WriteMemoryIndirect(Register16 via, byte data)
{
this.MEMPTR.Assign(via);
this.WriteMemoryIndirect(data);
}
protected void WriteMemoryIndirect(byte data)
{
this.Bus.Address.Assign(this.MEMPTR);
this.MEMPTR.Increment();
this.MEMPTR.High = this.Bus.Data = data;
this.MemoryWrite();
}
////
protected void Restart(byte address)
{
this.MEMPTR.Assign(address);

27
Intel8080/Intel8080.cs
View File

@@ -739,33 +739,6 @@ namespace Intel8080
this.Tick(2);
}
private byte ReadMemoryIndirect(Register16 via)
{
this.MEMPTR.Assign(via);
return this.ReadMemoryIndirect();
}
private byte ReadMemoryIndirect()
{
this.Bus.Address.Assign(this.MEMPTR);
this.MEMPTR.Increment();
return this.MemoryRead();
}
private void WriteMemoryIndirect(Register16 via, byte data)
{
this.MEMPTR.Assign(via);
this.WriteMemoryIndirect(data);
}
private void WriteMemoryIndirect(byte data)
{
this.Bus.Address.Assign(this.MEMPTR);
this.MEMPTR.Increment();
this.MEMPTR.High = this.Bus.Data = data;
this.MemoryWrite();
}
private void WritePort(byte port)
{
this.Bus.Address.Assign(port, this.A);

15
LR35902/LR35902.cs
View File

@@ -560,50 +560,53 @@ namespace LR35902
switch (p)
{
case 0: // LD (BC),A
this.Bus.Address.Assign(this.BC);
this.WriteMemoryIndirect(this.BC, A);
break;
case 1: // LD (DE),A
this.Bus.Address.Assign(this.DE);
this.WriteMemoryIndirect(this.DE, A);
break;
case 2: // GB: LDI (HL),A
this.Bus.Address.Assign(this.HL);
_ = this.HL.Increment();
this.MemoryWrite(this.A);
break;
case 3: // GB: LDD (HL),A
this.Bus.Address.Assign(this.HL);
_ = this.HL.Decrement();
this.MemoryWrite(this.A);
break;
default:
throw new InvalidOperationException("Invalid operation mode");
}
this.MemoryWrite(this.A);
break;
case 1:
switch(p)
{
case 0: // LD A,(BC)
this.Bus.Address.Assign(this.BC);
this.A = this.ReadMemoryIndirect(this.BC);
break;
case 1: // LD A,(DE)
this.Bus.Address.Assign(this.DE);
this.A = this.ReadMemoryIndirect(this.DE);
break;
case 2: // GB: LDI A,(HL)
this.Bus.Address.Assign(this.HL);
_ = this.HL.Increment();
this.A = this.MemoryRead();
break;
case 3: // GB: LDD A,(HL)
this.Bus.Address.Assign(this.HL);
_ = this.HL.Decrement();
this.A = this.MemoryRead();
break;
default:
throw new InvalidOperationException("Invalid operation mode");
}
this.A = this.MemoryRead();
break;
default:

27
Z80/Z80.cs
View File

@@ -2271,33 +2271,6 @@ namespace Z80
this.AdjustSZXY(this.A);
}
private byte ReadMemoryIndirect(Register16 via)
{
this.MEMPTR.Assign(via);
return this.ReadMemoryIndirect();
}
private byte ReadMemoryIndirect()
{
this.Bus.Address.Assign(this.MEMPTR);
this.MEMPTR.Increment();
return this.MemoryRead();
}
private void WriteMemoryIndirect(Register16 via, byte data)
{
this.MEMPTR.Assign(via);
this.WriteMemoryIndirect(data);
}
private void WriteMemoryIndirect(byte data)
{
this.Bus.Address.Assign(this.MEMPTR);
this.MEMPTR.Increment();
this.MEMPTR.High = this.Bus.Data = data;
this.MemoryWrite();
}
private void RRD()
{
var memory = ReadMemoryIndirect(this.HL);